Change in flashrom[master]: sb600spi.c: Don't access spibar directly
by Edward O'Callaghan (Code Review)
Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/36433 )
Change subject: sb600spi.c: Don't access spibar directly
......................................................................
sb600spi.c: Don't access spibar directly
Constrain the manner in which the global state of spibar is
set and then subsequently accessed. This makes it easier to
write unit-tests and instrument the code.
Change-Id: Ic26372b9c1baebb20716eea1db1e942239ed3e48
Signed-off-by: Edward O'Callaghan <quasisec(a)chromium.org>
---
M sb600spi.c
1 file changed, 53 insertions(+), 38 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/33/36433/1
diff --git a/sb600spi.c b/sb600spi.c
index 23b36ee..7bdd11f 100644
--- a/sb600spi.c
+++ b/sb600spi.c
@@ -40,7 +40,13 @@
*};
*/
-static uint8_t *sb600_spibar = NULL;
+static uint8_t *g_sb600_spibar = NULL;
+
+static inline uint8_t * get_spibar(void)
+{
+ return g_sb600_spibar;
+}
+
enum amd_chipset {
CHIPSET_AMD_UNKNOWN,
CHIPSET_SB6XX,
@@ -180,16 +186,18 @@
static void reset_internal_fifo_pointer(void)
{
- mmio_writeb(mmio_readb(sb600_spibar + 2) | 0x10, sb600_spibar + 2);
+ uint8_t *spibar = get_spibar();
+ mmio_writeb(mmio_readb(spibar + 2) | 0x10, spibar + 2);
/* FIXME: This loop needs a timeout and a clearer message. */
- while (mmio_readb(sb600_spibar + 0xD) & 0x7)
+ while (mmio_readb(spibar + 0xD) & 0x7)
msg_pspew("reset\n");
}
static int compare_internal_fifo_pointer(uint8_t want)
{
- uint8_t have = mmio_readb(sb600_spibar + 0xd) & 0x07;
+ uint8_t *spibar = get_spibar();
+ uint8_t have = mmio_readb(spibar + 0xd) & 0x07;
want %= FIFO_SIZE_OLD;
if (have != want) {
msg_perr("AMD SPI FIFO pointer corruption! Pointer is %d, wanted %d\n", have, want);
@@ -224,8 +232,9 @@
static void execute_command(void)
{
msg_pspew("Executing... ");
- mmio_writeb(mmio_readb(sb600_spibar + 2) | 1, sb600_spibar + 2);
- while (mmio_readb(sb600_spibar + 2) & 1)
+ uint8_t *spibar = get_spibar();
+ mmio_writeb(mmio_readb(spibar + 2) | 1, spibar + 2);
+ while (mmio_readb(spibar + 2) & 1)
;
msg_pspew("done\n");
}
@@ -239,7 +248,8 @@
unsigned char cmd = *writearr++;
writecnt--;
msg_pspew("%s, cmd=0x%02x, writecnt=%d, readcnt=%d\n", __func__, cmd, writecnt, readcnt);
- mmio_writeb(cmd, sb600_spibar + 0);
+ uint8_t *spibar = get_spibar();
+ mmio_writeb(cmd, spibar + 0);
int ret = check_readwritecnt(flash, writecnt, readcnt);
if (ret != 0)
@@ -253,14 +263,14 @@
*/
unsigned int readoffby1 = (writecnt > 0) ? 0 : 1;
uint8_t readwrite = (readcnt + readoffby1) << 4 | (writecnt);
- mmio_writeb(readwrite, sb600_spibar + 1);
+ mmio_writeb(readwrite, spibar + 1);
reset_internal_fifo_pointer();
msg_pspew("Filling FIFO: ");
unsigned int count;
for (count = 0; count < writecnt; count++) {
msg_pspew("[%02x]", writearr[count]);
- mmio_writeb(writearr[count], sb600_spibar + 0xC);
+ mmio_writeb(writearr[count], spibar + 0xC);
}
msg_pspew("\n");
if (compare_internal_fifo_pointer(writecnt))
@@ -291,7 +301,7 @@
/* Skip the bytes we sent. */
msg_pspew("Skipping: ");
for (count = 0; count < writecnt; count++) {
- msg_pspew("[%02x]", mmio_readb(sb600_spibar + 0xC));
+ msg_pspew("[%02x]", mmio_readb(spibar + 0xC));
}
msg_pspew("\n");
if (compare_internal_fifo_pointer(writecnt))
@@ -299,14 +309,14 @@
msg_pspew("Reading FIFO: ");
for (count = 0; count < readcnt; count++) {
- readarr[count] = mmio_readb(sb600_spibar + 0xC);
+ readarr[count] = mmio_readb(spibar + 0xC);
msg_pspew("[%02x]", readarr[count]);
}
msg_pspew("\n");
if (compare_internal_fifo_pointer(writecnt+readcnt))
return SPI_PROGRAMMER_ERROR;
- if (mmio_readb(sb600_spibar + 1) != readwrite) {
+ if (mmio_readb(spibar + 1) != readwrite) {
msg_perr("Unexpected change in AMD SPI read/write count!\n");
msg_perr("Something else is accessing the flash chip and causes random corruption.\n"
"Please stop all applications and drivers and IPMI which access the flash chip.\n");
@@ -325,21 +335,22 @@
unsigned char cmd = *writearr++;
writecnt--;
msg_pspew("%s, cmd=0x%02x, writecnt=%d, readcnt=%d\n", __func__, cmd, writecnt, readcnt);
- mmio_writeb(cmd, sb600_spibar + 0);
+ uint8_t *spibar = get_spibar();
+ mmio_writeb(cmd, spibar + 0);
int ret = check_readwritecnt(flash, writecnt, readcnt);
if (ret != 0)
return ret;
/* Use the extended TxByteCount and RxByteCount registers. */
- mmio_writeb(writecnt, sb600_spibar + 0x48);
- mmio_writeb(readcnt, sb600_spibar + 0x4b);
+ mmio_writeb(writecnt, spibar + 0x48);
+ mmio_writeb(readcnt, spibar + 0x4b);
msg_pspew("Filling buffer: ");
unsigned int count;
for (count = 0; count < writecnt; count++) {
msg_pspew("[%02x]", writearr[count]);
- mmio_writeb(writearr[count], sb600_spibar + 0x80 + count);
+ mmio_writeb(writearr[count], spibar + 0x80 + count);
}
msg_pspew("\n");
@@ -347,7 +358,7 @@
msg_pspew("Reading buffer: ");
for (count = 0; count < readcnt; count++) {
- readarr[count] = mmio_readb(sb600_spibar + 0x80 + (writecnt + count) % FIFO_SIZE_YANGTZE);
+ readarr[count] = mmio_readb(spibar + 0x80 + (writecnt + count) % FIFO_SIZE_YANGTZE);
msg_pspew("[%02x]", readarr[count]);
}
msg_pspew("\n");
@@ -375,16 +386,17 @@
{
bool success = false;
uint8_t speed = spispeed->speed;
+ uint8_t *spibar = get_spibar();
msg_pdbg("Setting SPI clock to %s (0x%x).\n", spispeed->name, speed);
if (amd_gen >= CHIPSET_YANGTZE) {
- rmmio_writew((speed << 12) | (speed << 8) | (speed << 4) | speed, sb600_spibar + 0x22);
- uint16_t tmp = mmio_readw(sb600_spibar + 0x22);
+ rmmio_writew((speed << 12) | (speed << 8) | (speed << 4) | speed, spibar + 0x22);
+ uint16_t tmp = mmio_readw(spibar + 0x22);
success = (((tmp >> 12) & 0xf) == speed && ((tmp >> 8) & 0xf) == speed &&
((tmp >> 4) & 0xf) == speed && ((tmp >> 0) & 0xf) == speed);
} else {
- rmmio_writeb((mmio_readb(sb600_spibar + 0xd) & ~(0x3 << 4)) | (speed << 4), sb600_spibar + 0xd);
- success = (speed == ((mmio_readb(sb600_spibar + 0xd) >> 4) & 0x3));
+ rmmio_writeb((mmio_readb(spibar + 0xd) & ~(0x3 << 4)) | (speed << 4), spibar + 0xd);
+ success = (speed == ((mmio_readb(spibar + 0xd) >> 4) & 0x3));
}
if (!success) {
@@ -396,11 +408,12 @@
static int set_mode(struct pci_dev *dev, uint8_t read_mode)
{
- uint32_t tmp = mmio_readl(sb600_spibar + 0x00);
+ uint8_t *spibar = get_spibar();
+ uint32_t tmp = mmio_readl(spibar + 0x00);
tmp &= ~(0x6 << 28 | 0x1 << 18); /* Clear mode bits */
tmp |= ((read_mode & 0x6) << 28) | ((read_mode & 0x1) << 18);
- rmmio_writel(tmp, sb600_spibar + 0x00);
- if (tmp != mmio_readl(sb600_spibar + 0x00))
+ rmmio_writel(tmp, spibar + 0x00);
+ if (tmp != mmio_readl(spibar + 0x00))
return 1;
return 0;
}
@@ -409,6 +422,7 @@
{
uint32_t tmp;
uint8_t spispeed_idx = 3; /* Default to 16.5 MHz */
+ uint8_t *spibar = get_spibar();
char *spispeed = extract_programmer_param("spispeed");
if (spispeed != NULL) {
@@ -450,7 +464,7 @@
"Normal (up to 66 MHz)", /* 6 */
"Fast Read", /* 7 (Not defined in the Bolton datasheet.) */
};
- tmp = mmio_readl(sb600_spibar + 0x00);
+ tmp = mmio_readl(spibar + 0x00);
uint8_t read_mode = ((tmp >> 28) & 0x6) | ((tmp >> 18) & 0x1);
msg_pdbg("SpiReadMode=%s (%i)\n", spireadmodes[read_mode], read_mode);
if (read_mode != 6) {
@@ -463,11 +477,11 @@
}
if (amd_gen >= CHIPSET_YANGTZE) {
- tmp = mmio_readb(sb600_spibar + 0x20);
+ tmp = mmio_readb(spibar + 0x20);
msg_pdbg("UseSpi100 is %sabled\n", (tmp & 0x1) ? "en" : "dis");
if ((tmp & 0x1) == 0) {
- rmmio_writeb(tmp | 0x1, sb600_spibar + 0x20);
- tmp = mmio_readb(sb600_spibar + 0x20) & 0x1;
+ rmmio_writeb(tmp | 0x1, spibar + 0x20);
+ tmp = mmio_readb(spibar + 0x20) & 0x1;
if (tmp == 0) {
msg_perr("Enabling Spi100 failed.\n");
return 1;
@@ -475,7 +489,7 @@
msg_pdbg("Enabling Spi100 succeeded.\n");
}
- tmp = mmio_readw(sb600_spibar + 0x22); /* SPI 100 Speed Config */
+ tmp = mmio_readw(spibar + 0x22); /* SPI 100 Speed Config */
msg_pdbg("NormSpeedNew is %s\n", spispeeds[(tmp >> 12) & 0xf].name);
msg_pdbg("FastSpeedNew is %s\n", spispeeds[(tmp >> 8) & 0xf].name);
msg_pdbg("AltSpeedNew is %s\n", spispeeds[(tmp >> 4) & 0xf].name);
@@ -483,15 +497,15 @@
}
} else {
if (amd_gen >= CHIPSET_SB89XX && amd_gen <= CHIPSET_HUDSON234) {
- bool fast_read = (mmio_readl(sb600_spibar + 0x00) >> 18) & 0x1;
+ bool fast_read = (mmio_readl(spibar + 0x00) >> 18) & 0x1;
msg_pdbg("Fast Reads are %sabled\n", fast_read ? "en" : "dis");
if (fast_read) {
msg_pdbg("Disabling them temporarily.\n");
- rmmio_writel(mmio_readl(sb600_spibar + 0x00) & ~(0x1 << 18),
- sb600_spibar + 0x00);
+ rmmio_writel(mmio_readl(spibar + 0x00) & ~(0x1 << 18),
+ spibar + 0x00);
}
}
- tmp = (mmio_readb(sb600_spibar + 0xd) >> 4) & 0x3;
+ tmp = (mmio_readb(spibar + 0xd) >> 4) & 0x3;
msg_pdbg("NormSpeed is %s\n", spispeeds[tmp].name);
}
return set_speed(dev, amd_gen, &spispeeds[spispeed_idx]);
@@ -581,14 +595,14 @@
return 0;
/* Physical memory has to be mapped at page (4k) boundaries. */
- sb600_spibar = rphysmap("SB600 SPI registers", tmp & 0xfffff000, 0x1000);
- if (sb600_spibar == ERROR_PTR)
+ g_sb600_spibar = rphysmap("SB600 SPI registers", tmp & 0xfffff000, 0x1000);
+ if (g_sb600_spibar == ERROR_PTR)
return ERROR_FATAL;
/* The low bits of the SPI base address are used as offset into
* the mapped page.
*/
- sb600_spibar += tmp & 0xfff;
+ g_sb600_spibar += tmp & 0xfff;
int amd_gen = determine_generation(dev);
if (amd_gen < 0)
@@ -649,7 +663,8 @@
*
* <1> see handle_speed
*/
- tmp = mmio_readl(sb600_spibar + 0x00);
+ uint8_t *spibar = get_spibar();
+ tmp = mmio_readl(spibar + 0x00);
msg_pdbg("(0x%08" PRIx32 ") SpiArbEnable=%i", tmp, (tmp >> 19) & 0x1);
if (amd_gen >= CHIPSET_YANGTZE)
msg_pdbg(", IllegalAccess=%i", (tmp >> 21) & 0x1);
@@ -679,7 +694,7 @@
}
if (amd_gen >= CHIPSET_SB89XX) {
- tmp = mmio_readb(sb600_spibar + 0x1D);
+ tmp = mmio_readb(spibar + 0x1D);
msg_pdbg("Using SPI_CS%d\n", tmp & 0x3);
/* FIXME: Handle SpiProtect* configuration on Yangtze. */
}
--
To view, visit https://review.coreboot.org/c/flashrom/+/36433
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Gerrit-Project: flashrom
Gerrit-Branch: master
Gerrit-Change-Id: Ic26372b9c1baebb20716eea1db1e942239ed3e48
Gerrit-Change-Number: 36433
Gerrit-PatchSet: 1
Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org>
Gerrit-MessageType: newchange
1 day, 2 hours
- 2
- 2
Change in flashrom[master]: sb600spi.c: Remove 'amd_gen' out of global state.
by Edward O'Callaghan (Code Review)
Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/36432 )
Change subject: sb600spi.c: Remove 'amd_gen' out of global state.
......................................................................
sb600spi.c: Remove 'amd_gen' out of global state.
Have 'determine_generation()' explicitly return 'amd_gen'
and then pass the state into what requires it. Thus making
the code more pure, easier to read and more unit-testable.
Change-Id: I99fbad9486123c6b921eab83756de54a53ddfa7a
Signed-off-by: Edward O'Callaghan <quasisec(a)chromium.org>
---
M sb600spi.c
1 file changed, 12 insertions(+), 13 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/32/36432/1
diff --git a/sb600spi.c b/sb600spi.c
index 8daaf03..23b36ee 100644
--- a/sb600spi.c
+++ b/sb600spi.c
@@ -51,7 +51,6 @@
CHIPSET_YANGTZE,
CHIPSET_PROMONTORY,
};
-static enum amd_chipset amd_gen = CHIPSET_AMD_UNKNOWN;
#define FIFO_SIZE_OLD 8
#define FIFO_SIZE_YANGTZE 71
@@ -110,7 +109,7 @@
/* Determine the chipset's version and identify the respective SMBUS device. */
static int determine_generation(struct pci_dev *dev)
{
- amd_gen = CHIPSET_AMD_UNKNOWN;
+ enum amd_chipset amd_gen = CHIPSET_AMD_UNKNOWN;
msg_pdbg2("Trying to determine the generation of the SPI interface... ");
if (dev->device_id == 0x438d) {
amd_gen = CHIPSET_SB6XX;
@@ -173,11 +172,10 @@
"Please report this to flashrom(a)flashrom.org and include this log and\n"
"the output of lspci -nnvx, thanks!\n",
__func__, dev->vendor_id, dev->device_id);
- if (amd_gen == CHIPSET_AMD_UNKNOWN) {
+ if (amd_gen == CHIPSET_AMD_UNKNOWN)
msg_perr("Could not determine chipset generation.");
- return -1;
- }
- return 0;
+
+ return amd_gen;
}
static void reset_internal_fifo_pointer(void)
@@ -373,7 +371,7 @@
{ "800 kHz", 0x07 },
};
-static int set_speed(struct pci_dev *dev, const struct spispeed *spispeed)
+static int set_speed(struct pci_dev *dev, enum amd_chipset amd_gen, const struct spispeed *spispeed)
{
bool success = false;
uint8_t speed = spispeed->speed;
@@ -407,7 +405,7 @@
return 0;
}
-static int handle_speed(struct pci_dev *dev)
+static int handle_speed(struct pci_dev *dev, enum amd_chipset amd_gen)
{
uint32_t tmp;
uint8_t spispeed_idx = 3; /* Default to 16.5 MHz */
@@ -496,10 +494,10 @@
tmp = (mmio_readb(sb600_spibar + 0xd) >> 4) & 0x3;
msg_pdbg("NormSpeed is %s\n", spispeeds[tmp].name);
}
- return set_speed(dev, &spispeeds[spispeed_idx]);
+ return set_speed(dev, amd_gen, &spispeeds[spispeed_idx]);
}
-static int handle_imc(struct pci_dev *dev)
+static int handle_imc(struct pci_dev *dev, enum amd_chipset amd_gen)
{
/* Handle IMC everywhere but sb600 which does not have one. */
if (amd_gen == CHIPSET_SB6XX)
@@ -592,7 +590,8 @@
*/
sb600_spibar += tmp & 0xfff;
- if (determine_generation(dev) < 0)
+ int amd_gen = determine_generation(dev);
+ if (amd_gen < 0)
return ERROR_NONFATAL;
/* How to read the following table and similar ones in this file:
@@ -725,10 +724,10 @@
return 0;
}
- if (handle_speed(dev) != 0)
+ if (handle_speed(dev, amd_gen) != 0)
return ERROR_FATAL;
- if (handle_imc(dev) != 0)
+ if (handle_imc(dev, amd_gen) != 0)
return ERROR_FATAL;
/* Starting with Yangtze the SPI controller got a different interface with a much bigger buffer. */
--
To view, visit https://review.coreboot.org/c/flashrom/+/36432
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Gerrit-Project: flashrom
Gerrit-Branch: master
Gerrit-Change-Id: I99fbad9486123c6b921eab83756de54a53ddfa7a
Gerrit-Change-Number: 36432
Gerrit-PatchSet: 1
Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org>
Gerrit-MessageType: newchange
2 days, 1 hour
- 5
- 15
Change in flashrom[master]: tests/: [RFC]: Implement unit-testing using mtest
by Edward O'Callaghan (Code Review)
Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/38954 )
Change subject: tests/: [RFC]: Implement unit-testing using mtest
......................................................................
tests/: [RFC]: Implement unit-testing using mtest
The following allows the use of a ultra minimal unit-testing
framework and includes an example that exercises the libflashrom
init self-check and tear-down.
Some work is needed to get include paths into a healthy state so
that inner logic can be instrumented however this sets the tone.
Change-Id: I18d68d3ace32b5be264aae2988a8ed84c779be43
Signed-off-by: Edward O'Callaghan <quasisec(a)google.com>
---
M meson.build
A tests/meson.build
A tests/selfcheck.c
3 files changed, 60 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/54/38954/1
diff --git a/meson.build b/meson.build
index 375089c..8a998d0 100644
--- a/meson.build
+++ b/meson.build
@@ -402,3 +402,10 @@
)
subdir('util')
+
+# unit-test framework
+munit_dep = dependency(
+ 'munit',
+ fallback: ['munit', 'munit_dep']
+)
+subdir('tests')
diff --git a/tests/meson.build b/tests/meson.build
new file mode 100644
index 0000000..af65a81
--- /dev/null
+++ b/tests/meson.build
@@ -0,0 +1,12 @@
+root_includes = include_directories(['../', '../subprojects'])
+
+srcs = files('selfcheck.c')
+
+flashrom_tests = executable('flashrom_unit_tests',
+ srcs,
+ include_directories : root_includes,
+ dependencies : munit_dep,
+ link_with : flashrom
+)
+
+test('munit test flashrom', flashrom_tests)
diff --git a/tests/selfcheck.c b/tests/selfcheck.c
new file mode 100644
index 0000000..abe88b1
--- /dev/null
+++ b/tests/selfcheck.c
@@ -0,0 +1,41 @@
+#include <stdlib.h>
+
+#include "munit/munit.h"
+
+#include "libflashrom.h"
+
+
+MunitResult self_check_test(const MunitParameter params[], void* user_data_or_fixture)
+{
+ //Programmer table miscompilation!
+ munit_assert(flashrom_init(1 /*perform_selfcheck*/) == 0);
+ munit_assert(flashrom_shutdown() == 0);
+
+ return MUNIT_OK;
+}
+
+MunitTest tests[] = {
+ {
+ (char *)"/self_check", /* name */
+ self_check_test, /* test */
+ NULL, /* setup */
+ NULL, /* tear_down */
+ MUNIT_TEST_OPTION_NONE, /* options */
+ NULL /* parameters */
+ },
+ /* Mark the end of the array with an entry where the test
+ * function is NULL */
+ { NULL, NULL, NULL, NULL, MUNIT_TEST_OPTION_NONE, NULL }
+};
+
+static const MunitSuite suite = {
+ (char *)"/basic", /* name */
+ tests, /* tests */
+ NULL, /* suites */
+ 1, /* iterations */
+ MUNIT_SUITE_OPTION_NONE /* options */
+};
+
+int main (int argc, char* argv[]) {
+ return munit_suite_main(&suite, (char*)"flashrom", argc, argv);
+}
--
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Gerrit-Project: flashrom
Gerrit-Branch: master
Gerrit-Change-Id: I18d68d3ace32b5be264aae2988a8ed84c779be43
Gerrit-Change-Number: 38954
Gerrit-PatchSet: 1
Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org>
Gerrit-MessageType: newchange
3 days, 6 hours
- 1
- 2
Change in flashrom[master]: ft2232_spi.c - Pack read cmd and nCS in one ftdi_write_data() call
by Simon Buhrow (Code Review)
Simon Buhrow has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/40748 )
Change subject: ft2232_spi.c - Pack read cmd and nCS in one ftdi_write_data() call
......................................................................
ft2232_spi.c - Pack read cmd and nCS in one ftdi_write_data() call
Every ftdi_write_data() call is quite time consuming as the ftdi-chip takes 2-3ms to respond.
As the comment already says: Minimize USB transfers by packing as many commands as possible together.
As I cannot see any reason to put read cmd and deassertion of nCS into seperated ftdi calls,
I packed them together to save programming time.
Signed-off-by: Simon Buhrow <simon.buhrow(a)posteo.de>
Change-Id: I3f76da3dd0124a0deec7f937dbc4b7dc488c8004
---
M ft2232_spi.c
1 file changed, 38 insertions(+), 40 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/48/40748/1
diff --git a/ft2232_spi.c b/ft2232_spi.c
index 9f4c7f0..b2f5e40 100644
--- a/ft2232_spi.c
+++ b/ft2232_spi.c
@@ -398,7 +398,10 @@
msg_perr("Unable to set latency timer (%s).\n", ftdi_get_error_string(ftdic));
}
- if (ftdi_write_data_set_chunksize(ftdic, 270)) {
+ if (ftdi_write_data_set_chunksize(ftdic, 280)) {
+ /* 280 Byte = (9 Byte CMD + 1 Byte WREN) + (9 Byte CMD + 1 Byte op) + 4 Byte Addr
+ * + 256 Byte PageWrite-data
+ with op: PageProgram or Erase; CMD: FTDI-Chip commands*/
msg_perr("Unable to set chunk size (%s).\n", ftdi_get_error_string(ftdic));
}
@@ -467,31 +470,26 @@
struct ftdi_context *ftdic = &ftdic_context;
static unsigned char *buf = NULL;
/* failed is special. We use bitwise ops, but it is essentially bool. */
- int i = 0, ret = 0, failed = 0;
- size_t bufsize;
- static size_t oldbufsize = 0;
+ static int i = 0;
+ int ret = 0, failed = 0;
if (writecnt > 65536 || readcnt > 65536)
return SPI_INVALID_LENGTH;
- /* buf is not used for the response from the chip. */
- bufsize = max(writecnt + 9, 260 + 9);
- /* Never shrink. realloc() calls are expensive. */
- if (!buf || bufsize > oldbufsize) {
- buf = realloc(buf, bufsize);
+ if (!buf) {
+ /* set buf size to hardware buffer size of ftdi*/
+ buf = realloc(buf, 4096);
if (!buf) {
msg_perr("Out of memory!\n");
/* TODO: What to do with buf? */
return SPI_GENERIC_ERROR;
}
- oldbufsize = bufsize;
}
/*
* Minimize USB transfers by packing as many commands as possible
- * together. If we're not expecting to read, we can assert CS#, write,
- * and deassert CS# all in one shot. If reading, we do three separate
- * operations.
+ * together. We can assert CS#, write, (read,)
+ * and deassert CS# all in one shot.
*/
msg_pspew("Assert CS#\n");
buf[i++] = SET_BITS_LOW;
@@ -506,44 +504,44 @@
i += writecnt;
}
- /*
- * Optionally terminate this batch of commands with a
- * read command, then do the fetch of the results.
- */
+ /* A optionally read command */
if (readcnt) {
buf[i++] = MPSSE_DO_READ;
buf[i++] = (readcnt - 1) & 0xff;
buf[i++] = ((readcnt - 1) >> 8) & 0xff;
- ret = send_buf(ftdic, buf, i);
- failed = ret;
- /* We can't abort here, we still have to deassert CS#. */
- if (ret)
- msg_perr("send_buf failed before read: %i\n", ret);
- i = 0;
- if (ret == 0) {
- /*
- * FIXME: This is unreliable. There's no guarantee that
- * we read the response directly after sending the read
- * command. We may be scheduled out etc.
- */
- ret = get_buf(ftdic, readarr, readcnt);
- failed |= ret;
- /* We can't abort here either. */
- if (ret)
- msg_perr("get_buf failed: %i\n", ret);
- }
}
msg_pspew("De-assert CS#\n");
buf[i++] = SET_BITS_LOW;
buf[i++] = cs_bits;
buf[i++] = pindir;
- ret = send_buf(ftdic, buf, i);
- failed |= ret;
- if (ret)
- msg_perr("send_buf failed at end: %i\n", ret);
- return failed ? -1 : 0;
+ if (writearr[0] == JEDEC_WREN) {
+ /* Return to get second op (Program or Erase) without resetting buf nor i*/
+ return 0;
+ } else {
+ ret = send_buf(ftdic, buf, i);
+ failed |= ret;
+ if (ret)
+ msg_perr("send_buf failed: %i\n", ret);
+ i = 0;
+
+ if (readcnt) {
+ if (ret == 0) {
+ /*
+ * FIXME: This is unreliable. There's no guarantee that
+ * we read the response directly after sending the read
+ * command. We may be scheduled out etc.
+ */
+ ret = get_buf(ftdic, readarr, readcnt);
+ failed |= ret;
+ /* We can't abort here either. */
+ if (ret)
+ msg_perr("get_buf failed: %i\n", ret);
+ }
+ }
+ return failed ? -1 : 0;
+ }
}
#endif
--
To view, visit https://review.coreboot.org/c/flashrom/+/40748
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Gerrit-Project: flashrom
Gerrit-Branch: master
Gerrit-Change-Id: I3f76da3dd0124a0deec7f937dbc4b7dc488c8004
Gerrit-Change-Number: 40748
Gerrit-PatchSet: 1
Gerrit-Owner: Simon Buhrow
Gerrit-MessageType: newchange
2 weeks, 2 days
- 3
- 8
Change in flashrom[master]: programmer: Introduce programmer alias mechanism
by Edward O'Callaghan (Code Review)
Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/38671 )
Change subject: programmer: Introduce programmer alias mechanism
......................................................................
programmer: Introduce programmer alias mechanism
Originally introduced in the downstream commit
ba0827acee4da6740133345f43aae386923bbaad .
This was originally authored by David Hendricks so that
the various flash peripheral in ChromeOS devices can be
flashed. For example,
flashrom -p ec -r ec.bin
flashrom -p host -r host.bin
Note that this requires,
`CONFIG_DEFAULT_PROGRAMMER=PROGRAMMER_INTERNAL make`
to be defined as build-time.
BUG=b:148755493
BRANCH=none
TEST=ran ./flashrom -p host --flash-name
Change-Id: I73766451cd8900a9e0fe08efc7a4d81b2a35ac8d
Signed-off-by: Edward O'Callaghan <quasisec(a)google.com>
---
M cli_classic.c
M it85spi.c
M linux_mtd.c
M linux_spi.c
M programmer.c
M programmer.h
6 files changed, 98 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/71/38671/1
diff --git a/cli_classic.c b/cli_classic.c
index 73cc417..d58562b 100644
--- a/cli_classic.c
+++ b/cli_classic.c
@@ -329,13 +329,51 @@
break;
}
}
- if (prog == PROGRAMMER_INVALID) {
+
+ for (i = 0; aliases[i].name; i++) {
+ name = aliases[i].name;
+ namelen = strlen(aliases[i].name);
+
+ if (strncmp(optarg, name, namelen))
+ continue;
+
+ switch (optarg[namelen]) {
+ case ':':
+ pparam = strdup(optarg + namelen + 1);
+ if (!strlen(pparam)) {
+ free(pparam);
+ pparam = NULL;
+ }
+ break;
+ case '\0':
+ break;
+ default:
+ /* The continue refers to the for-loop.
+ * It is here to be able to
+ * differentiate between foo and foobar.
+ */
+ continue;
+ }
+
+ alias = &aliases[i];
+ msg_gdbg("Programmer alias: \"%s\", parameter: "
+ " \"%s\",\n", alias->name, pparam);
+ break;
+ }
+
+ if ((prog == PROGRAMMER_INVALID) && !alias) {
fprintf(stderr, "Error: Unknown programmer \"%s\". Valid choices are:\n",
optarg);
list_programmers_linebreak(0, 80, 0);
msg_ginfo(".\n");
cli_classic_abort_usage(NULL);
}
+
+ if ((prog != PROGRAMMER_INVALID) && alias) {
+ fprintf(stderr, "Error: Alias cannot be used "
+ "with programmer name.\n");
+ cli_classic_abort_usage(NULL);
+ }
break;
case 'R':
/* print_version() is always called during startup. */
diff --git a/it85spi.c b/it85spi.c
index 5ce9193..47e2337 100644
--- a/it85spi.c
+++ b/it85spi.c
@@ -289,6 +289,9 @@
{
int ret;
+ if (!programming_ec())
+ return 1;
+
if (!(internal_buses_supported & BUS_FWH)) {
msg_pdbg("%s():%d buses not support FWH\n", __func__, __LINE__);
return 1;
diff --git a/linux_mtd.c b/linux_mtd.c
index d2df95e..bee7cc5 100644
--- a/linux_mtd.c
+++ b/linux_mtd.c
@@ -363,6 +363,9 @@
int dev_num = 0;
int ret = 1;
+ if (!programming_host())
+ return 1;
+
param = extract_programmer_param("dev");
if (param) {
char *endptr;
diff --git a/linux_spi.c b/linux_spi.c
index aa73c18..221a36e 100644
--- a/linux_spi.c
+++ b/linux_spi.c
@@ -78,6 +78,14 @@
const uint8_t mode = SPI_MODE_0;
const uint8_t bits = 8;
+ /*
+ * FIXME: There might be other programmers with flash memory (such as
+ * an EC) connected via SPI. For now we rely on the device's driver to
+ * distinguish it and assume generic SPI implies host.
+ */
+ if (!programming_host())
+ return 1;
+
p = extract_programmer_param("spispeed");
if (p && strlen(p)) {
speed_hz = (uint32_t)strtoul(p, &endp, 10) * 1000;
diff --git a/programmer.c b/programmer.c
index f4b4384..ffad784 100644
--- a/programmer.c
+++ b/programmer.c
@@ -128,6 +128,13 @@
return 0;
}
+struct programmer_alias aliases[] = {
+ { "ec", ALIAS_EC },
+ { "host", ALIAS_HOST },
+ { NULL },
+};
+struct programmer_alias *alias;
+
enum chipbustype get_buses_supported(void)
{
int i;
diff --git a/programmer.h b/programmer.h
index 3cf53b9..a7bd947 100644
--- a/programmer.h
+++ b/programmer.h
@@ -130,6 +130,44 @@
PROGRAMMER_INVALID /* This must always be the last entry. */
};
+enum alias_type {
+ ALIAS_NONE = 0, /* no alias (default) */
+ ALIAS_EC, /* embedded controller */
+ ALIAS_HOST, /* chipset / PCH / SoC / etc. */
+};
+
+struct programmer_alias {
+ const char *name;
+ enum alias_type type;
+};
+
+extern struct programmer_alias *alias;
+extern struct programmer_alias aliases[];
+
+/**
+ * This function returns 'true' if current flashrom invocation is programming
+ * NONE.
+ */
+static inline int programming_none(void) {
+ return alias && (alias->type == ALIAS_NONE);
+}
+
+/**
+ * This function returns 'true' if current flashrom invocation is programming
+ * the EC.
+ */
+static inline int programming_ec(void) {
+ return alias && (alias->type == ALIAS_EC);
+}
+
+/**
+ * This function returns 'true' if current flashrom invocation is programming
+ * the HOST.
+ */
+static inline int programming_host(void) {
+ return alias && (alias->type == ALIAS_HOST);
+}
+
enum programmer_type {
PCI = 1, /* to detect uninitialized values */
USB,
--
To view, visit https://review.coreboot.org/c/flashrom/+/38671
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Gerrit-Project: flashrom
Gerrit-Branch: master
Gerrit-Change-Id: I73766451cd8900a9e0fe08efc7a4d81b2a35ac8d
Gerrit-Change-Number: 38671
Gerrit-PatchSet: 1
Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org>
Gerrit-MessageType: newchange
1 month
- 4
- 10
Change in flashrom[master]: Add writeprotect support
by Edward O'Callaghan (Code Review)
Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/40325 )
Change subject: Add writeprotect support
......................................................................
Add writeprotect support
[NOT-FOR-MERGE-(yet)]: PoC WIP.
BUG=b:153800563
BRANCH=none
TEST=builds
Change-Id: Id93b5a1cb2da476fa8a7dde41d7b963024117474
Signed-off-by: Edward O'Callaghan <quasisec(a)google.com>
---
M Makefile
M cli_classic.c
M flash.h
M meson.build
A writeprotect.c
A writeprotect.h
6 files changed, 2,722 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/25/40325/1
diff --git a/Makefile b/Makefile
index a533acf..a1bf898 100644
--- a/Makefile
+++ b/Makefile
@@ -589,7 +589,7 @@
CHIP_OBJS = jedec.o stm50.o w39.o w29ee011.o \
sst28sf040.o 82802ab.o \
sst49lfxxxc.o sst_fwhub.o edi.o flashchips.o spi.o spi25.o spi25_statusreg.o \
- spi95.o opaque.o sfdp.o en29lv640b.o at45db.o
+ spi95.o opaque.o sfdp.o en29lv640b.o at45db.o writeprotect.o
###############################################################################
# Library code.
diff --git a/cli_classic.c b/cli_classic.c
index 73cc417..9e2d8e8 100644
--- a/cli_classic.c
+++ b/cli_classic.c
@@ -17,6 +17,7 @@
* GNU General Public License for more details.
*/
+#include <errno.h>
#include <stdio.h>
#include <fcntl.h>
#include <sys/stat.h>
@@ -27,6 +28,7 @@
#include "flashchips.h"
#include "fmap.h"
#include "programmer.h"
+#include "writeprotect.h"
#include "libflashrom.h"
static void cli_classic_usage(const char *name)
@@ -116,6 +118,8 @@
int list_supported_wiki = 0;
#endif
int flash_name = 0, flash_size = 0;
+ int set_wp_range = 0, set_wp_region = 0, set_wp_enable = 0,
+ set_wp_disable = 0, wp_status = 0, wp_list = 0;
int read_it = 0, write_it = 0, erase_it = 0, verify_it = 0;
int dont_verify_it = 0, dont_verify_all = 0, list_supported = 0, operation_specified = 0;
struct flashrom_layout *layout = NULL;
@@ -127,6 +131,12 @@
OPTION_FLASH_CONTENTS,
OPTION_FLASH_NAME,
OPTION_FLASH_SIZE,
+ OPTION_WP_STATUS,
+ OPTION_WP_SET_RANGE,
+ OPTION_WP_SET_REGION,
+ OPTION_WP_ENABLE,
+ OPTION_WP_DISABLE,
+ OPTION_WP_LIST,
};
int ret = 0;
@@ -150,6 +160,12 @@
{"flash-name", 0, NULL, OPTION_FLASH_NAME},
{"flash-size", 0, NULL, OPTION_FLASH_SIZE},
{"get-size", 0, NULL, OPTION_FLASH_SIZE}, // (deprecated): back compatibility.
+ {"wp-status", 0, 0, OPTION_WP_STATUS},
+ {"wp-range", 0, 0, OPTION_WP_SET_RANGE},
+ {"wp-region", 1, 0, OPTION_WP_SET_REGION},
+ {"wp-enable", optional_argument, 0, OPTION_WP_ENABLE},
+ {"wp-disable", 0, 0, OPTION_WP_DISABLE},
+ {"wp-list", 0, 0, OPTION_WP_LIST},
{"list-supported", 0, NULL, 'L'},
{"list-supported-wiki", 0, NULL, 'z'},
{"programmer", 1, NULL, 'p'},
@@ -169,6 +185,7 @@
char *tempstr = NULL;
char *pparam = NULL;
struct layout_include_args *include_args = NULL;
+ char *wp_mode_opt = NULL;
flashrom_set_log_callback((flashrom_log_callback *)&flashrom_print_cb);
@@ -283,6 +300,23 @@
cli_classic_validate_singleop(&operation_specified);
flash_size = 1;
break;
+ case OPTION_WP_STATUS:
+ wp_status = 1;
+ break;
+ case OPTION_WP_LIST:
+ wp_list = 1;
+ break;
+ case OPTION_WP_SET_RANGE:
+ set_wp_range = 1;
+ break;
+ case OPTION_WP_ENABLE:
+ set_wp_enable = 1;
+ if (optarg)
+ wp_mode_opt = strdup(optarg);
+ break;
+ case OPTION_WP_DISABLE:
+ set_wp_disable = 1;
+ break;
case 'L':
cli_classic_validate_singleop(&operation_specified);
list_supported = 1;
@@ -562,11 +596,19 @@
goto out_shutdown;
}
- if (!(read_it | write_it | verify_it | erase_it | flash_name | flash_size)) {
+ if (!(read_it | write_it | verify_it | erase_it | flash_name | flash_size
+ | set_wp_range | set_wp_region | set_wp_enable |
+ set_wp_disable | wp_status | wp_list )) {
msg_ginfo("No operations were specified.\n");
goto out_shutdown;
}
+ if (set_wp_enable && set_wp_disable) {
+ msg_ginfo("Error: --wp-enable and --wp-disable are mutually exclusive\n");
+ ret = 1;
+ goto out_shutdown;
+ }
+
if (flash_name) {
if (fill_flash->chip->vendor && fill_flash->chip->name) {
printf("vendor=\"%s\" name=\"%s\"\n",
@@ -583,6 +625,110 @@
goto out_shutdown;
}
+ if (wp_status) {
+ if (fill_flash->chip->wp && fill_flash->chip->wp->wp_status) {
+ ret |= fill_flash->chip->wp->wp_status(fill_flash);
+ } else {
+ msg_gerr("Error: write protect is not supported "
+ "on this flash chip.\n");
+ ret = 1;
+ }
+ goto out_shutdown;
+ }
+
+ /* Note: set_wp_disable should be done before setting the range */
+ if (set_wp_disable) {
+ if (fill_flash->chip->wp && fill_flash->chip->wp->disable) {
+ ret |= fill_flash->chip->wp->disable(fill_flash);
+ } else {
+ msg_gerr("Error: write protect is not supported "
+ "on this flash chip.\n");
+ ret = 1;
+ goto out_shutdown;
+ }
+ }
+
+ if (!ret && set_wp_enable) {
+ enum wp_mode wp_mode;
+
+ if (wp_mode_opt)
+ wp_mode = get_wp_mode(wp_mode_opt);
+ else
+ wp_mode = WP_MODE_HARDWARE; /* default */
+
+ if (wp_mode == WP_MODE_UNKNOWN) {
+ msg_gerr("Error: Invalid WP mode: \"%s\"\n", wp_mode_opt);
+ ret = 1;
+ goto out_shutdown;
+ }
+
+ if (fill_flash->chip->wp && fill_flash->chip->wp->enable) {
+ ret |= fill_flash->chip->wp->enable(fill_flash, wp_mode);
+ } else {
+ msg_gerr("Error: write protect is not supported "
+ "on this flash chip.\n");
+ ret = 1;
+ goto out_shutdown;
+ }
+ }
+
+ if (wp_list) {
+ msg_ginfo("Valid write protection ranges:\n");
+ if (fill_flash->chip->wp && fill_flash->chip->wp->list_ranges) {
+ ret |= fill_flash->chip->wp->list_ranges(fill_flash);
+ } else {
+ msg_gerr("Error: write protect is not supported "
+ "on this flash chip.\n");
+ ret = 1;
+ }
+ goto out_shutdown;
+ }
+
+ if (set_wp_range || set_wp_region) {
+ if (set_wp_range && set_wp_region) {
+ msg_gerr("Error: Cannot use both --wp-range and "
+ "--wp-region simultaneously.\n");
+ ret = 1;
+ goto out_shutdown;
+ }
+
+ if (!fill_flash->chip->wp || !fill_flash->chip->wp->set_range) {
+ msg_gerr("Error: write protect is not supported "
+ "on this flash chip.\n");
+ ret = 1;
+ goto out_shutdown;
+ }
+ }
+
+ /* Note: set_wp_range must happen before set_wp_enable */
+ if (set_wp_range) {
+ unsigned int start, len;
+ char *endptr = NULL;
+
+ if ((argc - optind) != 2) {
+ msg_gerr("Error: invalid number of arguments\n");
+ ret = 1;
+ goto out_shutdown;
+ }
+
+ /* FIXME: add some error checking */
+ start = strtoul(argv[optind], &endptr, 0);
+ if (errno == ERANGE || errno == EINVAL || *endptr != '\0') {
+ msg_gerr("Error: value \"%s\" invalid\n", argv[optind]);
+ ret = 1;
+ goto out_shutdown;
+ }
+
+ len = strtoul(argv[optind + 1], &endptr, 0);
+ if (errno == ERANGE || errno == EINVAL || *endptr != '\0') {
+ msg_gerr("Error: value \"%s\" invalid\n", argv[optind + 1]);
+ ret = 1;
+ goto out_shutdown;
+ }
+
+ ret |= fill_flash->chip->wp->set_range(fill_flash, start, len);
+ }
+
if (layoutfile) {
layout = get_global_layout();
} else if (ifd && (flashrom_layout_read_from_ifd(&layout, fill_flash, NULL, 0) ||
diff --git a/flash.h b/flash.h
index 2f0143b..fefca9d 100644
--- a/flash.h
+++ b/flash.h
@@ -235,6 +235,8 @@
int (*unlock) (struct flashctx *flash);
int (*write) (struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len);
int (*read) (struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len);
+ uint8_t (*read_status) (const struct flashctx *flash);
+ int (*write_status) (const struct flashctx *flash, int status);
struct voltage {
uint16_t min;
uint16_t max;
@@ -243,6 +245,8 @@
/* SPI specific options (TODO: Make it a union in case other bustypes get specific options.) */
uint8_t wrea_override; /**< override opcode for write extended address register */
+
+ struct wp *wp;
};
struct flashrom_flashctx {
diff --git a/meson.build b/meson.build
index 699370a..38bf671 100644
--- a/meson.build
+++ b/meson.build
@@ -350,6 +350,7 @@
srcs += 'udelay.c'
srcs += 'w29ee011.c'
srcs += 'w39.c'
+srcs += 'writeprotect.c'
mapfile = 'libflashrom.map'
vflag = '-Wl,--version-script,@0@/@1@'.format(meson.current_source_dir(), mapfile)
diff --git a/writeprotect.c b/writeprotect.c
new file mode 100644
index 0000000..f54ccad
--- /dev/null
+++ b/writeprotect.c
@@ -0,0 +1,2512 @@
+/*
+ * This file is part of the flashrom project.
+ *
+ * Copyright (C) 2010 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <stdlib.h>
+#include <string.h>
+#include <strings.h>
+
+#include "flash.h"
+#include "flashchips.h"
+#include "chipdrivers.h"
+#include "spi.h"
+#include "writeprotect.h"
+
+/*
+ * The following procedures rely on look-up tables to match the user-specified
+ * range with the chip's supported ranges. This turned out to be the most
+ * elegant approach since diferent flash chips use different levels of
+ * granularity and methods to determine protected ranges. In other words,
+ * be stupid and simple since clever arithmetic will not work for many chips.
+ */
+
+struct wp_range {
+ unsigned int start; /* starting address */
+ unsigned int len; /* len */
+};
+
+enum bit_state {
+ OFF = 0,
+ ON = 1,
+ X = -1 /* don't care. Must be bigger than max # of bp. */
+};
+
+/*
+ * Generic write-protection schema for 25-series SPI flash chips. This assumes
+ * there is a status register that contains one or more consecutive bits which
+ * determine which address range is protected.
+ */
+
+struct status_register_layout {
+ int bp0_pos; /* position of BP0 */
+ int bp_bits; /* number of block protect bits */
+ int srp_pos; /* position of status register protect enable bit */
+};
+
+/*
+ * The following ranges and functions are useful for representing the
+ * writeprotect schema in which there are typically 5 bits of
+ * relevant information stored in status register 1:
+ * m.sec: This bit indicates the units (sectors vs. blocks)
+ * m.tb: The top-bottom bit indicates if the affected range is at the top of
+ * the flash memory's address space or at the bottom.
+ * bp: Bitmask representing the number of affected sectors/blocks.
+ */
+struct wp_range_descriptor {
+ struct modifier_bits m;
+ unsigned int bp; /* block protect bitfield */
+ struct wp_range range;
+};
+
+struct wp_context {
+ struct status_register_layout sr1; /* status register 1 */
+ struct wp_range_descriptor *descrs;
+
+ /*
+ * Some chips store modifier bits in one or more special control
+ * registers instead of the status register like many older SPI NOR
+ * flash chips did. get_modifier_bits() and set_modifier_bits() will do
+ * any chip-specific operations necessary to get/set these bit values.
+ */
+ int (*get_modifier_bits)(const struct flashctx *flash,
+ struct modifier_bits *m);
+ int (*set_modifier_bits)(const struct flashctx *flash,
+ struct modifier_bits *m);
+};
+
+struct w25q_status {
+ /* this maps to register layout -- do not change ordering */
+ unsigned char busy : 1;
+ unsigned char wel : 1;
+ unsigned char bp0 : 1;
+ unsigned char bp1 : 1;
+ unsigned char bp2 : 1;
+ unsigned char tb : 1;
+ unsigned char sec : 1;
+ unsigned char srp0 : 1;
+} __attribute__ ((packed));
+
+/* Status register for large flash layouts with 4 BP bits */
+struct w25q_status_large {
+ unsigned char busy : 1;
+ unsigned char wel : 1;
+ unsigned char bp0 : 1;
+ unsigned char bp1 : 1;
+ unsigned char bp2 : 1;
+ unsigned char bp3 : 1;
+ unsigned char tb : 1;
+ unsigned char srp0 : 1;
+} __attribute__ ((packed));
+
+struct w25q_status_2 {
+ unsigned char srp1 : 1;
+ unsigned char qe : 1;
+ unsigned char rsvd : 6;
+} __attribute__ ((packed));
+
+int w25_range_to_status(const struct flashctx *flash,
+ unsigned int start, unsigned int len,
+ struct w25q_status *status);
+int w25_status_to_range(const struct flashctx *flash,
+ const struct w25q_status *status,
+ unsigned int *start, unsigned int *len);
+
+/*
+ * Mask to extract write-protect enable and range bits
+ * Status register 1:
+ * SRP0: bit 7
+ * range(BP2-BP0): bit 4-2
+ * range(BP3-BP0): bit 5-2 (large chips)
+ * Status register 2:
+ * SRP1: bit 1
+ */
+#define MASK_WP_AREA (0x9C)
+#define MASK_WP_AREA_LARGE (0x9C)
+#define MASK_WP2_AREA (0x01)
+
+struct wp_range_descriptor en25f40_ranges[] = {
+ { .m = { .sec = X, .tb = X }, 0, {0, 0} }, /* none */
+ { .m = { .sec = 0, .tb = 0 }, 0x1, {0x000000, 504 * 1024} },
+ { .m = { .sec = 0, .tb = 0 }, 0x2, {0x000000, 496 * 1024} },
+ { .m = { .sec = 0, .tb = 0 }, 0x3, {0x000000, 480 * 1024} },
+ { .m = { .sec = 0, .tb = 0 }, 0x4, {0x000000, 448 * 1024} },
+ { .m = { .sec = 0, .tb = 0 }, 0x5, {0x000000, 384 * 1024} },
+ { .m = { .sec = 0, .tb = 0 }, 0x6, {0x000000, 256 * 1024} },
+ { .m = { .sec = 0, .tb = 0 }, 0x7, {0x000000, 512 * 1024} },
+};
+
+struct wp_range_descriptor en25q40_ranges[] = {
+ { .m = { .sec = 0, .tb = 0 }, 0, {0, 0} }, /* none */
+ { .m = { .sec = 0, .tb = 0 }, 0x1, {0x000000, 504 * 1024} },
+ { .m = { .sec = 0, .tb = 0 }, 0x2, {0x000000, 496 * 1024} },
+ { .m = { .sec = 0, .tb = 0 }, 0x3, {0x000000, 480 * 1024} },
+
+ { .m = { .sec = 0, .tb = 1 }, 0x0, {0x000000, 448 * 1024} },
+ { .m = { .sec = 0, .tb = 1 }, 0x1, {0x000000, 384 * 1024} },
+ { .m = { .sec = 0, .tb = 1 }, 0x2, {0x000000, 256 * 1024} },
+ { .m = { .sec = 0, .tb = 1 }, 0x3, {0x000000, 512 * 1024} },
+};
+
+struct wp_range_descriptor en25q80_ranges[] = {
+ { .m = { .sec = 0, .tb = 0 }, 0, {0, 0} }, /* none */
+ { .m = { .sec = 0, .tb = 0 }, 0x1, {0x000000, 1016 * 1024} },
+ { .m = { .sec = 0, .tb = 0 }, 0x2, {0x000000, 1008 * 1024} },
+ { .m = { .sec = 0, .tb = 0 }, 0x3, {0x000000, 992 * 1024} },
+ { .m = { .sec = 0, .tb = 0 }, 0x4, {0x000000, 960 * 1024} },
+ { .m = { .sec = 0, .tb = 0 }, 0x5, {0x000000, 896 * 1024} },
+ { .m = { .sec = 0, .tb = 0 }, 0x6, {0x000000, 768 * 1024} },
+ { .m = { .sec = 0, .tb = 0 }, 0x7, {0x000000, 1024 * 1024} },
+};
+
+struct wp_range_descriptor en25q32_ranges[] = {
+ { .m = { .sec = 0, .tb = 0 }, 0, {0, 0} }, /* none */
+ { .m = { .sec = 0, .tb = 0 }, 0x1, {0x000000, 4032 * 1024} },
+ { .m = { .sec = 0, .tb = 0 }, 0x2, {0x000000, 3968 * 1024} },
+ { .m = { .sec = 0, .tb = 0 }, 0x3, {0x000000, 3840 * 1024} },
+ { .m = { .sec = 0, .tb = 0 }, 0x4, {0x000000, 3584 * 1024} },
+ { .m = { .sec = 0, .tb = 0 }, 0x5, {0x000000, 3072 * 1024} },
+ { .m = { .sec = 0, .tb = 0 }, 0x6, {0x000000, 2048 * 1024} },
+ { .m = { .sec = 0, .tb = 0 }, 0x7, {0x000000, 4096 * 1024} },
+
+ { .m = { .sec = 0, .tb = 1 }, 0, {0, 0} }, /* none */
+ { .m = { .sec = 0, .tb = 1 }, 0x1, {0x010000, 4032 * 1024} },
+ { .m = { .sec = 0, .tb = 1 }, 0x2, {0x020000, 3968 * 1024} },
+ { .m = { .sec = 0, .tb = 1 }, 0x3, {0x040000, 3840 * 1024} },
+ { .m = { .sec = 0, .tb = 1 }, 0x4, {0x080000, 3584 * 1024} },
+ { .m = { .sec = 0, .tb = 1 }, 0x5, {0x100000, 3072 * 1024} },
+ { .m = { .sec = 0, .tb = 1 }, 0x6, {0x200000, 2048 * 1024} },
+ { .m = { .sec = 0, .tb = 1 }, 0x7, {0x000000, 4096 * 1024} },
+};
+
+struct wp_range_descriptor en25q64_ranges[] = {
+ { .m = { .sec = 0, .tb = 0 }, 0, {0, 0} }, /* none */
+ { .m = { .sec = 0, .tb = 0 }, 0x1, {0x000000, 8128 * 1024} },
+ { .m = { .sec = 0, .tb = 0 }, 0x2, {0x000000, 8064 * 1024} },
+ { .m = { .sec = 0, .tb = 0 }, 0x3, {0x000000, 7936 * 1024} },
+ { .m = { .sec = 0, .tb = 0 }, 0x4, {0x000000, 7680 * 1024} },
+ { .m = { .sec = 0, .tb = 0 }, 0x5, {0x000000, 7168 * 1024} },
+ { .m = { .sec = 0, .tb = 0 }, 0x6, {0x000000, 6144 * 1024} },
+ { .m = { .sec = 0, .tb = 0 }, 0x7, {0x000000, 8192 * 1024} },
+
+ { .m = { .sec = 0, .tb = 1 }, 0, {0, 0} }, /* none */
+ { .m = { .sec = 0, .tb = 1 }, 0x1, {0x010000, 8128 * 1024} },
+ { .m = { .sec = 0, .tb = 1 }, 0x2, {0x020000, 8064 * 1024} },
+ { .m = { .sec = 0, .tb = 1 }, 0x3, {0x040000, 7936 * 1024} },
+ { .m = { .sec = 0, .tb = 1 }, 0x4, {0x080000, 7680 * 1024} },
+ { .m = { .sec = 0, .tb = 1 }, 0x5, {0x100000, 7168 * 1024} },
+ { .m = { .sec = 0, .tb = 1 }, 0x6, {0x200000, 6144 * 1024} },
+ { .m = { .sec = 0, .tb = 1 }, 0x7, {0x000000, 8192 * 1024} },
+};
+
+struct wp_range_descriptor en25q128_ranges[] = {
+ { .m = { .sec = 0, .tb = 0 }, 0, {0, 0} }, /* none */
+ { .m = { .sec = 0, .tb = 0 }, 0x1, {0x000000, 16320 * 1024} },
+ { .m = { .sec = 0, .tb = 0 }, 0x2, {0x000000, 16256 * 1024} },
+ { .m = { .sec = 0, .tb = 0 }, 0x3, {0x000000, 16128 * 1024} },
+ { .m = { .sec = 0, .tb = 0 }, 0x4, {0x000000, 15872 * 1024} },
+ { .m = { .sec = 0, .tb = 0 }, 0x5, {0x000000, 15360 * 1024} },
+ { .m = { .sec = 0, .tb = 0 }, 0x6, {0x000000, 14336 * 1024} },
+ { .m = { .sec = 0, .tb = 0 }, 0x7, {0x000000, 16384 * 1024} },
+
+ { .m = { .sec = 0, .tb = 1 }, 0, {0, 0} }, /* none */
+ { .m = { .sec = 0, .tb = 1 }, 0x1, {0x010000, 16320 * 1024} },
+ { .m = { .sec = 0, .tb = 1 }, 0x2, {0x020000, 16256 * 1024} },
+ { .m = { .sec = 0, .tb = 1 }, 0x3, {0x040000, 16128 * 1024} },
+ { .m = { .sec = 0, .tb = 1 }, 0x4, {0x080000, 15872 * 1024} },
+ { .m = { .sec = 0, .tb = 1 }, 0x5, {0x100000, 15360 * 1024} },
+ { .m = { .sec = 0, .tb = 1 }, 0x6, {0x200000, 14336 * 1024} },
+ { .m = { .sec = 0, .tb = 1 }, 0x7, {0x000000, 16384 * 1024} },
+};
+
+struct wp_range_descriptor en25s64_ranges[] = {
+ { .m = { .sec = 0, .tb = 0 }, 0, {0, 0} }, /* none */
+ { .m = { .sec = 0, .tb = 0 }, 0x1, {0x000000, 8064 * 1024} },
+ { .m = { .sec = 0, .tb = 0 }, 0x2, {0x000000, 7936 * 1024} },
+ { .m = { .sec = 0, .tb = 0 }, 0x3, {0x000000, 7680 * 1024} },
+ { .m = { .sec = 0, .tb = 0 }, 0x4, {0x000000, 7168 * 1024} },
+ { .m = { .sec = 0, .tb = 0 }, 0x5, {0x000000, 6144 * 1024} },
+ { .m = { .sec = 0, .tb = 0 }, 0x6, {0x000000, 4096 * 1024} },
+ { .m = { .sec = 0, .tb = 0 }, 0x7, {0x000000, 8192 * 1024} },
+
+ { .m = { .sec = 0, .tb = 1 }, 0, {0, 0} }, /* none */
+ { .m = { .sec = 0, .tb = 1 }, 0x1, {0x7e0000, 128 * 1024} },
+ { .m = { .sec = 0, .tb = 1 }, 0x2, {0x7c0000, 256 * 1024} },
+ { .m = { .sec = 0, .tb = 1 }, 0x3, {0x780000, 512 * 1024} },
+ { .m = { .sec = 0, .tb = 1 }, 0x4, {0x700000, 1024 * 1024} },
+ { .m = { .sec = 0, .tb = 1 }, 0x5, {0x600000, 2048 * 1024} },
+ { .m = { .sec = 0, .tb = 1 }, 0x6, {0x400000, 4096 * 1024} },
+ { .m = { .sec = 0, .tb = 1 }, 0x7, {0x000000, 8192 * 1024} },
+};
+
+/* mx25l1005 ranges also work for the mx25l1005c */
+static struct wp_range_descriptor mx25l1005_ranges[] = {
+ { .m = { .sec = X, .tb = X }, 0, {0, 0} }, /* none */
+ { .m = { .sec = X, .tb = X }, 0x1, {0x010000, 64 * 1024} },
+ { .m = { .sec = X, .tb = X }, 0x2, {0x000000, 128 * 1024} },
+ { .m = { .sec = X, .tb = X }, 0x3, {0x000000, 128 * 1024} },
+};
+
+static struct wp_range_descriptor mx25l2005_ranges[] = {
+ { .m = { .sec = X, .tb = X }, 0, {0, 0} }, /* none */
+ { .m = { .sec = X, .tb = X }, 0x1, {0x030000, 64 * 1024} },
+ { .m = { .sec = X, .tb = X }, 0x2, {0x020000, 128 * 1024} },
+ { .m = { .sec = X, .tb = X }, 0x3, {0x000000, 256 * 1024} },
+};
+
+static struct wp_range_descriptor mx25l4005_ranges[] = {
+ { .m = { .sec = X, .tb = X }, 0, {0, 0} }, /* none */
+ { .m = { .sec = X, .tb = X }, 0x1, {0x070000, 64 * 1 * 1024} }, /* block 7 */
+ { .m = { .sec = X, .tb = X }, 0x2, {0x060000, 64 * 2 * 1024} }, /* blocks 6-7 */
+ { .m = { .sec = X, .tb = X }, 0x3, {0x040000, 64 * 4 * 1024} }, /* blocks 4-7 */
+ { .m = { .sec = X, .tb = X }, 0x4, {0x000000, 512 * 1024} },
+ { .m = { .sec = X, .tb = X }, 0x5, {0x000000, 512 * 1024} },
+ { .m = { .sec = X, .tb = X }, 0x6, {0x000000, 512 * 1024} },
+ { .m = { .sec = X, .tb = X }, 0x7, {0x000000, 512 * 1024} },
+};
+
+static struct wp_range_descriptor mx25l8005_ranges[] = {
+ { .m = { .sec = X, .tb = X }, 0, {0, 0} }, /* none */
+ { .m = { .sec = X, .tb = X }, 0x1, {0x0f0000, 64 * 1 * 1024} }, /* block 15 */
+ { .m = { .sec = X, .tb = X }, 0x2, {0x0e0000, 64 * 2 * 1024} }, /* blocks 14-15 */
+ { .m = { .sec = X, .tb = X }, 0x3, {0x0c0000, 64 * 4 * 1024} }, /* blocks 12-15 */
+ { .m = { .sec = X, .tb = X }, 0x4, {0x080000, 64 * 8 * 1024} }, /* blocks 8-15 */
+ { .m = { .sec = X, .tb = X }, 0x5, {0x000000, 1024 * 1024} },
+ { .m = { .sec = X, .tb = X }, 0x6, {0x000000, 1024 * 1024} },
+ { .m = { .sec = X, .tb = X }, 0x7, {0x000000, 1024 * 1024} },
+};
+
+static struct wp_range_descriptor mx25l1605d_ranges[] = {
+ { .m = { .sec = X, .tb = 0 }, 0, {0, 0} }, /* none */
+ { .m = { .sec = X, .tb = 0 }, 0x1, {0x1f0000, 64 * 1 * 1024} }, /* block 31 */
+ { .m = { .sec = X, .tb = 0 }, 0x2, {0x1e0000, 64 * 2 * 1024} }, /* blocks 30-31 */
+ { .m = { .sec = X, .tb = 0 }, 0x3, {0x1c0000, 64 * 4 * 1024} }, /* blocks 28-31 */
+ { .m = { .sec = X, .tb = 0 }, 0x4, {0x180000, 64 * 8 * 1024} }, /* blocks 24-31 */
+ { .m = { .sec = X, .tb = 0 }, 0x5, {0x100000, 64 * 16 * 1024} }, /* blocks 16-31 */
+ { .m = { .sec = X, .tb = 0 }, 0x6, {0x000000, 64 * 32 * 1024} }, /* blocks 0-31 */
+ { .m = { .sec = X, .tb = 0 }, 0x7, {0x000000, 64 * 32 * 1024} }, /* blocks 0-31 */
+
+ { .m = { .sec = X, .tb = 1 }, 0x0, {0x000000, 2048 * 1024} },
+ { .m = { .sec = X, .tb = 1 }, 0x1, {0x000000, 2048 * 1024} },
+ { .m = { .sec = X, .tb = 1 }, 0x2, {0x000000, 64 * 16 * 1024} }, /* blocks 0-15 */
+ { .m = { .sec = X, .tb = 1 }, 0x3, {0x000000, 64 * 24 * 1024} }, /* blocks 0-23 */
+ { .m = { .sec = X, .tb = 1 }, 0x4, {0x000000, 64 * 28 * 1024} }, /* blocks 0-27 */
+ { .m = { .sec = X, .tb = 1 }, 0x5, {0x000000, 64 * 30 * 1024} }, /* blocks 0-29 */
+ { .m = { .sec = X, .tb = 1 }, 0x6, {0x000000, 64 * 31 * 1024} }, /* blocks 0-30 */
+ { .m = { .sec = X, .tb = 1 }, 0x7, {0x000000, 64 * 32 * 1024} }, /* blocks 0-31 */
+};
+
+/* FIXME: Is there an mx25l3205 (without a trailing letter)? */
+static struct wp_range_descriptor mx25l3205d_ranges[] = {
+ { .m = { .sec = X, .tb = 0 }, 0, {0, 0} }, /* none */
+ { .m = { .sec = X, .tb = 0 }, 0x1, {0x3f0000, 64 * 1024} },
+ { .m = { .sec = X, .tb = 0 }, 0x2, {0x3e0000, 128 * 1024} },
+ { .m = { .sec = X, .tb = 0 }, 0x3, {0x3c0000, 256 * 1024} },
+ { .m = { .sec = X, .tb = 0 }, 0x4, {0x380000, 512 * 1024} },
+ { .m = { .sec = X, .tb = 0 }, 0x5, {0x300000, 1024 * 1024} },
+ { .m = { .sec = X, .tb = 0 }, 0x6, {0x200000, 2048 * 1024} },
+ { .m = { .sec = X, .tb = 0 }, 0x7, {0x000000, 4096 * 1024} },
+
+ { .m = { .sec = X, .tb = 1 }, 0x0, {0x000000, 4096 * 1024} },
+ { .m = { .sec = X, .tb = 1 }, 0x1, {0x000000, 2048 * 1024} },
+ { .m = { .sec = X, .tb = 1 }, 0x2, {0x000000, 3072 * 1024} },
+ { .m = { .sec = X, .tb = 1 }, 0x3, {0x000000, 3584 * 1024} },
+ { .m = { .sec = X, .tb = 1 }, 0x4, {0x000000, 3840 * 1024} },
+ { .m = { .sec = X, .tb = 1 }, 0x5, {0x000000, 3968 * 1024} },
+ { .m = { .sec = X, .tb = 1 }, 0x6, {0x000000, 4032 * 1024} },
+ { .m = { .sec = X, .tb = 1 }, 0x7, {0x000000, 4096 * 1024} },
+};
+
+static struct wp_range_descriptor mx25u3235e_ranges[] = {
+ { .m = { .sec = X, .tb = 0 }, 0, {0, 0} }, /* none */
+ { .m = { .sec = 0, .tb = 0 }, 0x1, {0x3f0000, 64 * 1024} },
+ { .m = { .sec = 0, .tb = 0 }, 0x2, {0x3e0000, 128 * 1024} },
+ { .m = { .sec = 0, .tb = 0 }, 0x3, {0x3c0000, 256 * 1024} },
+ { .m = { .sec = 0, .tb = 0 }, 0x4, {0x380000, 512 * 1024} },
+ { .m = { .sec = 0, .tb = 0 }, 0x5, {0x300000, 1024 * 1024} },
+ { .m = { .sec = 0, .tb = 0 }, 0x6, {0x200000, 2048 * 1024} },
+ { .m = { .sec = 0, .tb = 0 }, 0x7, {0x000000, 4096 * 1024} },
+
+ { .m = { .sec = 0, .tb = 1 }, 0x0, {0x000000, 4096 * 1024} },
+ { .m = { .sec = 0, .tb = 1 }, 0x1, {0x000000, 2048 * 1024} },
+ { .m = { .sec = 0, .tb = 1 }, 0x2, {0x000000, 3072 * 1024} },
+ { .m = { .sec = 0, .tb = 1 }, 0x3, {0x000000, 3584 * 1024} },
+ { .m = { .sec = 0, .tb = 1 }, 0x4, {0x000000, 3840 * 1024} },
+ { .m = { .sec = 0, .tb = 1 }, 0x5, {0x000000, 3968 * 1024} },
+ { .m = { .sec = 0, .tb = 1 }, 0x6, {0x000000, 4032 * 1024} },
+ { .m = { .sec = 0, .tb = 1 }, 0x7, {0x000000, 4096 * 1024} },
+};
+
+static struct wp_range_descriptor mx25u6435e_ranges[] = {
+ { .m = { .sec = X, .tb = 0 }, 0, {0, 0} }, /* none */
+ { .m = { .sec = 0, .tb = 0 }, 0x1, {0x7f0000, 1 * 64 * 1024} }, /* block 127 */
+ { .m = { .sec = 0, .tb = 0 }, 0x2, {0x7e0000, 2 * 64 * 1024} }, /* blocks 126-127 */
+ { .m = { .sec = 0, .tb = 0 }, 0x3, {0x7c0000, 4 * 64 * 1024} }, /* blocks 124-127 */
+ { .m = { .sec = 0, .tb = 0 }, 0x4, {0x780000, 8 * 64 * 1024} }, /* blocks 120-127 */
+ { .m = { .sec = 0, .tb = 0 }, 0x5, {0x700000, 16 * 64 * 1024} }, /* blocks 112-127 */
+ { .m = { .sec = 0, .tb = 0 }, 0x6, {0x600000, 32 * 64 * 1024} }, /* blocks 96-127 */
+ { .m = { .sec = 0, .tb = 0 }, 0x7, {0x400000, 64 * 64 * 1024} }, /* blocks 64-127 */
+
+ { .m = { .sec = 0, .tb = 1 }, 0x0, {0x000000, 64 * 64 * 1024} }, /* blocks 0-63 */
+ { .m = { .sec = 0, .tb = 1 }, 0x1, {0x000000, 96 * 64 * 1024} }, /* blocks 0-95 */
+ { .m = { .sec = 0, .tb = 1 }, 0x2, {0x000000, 112 * 64 * 1024} }, /* blocks 0-111 */
+ { .m = { .sec = 0, .tb = 1 }, 0x3, {0x000000, 120 * 64 * 1024} }, /* blocks 0-119 */
+ { .m = { .sec = 0, .tb = 1 }, 0x4, {0x000000, 124 * 64 * 1024} }, /* blocks 0-123 */
+ { .m = { .sec = 0, .tb = 1 }, 0x5, {0x000000, 126 * 64 * 1024} }, /* blocks 0-125 */
+ { .m = { .sec = 0, .tb = 1 }, 0x6, {0x000000, 127 * 64 * 1024} }, /* blocks 0-126 */
+ { .m = { .sec = 0, .tb = 1 }, 0x7, {0x000000, 128 * 64 * 1024} }, /* blocks 0-127 */
+};
+
+#define MX25U12835E_TB (1 << 3)
+static struct wp_range_descriptor mx25u12835e_tb0_ranges[] = {
+ { .m = { .sec = X, .tb = X }, 0, {0, 0} }, /* none */
+ { .m = { .sec = 0, .tb = 0 }, 0x1, {0xff0000, 1 * 64 * 1024} }, /* block 255 */
+ { .m = { .sec = 0, .tb = 0 }, 0x2, {0xfe0000, 2 * 64 * 1024} }, /* blocks 254-255 */
+ { .m = { .sec = 0, .tb = 0 }, 0x3, {0xfc0000, 4 * 64 * 1024} }, /* blocks 252-255 */
+ { .m = { .sec = 0, .tb = 0 }, 0x4, {0xf80000, 8 * 64 * 1024} }, /* blocks 248-255 */
+ { .m = { .sec = 0, .tb = 0 }, 0x5, {0xf00000, 16 * 64 * 1024} }, /* blocks 240-255 */
+ { .m = { .sec = 0, .tb = 0 }, 0x6, {0xe00000, 32 * 64 * 1024} }, /* blocks 224-255 */
+ { .m = { .sec = 0, .tb = 0 }, 0x7, {0xc00000, 64 * 64 * 1024} }, /* blocks 192-255 */
+ { .m = { .sec = 0, .tb = 0 }, 0x8, {0x800000, 128 * 64 * 1024} }, /* blocks 128-255 */
+ { .m = { .sec = 0, .tb = 0 }, 0x9, {0x000000, 256 * 64 * 1024} }, /* blocks all */
+ { .m = { .sec = 0, .tb = 0 }, 0xa, {0x000000, 256 * 64 * 1024} }, /* blocks all */
+ { .m = { .sec = 0, .tb = 0 }, 0xb, {0x000000, 256 * 64 * 1024} }, /* blocks all */
+ { .m = { .sec = 0, .tb = 0 }, 0xc, {0x000000, 256 * 64 * 1024} }, /* blocks all */
+ { .m = { .sec = 0, .tb = 0 }, 0xd, {0x000000, 256 * 64 * 1024} }, /* blocks all */
+ { .m = { .sec = 0, .tb = 0 }, 0xe, {0x000000, 256 * 64 * 1024} }, /* blocks all */
+ { .m = { .sec = 0, .tb = 0 }, 0xf, {0x000000, 256 * 64 * 1024} }, /* blocks all */
+};
+
+static struct wp_range_descriptor mx25u12835e_tb1_ranges[] = {
+ { .m = { .sec = 0, .tb = 1 }, 0x1, {0x000000, 1 * 64 * 1024} }, /* block 0 */
+ { .m = { .sec = 0, .tb = 1 }, 0x2, {0x000000, 2 * 64 * 1024} }, /* blocks 0-1 */
+ { .m = { .sec = 0, .tb = 1 }, 0x3, {0x000000, 4 * 64 * 1024} }, /* blocks 0-3 */
+ { .m = { .sec = 0, .tb = 1 }, 0x4, {0x000000, 8 * 64 * 1024} }, /* blocks 0-7 */
+ { .m = { .sec = 0, .tb = 1 }, 0x5, {0x000000, 16 * 64 * 1024} }, /* blocks 0-15 */
+ { .m = { .sec = 0, .tb = 1 }, 0x6, {0x000000, 32 * 64 * 1024} }, /* blocks 0-31 */
+ { .m = { .sec = 0, .tb = 1 }, 0x7, {0x000000, 64 * 64 * 1024} }, /* blocks 0-63 */
+ { .m = { .sec = 0, .tb = 1 }, 0x8, {0x000000, 128 * 64 * 1024} }, /* blocks 0-127 */
+ { .m = { .sec = 0, .tb = 1 }, 0x9, {0x000000, 256 * 64 * 1024} }, /* blocks all */
+ { .m = { .sec = 0, .tb = 1 }, 0xa, {0x000000, 256 * 64 * 1024} }, /* blocks all */
+ { .m = { .sec = 0, .tb = 1 }, 0xb, {0x000000, 256 * 64 * 1024} }, /* blocks all */
+ { .m = { .sec = 0, .tb = 1 }, 0xc, {0x000000, 256 * 64 * 1024} }, /* blocks all */
+ { .m = { .sec = 0, .tb = 1 }, 0xd, {0x000000, 256 * 64 * 1024} }, /* blocks all */
+ { .m = { .sec = 0, .tb = 1 }, 0xe, {0x000000, 256 * 64 * 1024} }, /* blocks all */
+ { .m = { .sec = 0, .tb = 1 }, 0xf, {0x000000, 256 * 64 * 1024} }, /* blocks all */
+};
+
+static struct wp_range_descriptor n25q064_ranges[] = {
+ /*
+ * Note: For N25Q064, sec (usually in bit position 6) is called BP3
+ * (block protect bit 3). It is only useful when all blocks are to
+ * be write-protected.
+ */
+ { .m = { .sec = 0, .tb = 0 }, 0, {0, 0} }, /* none */
+
+ { .m = { .sec = 0, .tb = 0 }, 0x1, {0x7f0000, 64 * 1024} }, /* block 127 */
+ { .m = { .sec = 0, .tb = 0 }, 0x2, {0x7e0000, 2 * 64 * 1024} }, /* blocks 126-127 */
+ { .m = { .sec = 0, .tb = 0 }, 0x3, {0x7c0000, 4 * 64 * 1024} }, /* blocks 124-127 */
+ { .m = { .sec = 0, .tb = 0 }, 0x4, {0x780000, 8 * 64 * 1024} }, /* blocks 120-127 */
+ { .m = { .sec = 0, .tb = 0 }, 0x5, {0x700000, 16 * 64 * 1024} }, /* blocks 112-127 */
+ { .m = { .sec = 0, .tb = 0 }, 0x6, {0x600000, 32 * 64 * 1024} }, /* blocks 96-127 */
+ { .m = { .sec = 0, .tb = 0 }, 0x7, {0x400000, 64 * 64 * 1024} }, /* blocks 64-127 */
+
+ { .m = { .sec = 0, .tb = 1 }, 0x1, {0x000000, 64 * 1024} }, /* block 0 */
+ { .m = { .sec = 0, .tb = 1 }, 0x2, {0x000000, 2 * 64 * 1024} }, /* blocks 0-1 */
+ { .m = { .sec = 0, .tb = 1 }, 0x3, {0x000000, 4 * 64 * 1024} }, /* blocks 0-3 */
+ { .m = { .sec = 0, .tb = 1 }, 0x4, {0x000000, 8 * 64 * 1024} }, /* blocks 0-7 */
+ { .m = { .sec = 0, .tb = 1 }, 0x5, {0x000000, 16 * 64 * 1024} }, /* blocks 0-15 */
+ { .m = { .sec = 0, .tb = 1 }, 0x6, {0x000000, 32 * 64 * 1024} }, /* blocks 0-31 */
+ { .m = { .sec = 0, .tb = 1 }, 0x7, {0x000000, 64 * 64 * 1024} }, /* blocks 0-63 */
+
+ { .m = { .sec = X, .tb = 1 }, 0x0, {0x000000, 128 * 64 * 1024} }, /* all */
+ { .m = { .sec = X, .tb = 1 }, 0x1, {0x000000, 128 * 64 * 1024} }, /* all */
+ { .m = { .sec = X, .tb = 1 }, 0x2, {0x000000, 128 * 64 * 1024} }, /* all */
+ { .m = { .sec = X, .tb = 1 }, 0x3, {0x000000, 128 * 64 * 1024} }, /* all */
+ { .m = { .sec = X, .tb = 1 }, 0x4, {0x000000, 128 * 64 * 1024} }, /* all */
+ { .m = { .sec = X, .tb = 1 }, 0x5, {0x000000, 128 * 64 * 1024} }, /* all */
+ { .m = { .sec = X, .tb = 1 }, 0x6, {0x000000, 128 * 64 * 1024} }, /* all */
+ { .m = { .sec = X, .tb = 1 }, 0x7, {0x000000, 128 * 64 * 1024} }, /* all */
+};
+
+static struct wp_range_descriptor w25q16_ranges[] = {
+ { .m = { .sec = X, .tb = X }, 0, {0, 0} }, /* none */
+ { .m = { .sec = 0, .tb = 0 }, 0x1, {0x1f0000, 64 * 1024} },
+ { .m = { .sec = 0, .tb = 0 }, 0x2, {0x1e0000, 128 * 1024} },
+ { .m = { .sec = 0, .tb = 0 }, 0x3, {0x1c0000, 256 * 1024} },
+ { .m = { .sec = 0, .tb = 0 }, 0x4, {0x180000, 512 * 1024} },
+ { .m = { .sec = 0, .tb = 0 }, 0x5, {0x100000, 1024 * 1024} },
+
+ { .m = { .sec = 0, .tb = 1 }, 0x1, {0x000000, 64 * 1024} },
+ { .m = { .sec = 0, .tb = 1 }, 0x2, {0x000000, 128 * 1024} },
+ { .m = { .sec = 0, .tb = 1 }, 0x3, {0x000000, 256 * 1024} },
+ { .m = { .sec = 0, .tb = 1 }, 0x4, {0x000000, 512 * 1024} },
+ { .m = { .sec = 0, .tb = 1 }, 0x5, {0x000000, 1024 * 1024} },
+ { .m = { .sec = X, .tb = X }, 0x6, {0x000000, 2048 * 1024} },
+ { .m = { .sec = X, .tb = X }, 0x7, {0x000000, 2048 * 1024} },
+
+ { .m = { .sec = 1, .tb = 0 }, 0x1, {0x1ff000, 4 * 1024} },
+ { .m = { .sec = 1, .tb = 0 }, 0x2, {0x1fe000, 8 * 1024} },
+ { .m = { .sec = 1, .tb = 0 }, 0x3, {0x1fc000, 16 * 1024} },
+ { .m = { .sec = 1, .tb = 0 }, 0x4, {0x1f8000, 32 * 1024} },
+ { .m = { .sec = 1, .tb = 0 }, 0x5, {0x1f8000, 32 * 1024} },
+
+ { .m = { .sec = 1, .tb = 1 }, 0x1, {0x000000, 4 * 1024} },
+ { .m = { .sec = 1, .tb = 1 }, 0x2, {0x000000, 8 * 1024} },
+ { .m = { .sec = 1, .tb = 1 }, 0x3, {0x000000, 16 * 1024} },
+ { .m = { .sec = 1, .tb = 1 }, 0x4, {0x000000, 32 * 1024} },
+ { .m = { .sec = 1, .tb = 1 }, 0x5, {0x000000, 32 * 1024} },
+};
+
+static struct wp_range_descriptor w25q32_ranges[] = {
+ { .m = { .sec = X, .tb = X }, 0, {0, 0} }, /* none */
+ { .m = { .sec = 0, .tb = 0 }, 0x1, {0x3f0000, 64 * 1024} },
+ { .m = { .sec = 0, .tb = 0 }, 0x2, {0x3e0000, 128 * 1024} },
+ { .m = { .sec = 0, .tb = 0 }, 0x3, {0x3c0000, 256 * 1024} },
+ { .m = { .sec = 0, .tb = 0 }, 0x4, {0x380000, 512 * 1024} },
+ { .m = { .sec = 0, .tb = 0 }, 0x5, {0x300000, 1024 * 1024} },
+ { .m = { .sec = 0, .tb = 0 }, 0x6, {0x200000, 2048 * 1024} },
+
+ { .m = { .sec = 0, .tb = 1 }, 0x1, {0x000000, 64 * 1024} },
+ { .m = { .sec = 0, .tb = 1 }, 0x2, {0x000000, 128 * 1024} },
+ { .m = { .sec = 0, .tb = 1 }, 0x3, {0x000000, 256 * 1024} },
+ { .m = { .sec = 0, .tb = 1 }, 0x4, {0x000000, 512 * 1024} },
+ { .m = { .sec = 0, .tb = 1 }, 0x5, {0x000000, 1024 * 1024} },
+ { .m = { .sec = 0, .tb = 1 }, 0x6, {0x000000, 2048 * 1024} },
+ { .m = { .sec = X, .tb = X }, 0x7, {0x000000, 4096 * 1024} },
+
+ { .m = { .sec = 1, .tb = 0 }, 0x1, {0x3ff000, 4 * 1024} },
+ { .m = { .sec = 1, .tb = 0 }, 0x2, {0x3fe000, 8 * 1024} },
+ { .m = { .sec = 1, .tb = 0 }, 0x3, {0x3fc000, 16 * 1024} },
+ { .m = { .sec = 1, .tb = 0 }, 0x4, {0x3f8000, 32 * 1024} },
+ { .m = { .sec = 1, .tb = 0 }, 0x5, {0x3f8000, 32 * 1024} },
+
+ { .m = { .sec = 1, .tb = 1 }, 0x1, {0x000000, 4 * 1024} },
+ { .m = { .sec = 1, .tb = 1 }, 0x2, {0x000000, 8 * 1024} },
+ { .m = { .sec = 1, .tb = 1 }, 0x3, {0x000000, 16 * 1024} },
+ { .m = { .sec = 1, .tb = 1 }, 0x4, {0x000000, 32 * 1024} },
+ { .m = { .sec = 1, .tb = 1 }, 0x5, {0x000000, 32 * 1024} },
+};
+
+static struct wp_range_descriptor w25q80_ranges[] = {
+ { .m = { .sec = X, .tb = X }, 0, {0, 0} }, /* none */
+ { .m = { .sec = 0, .tb = 0 }, 0x1, {0x0f0000, 64 * 1024} },
+ { .m = { .sec = 0, .tb = 0 }, 0x2, {0x0e0000, 128 * 1024} },
+ { .m = { .sec = 0, .tb = 0 }, 0x3, {0x0c0000, 256 * 1024} },
+ { .m = { .sec = 0, .tb = 0 }, 0x4, {0x080000, 512 * 1024} },
+
+ { .m = { .sec = 0, .tb = 1 }, 0x1, {0x000000, 64 * 1024} },
+ { .m = { .sec = 0, .tb = 1 }, 0x2, {0x000000, 128 * 1024} },
+ { .m = { .sec = 0, .tb = 1 }, 0x3, {0x000000, 256 * 1024} },
+ { .m = { .sec = 0, .tb = 1 }, 0x4, {0x000000, 512 * 1024} },
+ { .m = { .sec = X, .tb = X }, 0x6, {0x000000, 1024 * 1024} },
+ { .m = { .sec = X, .tb = X }, 0x7, {0x000000, 1024 * 1024} },
+
+ { .m = { .sec = 1, .tb = 0 }, 0x1, {0x1ff000, 4 * 1024} },
+ { .m = { .sec = 1, .tb = 0 }, 0x2, {0x1fe000, 8 * 1024} },
+ { .m = { .sec = 1, .tb = 0 }, 0x3, {0x1fc000, 16 * 1024} },
+ { .m = { .sec = 1, .tb = 0 }, 0x4, {0x1f8000, 32 * 1024} },
+ { .m = { .sec = 1, .tb = 0 }, 0x5, {0x1f8000, 32 * 1024} },
+
+ { .m = { .sec = 1, .tb = 1 }, 0x1, {0x000000, 4 * 1024} },
+ { .m = { .sec = 1, .tb = 1 }, 0x2, {0x000000, 8 * 1024} },
+ { .m = { .sec = 1, .tb = 1 }, 0x3, {0x000000, 16 * 1024} },
+ { .m = { .sec = 1, .tb = 1 }, 0x4, {0x000000, 32 * 1024} },
+ { .m = { .sec = 1, .tb = 1 }, 0x5, {0x000000, 32 * 1024} },
+};
+
+static struct wp_range_descriptor w25q64_ranges[] = {
+ { .m = { .sec = X, .tb = X }, 0, {0, 0} }, /* none */
+
+ { .m = { .sec = 0, .tb = 0 }, 0x1, {0x7e0000, 128 * 1024} },
+ { .m = { .sec = 0, .tb = 0 }, 0x2, {0x7c0000, 256 * 1024} },
+ { .m = { .sec = 0, .tb = 0 }, 0x3, {0x780000, 512 * 1024} },
+ { .m = { .sec = 0, .tb = 0 }, 0x4, {0x700000, 1024 * 1024} },
+ { .m = { .sec = 0, .tb = 0 }, 0x5, {0x600000, 2048 * 1024} },
+ { .m = { .sec = 0, .tb = 0 }, 0x6, {0x400000, 4096 * 1024} },
+
+ { .m = { .sec = 0, .tb = 1 }, 0x1, {0x000000, 128 * 1024} },
+ { .m = { .sec = 0, .tb = 1 }, 0x2, {0x000000, 256 * 1024} },
+ { .m = { .sec = 0, .tb = 1 }, 0x3, {0x000000, 512 * 1024} },
+ { .m = { .sec = 0, .tb = 1 }, 0x4, {0x000000, 1024 * 1024} },
+ { .m = { .sec = 0, .tb = 1 }, 0x5, {0x000000, 2048 * 1024} },
+ { .m = { .sec = 0, .tb = 1 }, 0x6, {0x000000, 4096 * 1024} },
+ { .m = { .sec = X, .tb = X }, 0x7, {0x000000, 8192 * 1024} },
+
+ { .m = { .sec = 1, .tb = 0 }, 0x1, {0x7ff000, 4 * 1024} },
+ { .m = { .sec = 1, .tb = 0 }, 0x2, {0x7fe000, 8 * 1024} },
+ { .m = { .sec = 1, .tb = 0 }, 0x3, {0x7fc000, 16 * 1024} },
+ { .m = { .sec = 1, .tb = 0 }, 0x4, {0x7f8000, 32 * 1024} },
+ { .m = { .sec = 1, .tb = 0 }, 0x5, {0x7f8000, 32 * 1024} },
+
+ { .m = { .sec = 1, .tb = 1 }, 0x1, {0x000000, 4 * 1024} },
+ { .m = { .sec = 1, .tb = 1 }, 0x2, {0x000000, 8 * 1024} },
+ { .m = { .sec = 1, .tb = 1 }, 0x3, {0x000000, 16 * 1024} },
+ { .m = { .sec = 1, .tb = 1 }, 0x4, {0x000000, 32 * 1024} },
+ { .m = { .sec = 1, .tb = 1 }, 0x5, {0x000000, 32 * 1024} },
+};
+
+static struct wp_range_descriptor w25rq128_cmp0_ranges[] = {
+ { .m = { .sec = X, .tb = X }, 0, {0, 0} }, /* NONE */
+
+ { .m = { .sec = 0, .tb = 0 }, 0x1, {0xfc0000, 256 * 1024} }, /* Upper 1/64 */
+ { .m = { .sec = 0, .tb = 0 }, 0x2, {0xf80000, 512 * 1024} }, /* Upper 1/32 */
+ { .m = { .sec = 0, .tb = 0 }, 0x3, {0xf00000, 1024 * 1024} }, /* Upper 1/16 */
+ { .m = { .sec = 0, .tb = 0 }, 0x4, {0xe00000, 2048 * 1024} }, /* Upper 1/8 */
+ { .m = { .sec = 0, .tb = 0 }, 0x5, {0xc00000, 4096 * 1024} }, /* Upper 1/4 */
+ { .m = { .sec = 0, .tb = 0 }, 0x6, {0x800000, 8192 * 1024} }, /* Upper 1/2 */
+
+ { .m = { .sec = 0, .tb = 1 }, 0x1, {0x000000, 256 * 1024} }, /* Lower 1/64 */
+ { .m = { .sec = 0, .tb = 1 }, 0x2, {0x000000, 512 * 1024} }, /* Lower 1/32 */
+ { .m = { .sec = 0, .tb = 1 }, 0x3, {0x000000, 1024 * 1024} }, /* Lower 1/16 */
+ { .m = { .sec = 0, .tb = 1 }, 0x4, {0x000000, 2048 * 1024} }, /* Lower 1/8 */
+ { .m = { .sec = 0, .tb = 1 }, 0x5, {0x000000, 4096 * 1024} }, /* Lower 1/4 */
+ { .m = { .sec = 0, .tb = 1 }, 0x6, {0x000000, 8192 * 1024} }, /* Lower 1/2 */
+
+ { .m = { .sec = X, .tb = X }, 0x7, {0x000000, 16384 * 1024} }, /* ALL */
+
+ { .m = { .sec = 1, .tb = 0 }, 0x1, {0xfff000, 4 * 1024} }, /* Upper 1/4096 */
+ { .m = { .sec = 1, .tb = 0 }, 0x2, {0xffe000, 8 * 1024} }, /* Upper 1/2048 */
+ { .m = { .sec = 1, .tb = 0 }, 0x3, {0xffc000, 16 * 1024} }, /* Upper 1/1024 */
+ { .m = { .sec = 1, .tb = 0 }, 0x4, {0xff8000, 32 * 1024} }, /* Upper 1/512 */
+ { .m = { .sec = 1, .tb = 0 }, 0x5, {0xff8000, 32 * 1024} }, /* Upper 1/512 */
+
+ { .m = { .sec = 1, .tb = 1 }, 0x1, {0x000000, 4 * 1024} }, /* Lower 1/4096 */
+ { .m = { .sec = 1, .tb = 1 }, 0x2, {0x000000, 8 * 1024} }, /* Lower 1/2048 */
+ { .m = { .sec = 1, .tb = 1 }, 0x3, {0x000000, 16 * 1024} }, /* Lower 1/1024 */
+ { .m = { .sec = 1, .tb = 1 }, 0x4, {0x000000, 32 * 1024} }, /* Lower 1/512 */
+ { .m = { .sec = 1, .tb = 1 }, 0x5, {0x000000, 32 * 1024} }, /* Lower 1/512 */
+};
+
+static struct wp_range_descriptor w25rq128_cmp1_ranges[] = {
+ { .m = { .sec = X, .tb = X }, 0x0, {0x000000, 16 * 1024 * 1024} }, /* ALL */
+
+ { .m = { .sec = 0, .tb = 0 }, 0x1, {0x000000, 16128 * 1024} }, /* Lower 63/64 */
+ { .m = { .sec = 0, .tb = 0 }, 0x2, {0x000000, 15872 * 1024} }, /* Lower 31/32 */
+ { .m = { .sec = 0, .tb = 0 }, 0x3, {0x000000, 15 * 1024 * 1024} }, /* Lower 15/16 */
+ { .m = { .sec = 0, .tb = 0 }, 0x4, {0x000000, 14 * 1024 * 1024} }, /* Lower 7/8 */
+ { .m = { .sec = 0, .tb = 0 }, 0x5, {0x000000, 12 * 1024 * 1024} }, /* Lower 3/4 */
+ { .m = { .sec = 0, .tb = 0 }, 0x6, {0x000000, 8 * 1024 * 1024} }, /* Lower 1/2 */
+
+ { .m = { .sec = 0, .tb = 1 }, 0x1, {0x040000, 16128 * 1024} }, /* Upper 63/64 */
+ { .m = { .sec = 0, .tb = 1 }, 0x2, {0x080000, 15872 * 1024} }, /* Upper 31/32 */
+ { .m = { .sec = 0, .tb = 1 }, 0x3, {0x100000, 15 * 1024 * 1024} }, /* Upper 15/16 */
+ { .m = { .sec = 0, .tb = 1 }, 0x4, {0x200000, 14 * 1024 * 1024} }, /* Upper 7/8 */
+ { .m = { .sec = 0, .tb = 1 }, 0x5, {0x400000, 12 * 1024 * 1024} }, /* Upper 3/4 */
+ { .m = { .sec = 0, .tb = 1 }, 0x6, {0x800000, 8 * 1024 * 1024} }, /* Upper 1/2 */
+
+ { .m = { .sec = X, .tb = X }, 0x7, {0x000000, 0} }, /* NONE */
+
+ { .m = { .sec = 1, .tb = 0 }, 0x1, {0x000000, 16380 * 1024} }, /* Lower 4095/4096 */
+ { .m = { .sec = 1, .tb = 0 }, 0x2, {0x000000, 16376 * 1024} }, /* Lower 2048/2048 */
+ { .m = { .sec = 1, .tb = 0 }, 0x3, {0x000000, 16368 * 1024} }, /* Lower 1023/1024 */
+ { .m = { .sec = 1, .tb = 0 }, 0x4, {0x000000, 16352 * 1024} }, /* Lower 511/512 */
+ { .m = { .sec = 1, .tb = 0 }, 0x5, {0x000000, 16352 * 1024} }, /* Lower 511/512 */
+
+ { .m = { .sec = 1, .tb = 1 }, 0x1, {0x001000, 16380 * 1024} }, /* Upper 4095/4096 */
+ { .m = { .sec = 1, .tb = 1 }, 0x2, {0x002000, 16376 * 1024} }, /* Upper 2047/2048 */
+ { .m = { .sec = 1, .tb = 1 }, 0x3, {0x004000, 16368 * 1024} }, /* Upper 1023/1024 */
+ { .m = { .sec = 1, .tb = 1 }, 0x4, {0x008000, 16352 * 1024} }, /* Upper 511/512 */
+ { .m = { .sec = 1, .tb = 1 }, 0x5, {0x008000, 16352 * 1024} }, /* Upper 511/512 */
+};
+
+static struct wp_range_descriptor w25rq256_cmp0_ranges[] = {
+ { .m = { .sec = X, .tb = X }, 0x0, {0x0000000, 0x0000000} }, /* NONE */
+
+ { .m = { .sec = X, .tb = 0 }, 0x1, {0x1ff0000, 64 * 1 * 1024} }, /* Upper 1/512 */
+ { .m = { .sec = X, .tb = 0 }, 0x2, {0x1fe0000, 64 * 2 * 1024} }, /* Upper 1/256 */
+ { .m = { .sec = X, .tb = 0 }, 0x3, {0x1fc0000, 64 * 4 * 1024} }, /* Upper 1/128 */
+ { .m = { .sec = X, .tb = 0 }, 0x4, {0x1f80000, 64 * 8 * 1024} }, /* Upper 1/64 */
+ { .m = { .sec = X, .tb = 0 }, 0x5, {0x1f00000, 64 * 16 * 1024} }, /* Upper 1/32 */
+ { .m = { .sec = X, .tb = 0 }, 0x6, {0x1e00000, 64 * 32 * 1024} }, /* Upper 1/16 */
+ { .m = { .sec = X, .tb = 0 }, 0x7, {0x1c00000, 64 * 64 * 1024} }, /* Upper 1/8 */
+ { .m = { .sec = X, .tb = 0 }, 0x8, {0x1800000, 64 * 128 * 1024} }, /* Upper 1/4 */
+ { .m = { .sec = X, .tb = 0 }, 0x9, {0x1000000, 64 * 256 * 1024} }, /* Upper 1/2 */
+
+ { .m = { .sec = X, .tb = 1 }, 0x1, {0x0000000, 64 * 1 * 1024} }, /* Lower 1/512 */
+ { .m = { .sec = X, .tb = 1 }, 0x2, {0x0000000, 64 * 2 * 1024} }, /* Lower 1/256 */
+ { .m = { .sec = X, .tb = 1 }, 0x3, {0x0000000, 64 * 4 * 1024} }, /* Lower 1/128 */
+ { .m = { .sec = X, .tb = 1 }, 0x4, {0x0000000, 64 * 8 * 1024} }, /* Lower 1/64 */
+ { .m = { .sec = X, .tb = 1 }, 0x5, {0x0000000, 64 * 16 * 1024} }, /* Lower 1/32 */
+ { .m = { .sec = X, .tb = 1 }, 0x6, {0x0000000, 64 * 32 * 1024} }, /* Lower 1/16 */
+ { .m = { .sec = X, .tb = 1 }, 0x7, {0x0000000, 64 * 64 * 1024} }, /* Lower 1/8 */
+ { .m = { .sec = X, .tb = 1 }, 0x8, {0x0000000, 64 * 128 * 1024} }, /* Lower 1/4 */
+ { .m = { .sec = X, .tb = 1 }, 0x9, {0x0000000, 64 * 256 * 1024} }, /* Lower 1/2 */
+
+ { .m = { .sec = X, .tb = X }, 0xa, {0x0000000, 64 * 512 * 1024} }, /* ALL */
+ { .m = { .sec = X, .tb = X }, 0xb, {0x0000000, 64 * 512 * 1024} }, /* ALL */
+ { .m = { .sec = X, .tb = X }, 0xc, {0x0000000, 64 * 512 * 1024} }, /* ALL */
+ { .m = { .sec = X, .tb = X }, 0xd, {0x0000000, 64 * 512 * 1024} }, /* ALL */
+ { .m = { .sec = X, .tb = X }, 0xe, {0x0000000, 64 * 512 * 1024} }, /* ALL */
+ { .m = { .sec = X, .tb = X }, 0xf, {0x0000000, 64 * 512 * 1024} }, /* ALL */
+};
+
+static struct wp_range_descriptor w25rq256_cmp1_ranges[] = {
+ { .m = { .sec = X, .tb = X }, 0x0, {0x0000000, 64 * 512 * 1024} }, /* ALL */
+
+ { .m = { .sec = X, .tb = 0 }, 0x1, {0x0000000, 64 * 511 * 1024} }, /* Lower 511/512 */
+ { .m = { .sec = X, .tb = 0 }, 0x2, {0x0000000, 64 * 510 * 1024} }, /* Lower 255/256 */
+ { .m = { .sec = X, .tb = 0 }, 0x3, {0x0000000, 64 * 508 * 1024} }, /* Lower 127/128 */
+ { .m = { .sec = X, .tb = 0 }, 0x4, {0x0000000, 64 * 504 * 1024} }, /* Lower 63/64 */
+ { .m = { .sec = X, .tb = 0 }, 0x5, {0x0000000, 64 * 496 * 1024} }, /* Lower 31/32 */
+ { .m = { .sec = X, .tb = 0 }, 0x6, {0x0000000, 64 * 480 * 1024} }, /* Lower 15/16 */
+ { .m = { .sec = X, .tb = 0 }, 0x7, {0x0000000, 64 * 448 * 1024} }, /* Lower 7/8 */
+ { .m = { .sec = X, .tb = 0 }, 0x8, {0x0000000, 64 * 384 * 1024} }, /* Lower 3/4 */
+ { .m = { .sec = X, .tb = 0 }, 0x9, {0x0000000, 64 * 256 * 1024} }, /* Lower 1/2 */
+
+ { .m = { .sec = X, .tb = 1 }, 0x1, {0x0010000, 64 * 511 * 1024} }, /* Upper 511/512 */
+ { .m = { .sec = X, .tb = 1 }, 0x2, {0x0020000, 64 * 510 * 1024} }, /* Upper 255/256 */
+ { .m = { .sec = X, .tb = 1 }, 0x3, {0x0040000, 64 * 508 * 1024} }, /* Upper 127/128 */
+ { .m = { .sec = X, .tb = 1 }, 0x4, {0x0080000, 64 * 504 * 1024} }, /* Upper 63/64 */
+ { .m = { .sec = X, .tb = 1 }, 0x5, {0x0100000, 64 * 496 * 1024} }, /* Upper 31/32 */
+ { .m = { .sec = X, .tb = 1 }, 0x6, {0x0200000, 64 * 480 * 1024} }, /* Upper 15/16 */
+ { .m = { .sec = X, .tb = 1 }, 0x7, {0x0400000, 64 * 448 * 1024} }, /* Upper 7/8 */
+ { .m = { .sec = X, .tb = 1 }, 0x8, {0x0800000, 64 * 384 * 1024} }, /* Upper 3/4 */
+ { .m = { .sec = X, .tb = 1 }, 0x9, {0x1000000, 64 * 256 * 1024} }, /* Upper 1/2 */
+
+ { .m = { .sec = X, .tb = X }, 0xa, {0x0000000, 0x0000000} }, /* NONE */
+ { .m = { .sec = X, .tb = X }, 0xb, {0x0000000, 0x0000000} }, /* NONE */
+ { .m = { .sec = X, .tb = X }, 0xc, {0x0000000, 0x0000000} }, /* NONE */
+ { .m = { .sec = X, .tb = X }, 0xd, {0x0000000, 0x0000000} }, /* NONE */
+ { .m = { .sec = X, .tb = X }, 0xe, {0x0000000, 0x0000000} }, /* NONE */
+ { .m = { .sec = X, .tb = X }, 0xf, {0x0000000, 0x0000000} }, /* NONE */
+};
+
+struct wp_range_descriptor w25x10_ranges[] = {
+ { .m = { .sec = X, .tb = X }, 0, {0, 0} }, /* none */
+ { .m = { .sec = 0, .tb = 0 }, 0x1, {0x010000, 64 * 1024} },
+ { .m = { .sec = 0, .tb = 1 }, 0x1, {0x000000, 64 * 1024} },
+ { .m = { .sec = X, .tb = X }, 0x2, {0x000000, 128 * 1024} },
+ { .m = { .sec = X, .tb = X }, 0x3, {0x000000, 128 * 1024} },
+};
+
+struct wp_range_descriptor w25x20_ranges[] = {
+ { .m = { .sec = X, .tb = X }, 0, {0, 0} }, /* none */
+ { .m = { .sec = 0, .tb = 0 }, 0x1, {0x030000, 64 * 1024} },
+ { .m = { .sec = 0, .tb = 0 }, 0x2, {0x020000, 128 * 1024} },
+ { .m = { .sec = 0, .tb = 1 }, 0x1, {0x000000, 64 * 1024} },
+ { .m = { .sec = 0, .tb = 1 }, 0x2, {0x000000, 128 * 1024} },
+ { .m = { .sec = 0, .tb = X }, 0x3, {0x000000, 256 * 1024} },
+};
+
+struct wp_range_descriptor w25x40_ranges[] = {
+ { .m = { .sec = X, .tb = X }, 0, {0, 0} }, /* none */
+ { .m = { .sec = 0, .tb = 0 }, 0x1, {0x070000, 64 * 1024} },
+ { .m = { .sec = 0, .tb = 0 }, 0x2, {0x060000, 128 * 1024} },
+ { .m = { .sec = 0, .tb = 0 }, 0x3, {0x040000, 256 * 1024} },
+ { .m = { .sec = 0, .tb = 1 }, 0x1, {0x000000, 64 * 1024} },
+ { .m = { .sec = 0, .tb = 1 }, 0x2, {0x000000, 128 * 1024} },
+ { .m = { .sec = 0, .tb = 1 }, 0x3, {0x000000, 256 * 1024} },
+ { .m = { .sec = 0, .tb = X }, 0x4, {0x000000, 512 * 1024} },
+ { .m = { .sec = 0, .tb = X }, 0x5, {0x000000, 512 * 1024} },
+ { .m = { .sec = 0, .tb = X }, 0x6, {0x000000, 512 * 1024} },
+ { .m = { .sec = 0, .tb = X }, 0x7, {0x000000, 512 * 1024} },
+};
+
+struct wp_range_descriptor w25x80_ranges[] = {
+ { .m = { .sec = X, .tb = X }, 0, {0, 0} }, /* none */
+ { .m = { .sec = 0, .tb = 0 }, 0x1, {0x0F0000, 64 * 1024} },
+ { .m = { .sec = 0, .tb = 0 }, 0x2, {0x0E0000, 128 * 1024} },
+ { .m = { .sec = 0, .tb = 0 }, 0x3, {0x0C0000, 256 * 1024} },
+ { .m = { .sec = 0, .tb = 0 }, 0x4, {0x080000, 512 * 1024} },
+ { .m = { .sec = 0, .tb = 1 }, 0x1, {0x000000, 64 * 1024} },
+ { .m = { .sec = 0, .tb = 1 }, 0x2, {0x000000, 128 * 1024} },
+ { .m = { .sec = 0, .tb = 1 }, 0x3, {0x000000, 256 * 1024} },
+ { .m = { .sec = 0, .tb = 1 }, 0x4, {0x000000, 512 * 1024} },
+ { .m = { .sec = 0, .tb = X }, 0x5, {0x000000, 1024 * 1024} },
+ { .m = { .sec = 0, .tb = X }, 0x6, {0x000000, 1024 * 1024} },
+ { .m = { .sec = 0, .tb = X }, 0x7, {0x000000, 1024 * 1024} },
+};
+
+static struct wp_range_descriptor gd25q40_cmp0_ranges[] = {
+ { .m = { .sec = X, .tb = X }, 0, {0, 0} }, /* None */
+ { .m = { .sec = 0, .tb = 0 }, 0x1, {0x070000, 64 * 1024} },
+ { .m = { .sec = 0, .tb = 0 }, 0x2, {0x060000, 128 * 1024} },
+ { .m = { .sec = 0, .tb = 0 }, 0x3, {0x040000, 256 * 1024} },
+ { .m = { .sec = 0, .tb = 1 }, 0x1, {0x000000, 64 * 1024} },
+ { .m = { .sec = 0, .tb = 1 }, 0x2, {0x000000, 128 * 1024} },
+ { .m = { .sec = 0, .tb = 1 }, 0x3, {0x000000, 256 * 1024} },
+ { .m = { .sec = 0, .tb = X }, 0x4, {0x000000, 512 * 1024} }, /* All */
+ { .m = { .sec = 0, .tb = X }, 0x5, {0x000000, 512 * 1024} }, /* All */
+ { .m = { .sec = 0, .tb = X }, 0x6, {0x000000, 512 * 1024} }, /* All */
+ { .m = { .sec = 0, .tb = X }, 0x7, {0x000000, 512 * 1024} }, /* All */
+ { .m = { .sec = 1, .tb = 0 }, 0x1, {0x07F000, 4 * 1024} },
+ { .m = { .sec = 1, .tb = 0 }, 0x2, {0x07E000, 8 * 1024} },
+ { .m = { .sec = 1, .tb = 0 }, 0x3, {0x07C000, 16 * 1024} },
+ { .m = { .sec = 1, .tb = 0 }, 0x4, {0x078000, 32 * 1024} },
+ { .m = { .sec = 1, .tb = 0 }, 0x5, {0x078000, 32 * 1024} },
+ { .m = { .sec = 1, .tb = 0 }, 0x6, {0x078000, 32 * 1024} },
+ { .m = { .sec = 1, .tb = 1 }, 0x1, {0x000000, 4 * 1024} },
+ { .m = { .sec = 1, .tb = 1 }, 0x2, {0x000000, 8 * 1024} },
+ { .m = { .sec = 1, .tb = 1 }, 0x3, {0x000000, 16 * 1024} },
+ { .m = { .sec = 1, .tb = 1 }, 0x4, {0x000000, 32 * 1024} },
+ { .m = { .sec = 1, .tb = 1 }, 0x5, {0x000000, 32 * 1024} },
+ { .m = { .sec = 1, .tb = 1 }, 0x6, {0x000000, 32 * 1024} },
+ { .m = { .sec = 1, .tb = X }, 0x7, {0x000000, 512 * 1024} }, /* All */
+};
+
+static struct wp_range_descriptor gd25q40_cmp1_ranges[] = {
+ { .m = { .sec = X, .tb = X }, 0x0, {0x000000, 512 * 1024} }, /* ALL */
+ { .m = { .sec = 0, .tb = 0 }, 0x1, {0x000000, 448 * 1024} },
+ { .m = { .sec = 0, .tb = 0 }, 0x2, {0x000000, 384 * 1024} },
+ { .m = { .sec = 0, .tb = 0 }, 0x3, {0x000000, 256 * 1024} },
+
+ { .m = { .sec = 0, .tb = 1 }, 0x1, {0x010000, 448 * 1024} },
+ { .m = { .sec = 0, .tb = 1 }, 0x2, {0x020000, 384 * 1024} },
+ { .m = { .sec = 0, .tb = 1 }, 0x3, {0x040000, 256 * 1024} },
+
+ { .m = { .sec = 0, .tb = X }, 0x4, {0x000000, 0} }, /* None */
+ { .m = { .sec = 0, .tb = X }, 0x5, {0x000000, 0} }, /* None */
+ { .m = { .sec = 0, .tb = X }, 0x6, {0x000000, 0} }, /* None */
+ { .m = { .sec = 0, .tb = X }, 0x7, {0x000000, 0} }, /* None */
+
+ { .m = { .sec = 1, .tb = 0 }, 0x1, {0x000000, 508 * 1024} },
+ { .m = { .sec = 1, .tb = 0 }, 0x2, {0x000000, 504 * 1024} },
+ { .m = { .sec = 1, .tb = 0 }, 0x3, {0x000000, 496 * 1024} },
+ { .m = { .sec = 1, .tb = 0 }, 0x4, {0x000000, 480 * 1024} },
+ { .m = { .sec = 1, .tb = 0 }, 0x5, {0x000000, 480 * 1024} },
+ { .m = { .sec = 1, .tb = 0 }, 0x6, {0x000000, 480 * 1024} },
+
+ { .m = { .sec = 1, .tb = 1 }, 0x1, {0x001000, 508 * 1024} },
+ { .m = { .sec = 1, .tb = 1 }, 0x2, {0x002000, 504 * 1024} },
+ { .m = { .sec = 1, .tb = 1 }, 0x3, {0x004000, 496 * 1024} },
+ { .m = { .sec = 1, .tb = 1 }, 0x4, {0x008000, 480 * 1024} },
+ { .m = { .sec = 1, .tb = 1 }, 0x5, {0x008000, 480 * 1024} },
+ { .m = { .sec = 1, .tb = 1 }, 0x6, {0x008000, 480 * 1024} },
+
+ { .m = { .sec = 1, .tb = X }, 0x7, {0x000000, 0} }, /* None */
+};
+
+static struct wp_range_descriptor gd25q64_ranges[] = {
+ { .m = { .sec = X, .tb = X }, 0, {0, 0} }, /* none */
+ { .m = { .sec = 0, .tb = 0 }, 0x1, {0x7e0000, 128 * 1024} },
+ { .m = { .sec = 0, .tb = 0 }, 0x2, {0x7c0000, 256 * 1024} },
+ { .m = { .sec = 0, .tb = 0 }, 0x3, {0x780000, 512 * 1024} },
+ { .m = { .sec = 0, .tb = 0 }, 0x4, {0x700000, 1024 * 1024} },
+ { .m = { .sec = 0, .tb = 0 }, 0x5, {0x600000, 2048 * 1024} },
+ { .m = { .sec = 0, .tb = 0 }, 0x6, {0x400000, 4096 * 1024} },
+
+ { .m = { .sec = 0, .tb = 1 }, 0x1, {0x000000, 128 * 1024} },
+ { .m = { .sec = 0, .tb = 1 }, 0x2, {0x000000, 256 * 1024} },
+ { .m = { .sec = 0, .tb = 1 }, 0x3, {0x000000, 512 * 1024} },
+ { .m = { .sec = 0, .tb = 1 }, 0x4, {0x000000, 1024 * 1024} },
+ { .m = { .sec = 0, .tb = 1 }, 0x5, {0x000000, 2048 * 1024} },
+ { .m = { .sec = 0, .tb = 1 }, 0x6, {0x000000, 4096 * 1024} },
+ { .m = { .sec = X, .tb = X }, 0x7, {0x000000, 8192 * 1024} },
+
+ { .m = { .sec = 1, .tb = 0 }, 0x1, {0x7ff000, 4 * 1024} },
+ { .m = { .sec = 1, .tb = 0 }, 0x2, {0x7fe000, 8 * 1024} },
+ { .m = { .sec = 1, .tb = 0 }, 0x3, {0x7fc000, 16 * 1024} },
+ { .m = { .sec = 1, .tb = 0 }, 0x4, {0x7f8000, 32 * 1024} },
+ { .m = { .sec = 1, .tb = 0 }, 0x5, {0x7f8000, 32 * 1024} },
+ { .m = { .sec = 1, .tb = 0 }, 0x6, {0x7f8000, 32 * 1024} },
+
+ { .m = { .sec = 1, .tb = 1 }, 0x1, {0x000000, 4 * 1024} },
+ { .m = { .sec = 1, .tb = 1 }, 0x2, {0x000000, 8 * 1024} },
+ { .m = { .sec = 1, .tb = 1 }, 0x3, {0x000000, 16 * 1024} },
+ { .m = { .sec = 1, .tb = 1 }, 0x4, {0x000000, 32 * 1024} },
+ { .m = { .sec = 1, .tb = 1 }, 0x5, {0x000000, 32 * 1024} },
+ { .m = { .sec = 1, .tb = 1 }, 0x6, {0x000000, 32 * 1024} },
+};
+
+static struct wp_range_descriptor a25l040_ranges[] = {
+ { .m = { .sec = X, .tb = X }, 0x0, {0, 0} }, /* none */
+ { .m = { .sec = X, .tb = X }, 0x1, {0x70000, 64 * 1024} },
+ { .m = { .sec = X, .tb = X }, 0x2, {0x60000, 128 * 1024} },
+ { .m = { .sec = X, .tb = X }, 0x3, {0x40000, 256 * 1024} },
+ { .m = { .sec = X, .tb = X }, 0x4, {0x00000, 512 * 1024} },
+ { .m = { .sec = X, .tb = X }, 0x5, {0x00000, 512 * 1024} },
+ { .m = { .sec = X, .tb = X }, 0x6, {0x00000, 512 * 1024} },
+ { .m = { .sec = X, .tb = X }, 0x7, {0x00000, 512 * 1024} },
+};
+
+static uint8_t do_read_status(const struct flashctx *flash)
+{
+ if (flash->chip->read_status)
+ return flash->chip->read_status(flash);
+ else
+ return spi_read_status_register(flash);
+}
+
+static int do_write_status(const struct flashctx *flash, int status)
+{
+ if (flash->chip->write_status)
+ return flash->chip->write_status(flash, status);
+ else
+ return spi_write_status_register(flash, status);
+}
+
+/* FIXME: Move to spi25.c if it's a JEDEC standard opcode */
+static uint8_t w25q_read_status_register_2(const struct flashctx *flash)
+{
+ static const unsigned char cmd[JEDEC_RDSR_OUTSIZE] = { 0x35 };
+ unsigned char readarr[2];
+ int ret;
+
+ /* Read Status Register */
+ ret = spi_send_command(flash, sizeof(cmd), sizeof(readarr), cmd, readarr);
+ if (ret) {
+ /*
+ * FIXME: make this a benign failure for now in case we are
+ * unable to execute the opcode
+ */
+ msg_cdbg("RDSR2 failed!\n");
+ readarr[0] = 0x00;
+ }
+
+ return readarr[0];
+}
+
+/* FIXME: Move to spi25.c if it's a JEDEC standard opcode */
+uint8_t mx25l_read_config_register(const struct flashctx *flash);//XXX
+uint8_t mx25l_read_config_register(const struct flashctx *flash)
+{
+ static const unsigned char cmd[JEDEC_RDSR_OUTSIZE] = { 0x15 };
+ unsigned char readarr[2]; /* leave room for dummy byte */
+ int ret;
+
+ ret = spi_send_command(flash, sizeof(cmd), sizeof(readarr), cmd, readarr);
+ if (ret) {
+ msg_cdbg("RDCR failed!\n");
+ readarr[0] = 0x00;
+ }
+
+ return readarr[0];
+}
+
+/* Given a flash chip, this function returns its range table. */
+static int w25_range_table(const struct flashctx *flash,
+ struct wp_range_descriptor **descrs,
+ int *num_entries)
+{
+ uint8_t cr;
+
+ *descrs = 0;
+ *num_entries = 0;
+
+ switch (flash->chip->manufacture_id) {
+ case WINBOND_NEX_ID:
+ switch(flash->chip->model_id) {
+ case WINBOND_NEX_W25X10:
+ *descrs = w25x10_ranges;
+ *num_entries = ARRAY_SIZE(w25x10_ranges);
+ break;
+ case WINBOND_NEX_W25X20:
+ *descrs = w25x20_ranges;
+ *num_entries = ARRAY_SIZE(w25x20_ranges);
+ break;
+ case WINBOND_NEX_W25X40:
+ *descrs = w25x40_ranges;
+ *num_entries = ARRAY_SIZE(w25x40_ranges);
+ break;
+ case WINBOND_NEX_W25X80:
+ *descrs = w25x80_ranges;
+ *num_entries = ARRAY_SIZE(w25x80_ranges);
+ break;
+ case WINBOND_NEX_W25Q80_V:
+ *descrs = w25q80_ranges;
+ *num_entries = ARRAY_SIZE(w25q80_ranges);
+ break;
+ case WINBOND_NEX_W25Q16_V:
+ *descrs = w25q16_ranges;
+ *num_entries = ARRAY_SIZE(w25q16_ranges);
+ break;
+ case WINBOND_NEX_W25Q32_V:
+ case WINBOND_NEX_W25Q32_W:
+ //case WINBOND_NEX_W25Q32JW:
+ *descrs = w25q32_ranges;
+ *num_entries = ARRAY_SIZE(w25q32_ranges);
+ break;
+ case WINBOND_NEX_W25Q64_V:
+ case WINBOND_NEX_W25Q64_W:
+ *descrs = w25q64_ranges;
+ *num_entries = ARRAY_SIZE(w25q64_ranges);
+ break;
+ case WINBOND_NEX_W25Q128_DTR:
+ case WINBOND_NEX_W25Q128_V_M:
+ case WINBOND_NEX_W25Q128_V:
+ case WINBOND_NEX_W25Q128_W:
+ if (w25q_read_status_register_2(flash) & (1 << 6)) {
+ /* CMP == 1 */
+ *descrs = w25rq128_cmp1_ranges;
+ *num_entries = ARRAY_SIZE(w25rq128_cmp1_ranges);
+ } else {
+ /* CMP == 0 */
+ *descrs = w25rq128_cmp0_ranges;
+ *num_entries = ARRAY_SIZE(w25rq128_cmp0_ranges);
+ }
+ break;
+ case WINBOND_NEX_W25Q256JV_M:
+ if (w25q_read_status_register_2(flash) & (1 << 6)) {
+ /* CMP == 1 */
+ *descrs = w25rq256_cmp1_ranges;
+ *num_entries = ARRAY_SIZE(w25rq256_cmp1_ranges);
+ } else {
+ /* CMP == 0 */
+ *descrs = w25rq256_cmp0_ranges;
+ *num_entries = ARRAY_SIZE(w25rq256_cmp0_ranges);
+ }
+ break;
+ default:
+ msg_cerr("%s() %d: WINBOND flash chip mismatch (0x%04x)"
+ ", aborting\n", __func__, __LINE__,
+ flash->chip->model_id);
+ return -1;
+ }
+ break;
+ case EON_ID_NOPREFIX:
+ switch (flash->chip->model_id) {
+ case EON_EN25F40:
+ *descrs = en25f40_ranges;
+ *num_entries = ARRAY_SIZE(en25f40_ranges);
+ break;
+ case EON_EN25Q40:
+ *descrs = en25q40_ranges;
+ *num_entries = ARRAY_SIZE(en25q40_ranges);
+ break;
+ case EON_EN25Q80:
+ *descrs = en25q80_ranges;
+ *num_entries = ARRAY_SIZE(en25q80_ranges);
+ break;
+ case EON_EN25Q32:
+ *descrs = en25q32_ranges;
+ *num_entries = ARRAY_SIZE(en25q32_ranges);
+ break;
+ case EON_EN25Q64:
+ *descrs = en25q64_ranges;
+ *num_entries = ARRAY_SIZE(en25q64_ranges);
+ break;
+ case EON_EN25Q128:
+ *descrs = en25q128_ranges;
+ *num_entries = ARRAY_SIZE(en25q128_ranges);
+ break;
+ case EON_EN25S64:
+ *descrs = en25s64_ranges;
+ *num_entries = ARRAY_SIZE(en25s64_ranges);
+ break;
+ default:
+ msg_cerr("%s():%d: EON flash chip mismatch (0x%04x)"
+ ", aborting\n", __func__, __LINE__,
+ flash->chip->model_id);
+ return -1;
+ }
+ break;
+ case MACRONIX_ID:
+ switch (flash->chip->model_id) {
+ case MACRONIX_MX25L1005:
+ *descrs = mx25l1005_ranges;
+ *num_entries = ARRAY_SIZE(mx25l1005_ranges);
+ break;
+ case MACRONIX_MX25L2005:
+ *descrs = mx25l2005_ranges;
+ *num_entries = ARRAY_SIZE(mx25l2005_ranges);
+ break;
+ case MACRONIX_MX25L4005:
+ *descrs = mx25l4005_ranges;
+ *num_entries = ARRAY_SIZE(mx25l4005_ranges);
+ break;
+ case MACRONIX_MX25L8005:
+ *descrs = mx25l8005_ranges;
+ *num_entries = ARRAY_SIZE(mx25l8005_ranges);
+ break;
+ case MACRONIX_MX25L1605:
+ /* FIXME: MX25L1605 and MX25L1605D have different write
+ * protection capabilities, but share IDs */
+ *descrs = mx25l1605d_ranges;
+ *num_entries = ARRAY_SIZE(mx25l1605d_ranges);
+ break;
+ case MACRONIX_MX25L3205:
+ *descrs = mx25l3205d_ranges;
+ *num_entries = ARRAY_SIZE(mx25l3205d_ranges);
+ break;
+ case MACRONIX_MX25U3235E:
+ *descrs = mx25u3235e_ranges;
+ *num_entries = ARRAY_SIZE(mx25u3235e_ranges);
+ break;
+ case MACRONIX_MX25U6435E:
+ *descrs = mx25u6435e_ranges;
+ *num_entries = ARRAY_SIZE(mx25u6435e_ranges);
+ break;
+ case MACRONIX_MX25U12835E:
+ cr = mx25l_read_config_register(flash);
+ if (cr & MX25U12835E_TB) { /* T/B == 1 */
+ *descrs = mx25u12835e_tb1_ranges;
+ *num_entries = ARRAY_SIZE(mx25u12835e_tb1_ranges);
+ } else { /* T/B == 0 */
+ *descrs = mx25u12835e_tb0_ranges;
+ *num_entries = ARRAY_SIZE(mx25u12835e_tb0_ranges);
+ }
+ break;
+ default:
+ msg_cerr("%s():%d: MXIC flash chip mismatch (0x%04x)"
+ ", aborting\n", __func__, __LINE__,
+ flash->chip->model_id);
+ return -1;
+ }
+ break;
+ case ST_ID:
+ switch(flash->chip->model_id) {
+ case ST_N25Q064__1E:
+ case ST_N25Q064__3E:
+ *descrs = n25q064_ranges;
+ *num_entries = ARRAY_SIZE(n25q064_ranges);
+ break;
+ default:
+ msg_cerr("%s() %d: Micron flash chip mismatch"
+ " (0x%04x), aborting\n", __func__, __LINE__,
+ flash->chip->model_id);
+ return -1;
+ }
+ break;
+ case GIGADEVICE_ID:
+ switch(flash->chip->model_id) {
+ case GIGADEVICE_GD25LQ32:
+ *descrs = w25q32_ranges;
+ *num_entries = ARRAY_SIZE(w25q32_ranges);
+ break;
+ case GIGADEVICE_GD25Q40:
+ if (w25q_read_status_register_2(flash) & (1 << 6)) {
+ /* CMP == 1 */
+ *descrs = gd25q40_cmp1_ranges;
+ *num_entries = ARRAY_SIZE(gd25q40_cmp1_ranges);
+ } else {
+ *descrs = gd25q40_cmp0_ranges;
+ *num_entries = ARRAY_SIZE(gd25q40_cmp0_ranges);
+ }
+ break;
+ case GIGADEVICE_GD25Q64:
+ case GIGADEVICE_GD25LQ64:
+ *descrs = gd25q64_ranges;
+ *num_entries = ARRAY_SIZE(gd25q64_ranges);
+ break;
+ case GIGADEVICE_GD25Q128:
+ case GIGADEVICE_GD25LQ128CD:
+ if (w25q_read_status_register_2(flash) & (1 << 6)) {
+ /* CMP == 1 */
+ *descrs = w25rq128_cmp1_ranges;
+ *num_entries = ARRAY_SIZE(w25rq128_cmp1_ranges);
+ } else {
+ /* CMP == 0 */
+ *descrs = w25rq128_cmp0_ranges;
+ *num_entries = ARRAY_SIZE(w25rq128_cmp0_ranges);
+ }
+ break;
+ case GIGADEVICE_GD25Q256D:
+ *descrs = w25rq256_cmp0_ranges;
+ *num_entries = ARRAY_SIZE(w25rq256_cmp0_ranges);
+ break;
+ default:
+ msg_cerr("%s() %d: GigaDevice flash chip mismatch"
+ " (0x%04x), aborting\n", __func__, __LINE__,
+ flash->chip->model_id);
+ return -1;
+ }
+ break;
+ case AMIC_ID_NOPREFIX:
+ switch(flash->chip->model_id) {
+ case AMIC_A25L040:
+ *descrs = a25l040_ranges;
+ *num_entries = ARRAY_SIZE(a25l040_ranges);
+ break;
+ default:
+ msg_cerr("%s() %d: AMIC flash chip mismatch"
+ " (0x%04x), aborting\n", __func__, __LINE__,
+ flash->chip->model_id);
+ return -1;
+ }
+ break;
+ case ATMEL_ID:
+ switch(flash->chip->model_id) {
+ //case ATMEL_AT25SF128A:
+ case ATMEL_AT25SL128A:
+ if (w25q_read_status_register_2(flash) & (1 << 6)) {
+ /* CMP == 1 */
+ *descrs = w25rq128_cmp1_ranges;
+ *num_entries = ARRAY_SIZE(w25rq128_cmp1_ranges);
+ } else {
+ /* CMP == 0 */
+ *descrs = w25rq128_cmp0_ranges;
+ *num_entries = ARRAY_SIZE(w25rq128_cmp0_ranges);
+ }
+ break;
+ default:
+ msg_cerr("%s() %d: Atmel flash chip mismatch"
+ " (0x%04x), aborting\n", __func__, __LINE__,
+ flash->chip->model_id);
+ return -1;
+ }
+ break;
+ default:
+ msg_cerr("%s: flash vendor (0x%x) not found, aborting\n",
+ __func__, flash->chip->manufacture_id);
+ return -1;
+ }
+
+ return 0;
+}
+
+int w25_range_to_status(const struct flashctx *flash,
+ unsigned int start, unsigned int len,
+ struct w25q_status *status)
+{
+ struct wp_range_descriptor *descrs;
+ int i, range_found = 0;
+ int num_entries;
+
+ if (w25_range_table(flash, &descrs, &num_entries))
+ return -1;
+
+ for (i = 0; i < num_entries; i++) {
+ struct wp_range *r = &descrs[i].range;
+
+ msg_cspew("comparing range 0x%x 0x%x / 0x%x 0x%x\n",
+ start, len, r->start, r->len);
+ if ((start == r->start) && (len == r->len)) {
+ status->bp0 = descrs[i].bp & 1;
+ status->bp1 = descrs[i].bp >> 1;
+ status->bp2 = descrs[i].bp >> 2;
+ status->tb = descrs[i].m.tb;
+ status->sec = descrs[i].m.sec;
+
+ range_found = 1;
+ break;
+ }
+ }
+
+ if (!range_found) {
+ msg_cerr("%s: matching range not found\n", __func__);
+ return -1;
+ }
+
+ return 0;
+}
+
+int w25_status_to_range(const struct flashctx *flash,
+ const struct w25q_status *status,
+ unsigned int *start, unsigned int *len)
+{
+ struct wp_range_descriptor *descrs;
+ int i, status_found = 0;
+ int num_entries;
+
+ if (w25_range_table(flash, &descrs, &num_entries))
+ return -1;
+
+ for (i = 0; i < num_entries; i++) {
+ int bp;
+ int table_bp, table_tb, table_sec;
+
+ bp = status->bp0 | (status->bp1 << 1) | (status->bp2 << 2);
+ msg_cspew("comparing 0x%x 0x%x / 0x%x 0x%x / 0x%x 0x%x\n",
+ bp, descrs[i].bp,
+ status->tb, descrs[i].m.tb,
+ status->sec, descrs[i].m.sec);
+ table_bp = descrs[i].bp;
+ table_tb = descrs[i].m.tb;
+ table_sec = descrs[i].m.sec;
+ if ((bp == table_bp || table_bp == X) &&
+ (status->tb == table_tb || table_tb == X) &&
+ (status->sec == table_sec || table_sec == X)) {
+ *start = descrs[i].range.start;
+ *len = descrs[i].range.len;
+
+ status_found = 1;
+ break;
+ }
+ }
+
+ if (!status_found) {
+ msg_cerr("matching status not found\n");
+ return -1;
+ }
+
+ return 0;
+}
+
+/* Given a [start, len], this function calls w25_range_to_status() to convert
+ * it to flash-chip-specific range bits, then sets into status register.
+ */
+static int w25_set_range(const struct flashctx *flash,
+ unsigned int start, unsigned int len)
+{
+ struct w25q_status status;
+ int tmp = 0;
+ int expected = 0;
+
+ memset(&status, 0, sizeof(status));
+ tmp = do_read_status(flash);
+ memcpy(&status, &tmp, 1);
+ msg_cdbg("%s: old status: 0x%02x\n", __func__, tmp);
+
+ if (w25_range_to_status(flash, start, len, &status))
+ return -1;
+
+ msg_cdbg("status.busy: %x\n", status.busy);
+ msg_cdbg("status.wel: %x\n", status.wel);
+ msg_cdbg("status.bp0: %x\n", status.bp0);
+ msg_cdbg("status.bp1: %x\n", status.bp1);
+ msg_cdbg("status.bp2: %x\n", status.bp2);
+ msg_cdbg("status.tb: %x\n", status.tb);
+ msg_cdbg("status.sec: %x\n", status.sec);
+ msg_cdbg("status.srp0: %x\n", status.srp0);
+
+ memcpy(&expected, &status, sizeof(status));
+ do_write_status(flash, expected);
+
+ tmp = do_read_status(flash);
+ msg_cdbg("%s: new status: 0x%02x\n", __func__, tmp);
+ if ((tmp & MASK_WP_AREA) != (expected & MASK_WP_AREA)) {
+ msg_cerr("expected=0x%02x, but actual=0x%02x.\n",
+ expected, tmp);
+ return 1;
+ }
+
+ return 0;
+}
+
+/* Print out the current status register value with human-readable text. */
+static int w25_wp_status(const struct flashctx *flash)
+{
+ struct w25q_status status;
+ int tmp;
+ unsigned int start, len;
+ int ret = 0;
+
+ memset(&status, 0, sizeof(status));
+ tmp = do_read_status(flash);
+ memcpy(&status, &tmp, 1);
+ msg_cinfo("WP: status: 0x%02x\n", tmp);
+ msg_cinfo("WP: status.srp0: %x\n", status.srp0);
+ msg_cinfo("WP: write protect is %s.\n",
+ status.srp0 ? "enabled" : "disabled");
+
+ msg_cinfo("WP: write protect range: ");
+ if (w25_status_to_range(flash, &status, &start, &len)) {
+ msg_cinfo("(cannot resolve the range)\n");
+ ret = -1;
+ } else {
+ msg_cinfo("start=0x%08x, len=0x%08x\n", start, len);
+ }
+
+ return ret;
+}
+
+static int w25q_large_range_to_status(const struct flashctx *flash,
+ unsigned int start, unsigned int len,
+ struct w25q_status_large *status)
+{
+ struct wp_range_descriptor *descrs;
+ int i, range_found = 0;
+ int num_entries;
+
+ if (w25_range_table(flash, &descrs, &num_entries))
+ return -1;
+
+ for (i = 0; i < num_entries; i++) {
+ struct wp_range *r = &descrs[i].range;
+
+ msg_cspew("comparing range 0x%x 0x%x / 0x%x 0x%x\n",
+ start, len, r->start, r->len);
+ if ((start == r->start) && (len == r->len)) {
+ status->bp0 = descrs[i].bp & 1;
+ status->bp1 = descrs[i].bp >> 1;
+ status->bp2 = descrs[i].bp >> 2;
+ status->bp3 = descrs[i].bp >> 3;
+ /*
+ * For MX25U12835E chip, Top/Bottom (T/B) bit is not
+ * part of status register and in that bit position is
+ * Quad Enable (QE)
+ */
+ if (flash->chip->manufacture_id != MACRONIX_ID ||
+ flash->chip->model_id != MACRONIX_MX25U12835E)
+ status->tb = descrs[i].m.tb;
+
+ range_found = 1;
+ break;
+ }
+ }
+
+ if (!range_found) {
+ msg_cerr("%s: matching range not found\n", __func__);
+ return -1;
+ }
+
+ return 0;
+}
+
+static int w25_large_status_to_range(const struct flashctx *flash,
+ const struct w25q_status_large *status,
+ unsigned int *start, unsigned int *len)
+{
+ struct wp_range_descriptor *descrs;
+ int i, status_found = 0;
+ int num_entries;
+
+ if (w25_range_table(flash, &descrs, &num_entries))
+ return -1;
+
+ for (i = 0; i < num_entries; i++) {
+ int bp;
+ int table_bp, table_tb;
+
+ bp = status->bp0 | (status->bp1 << 1) | (status->bp2 << 2) |
+ (status->bp3 << 3);
+ msg_cspew("comparing 0x%x 0x%x / 0x%x 0x%x\n",
+ bp, descrs[i].bp,
+ status->tb, descrs[i].m.tb);
+ table_bp = descrs[i].bp;
+ table_tb = descrs[i].m.tb;
+ if ((bp == table_bp || table_bp == X) &&
+ (status->tb == table_tb || table_tb == X)) {
+ *start = descrs[i].range.start;
+ *len = descrs[i].range.len;
+
+ status_found = 1;
+ break;
+ }
+ }
+
+ if (!status_found) {
+ msg_cerr("matching status not found\n");
+ return -1;
+ }
+
+ return 0;
+}
+
+/* Given a [start, len], this function calls w25_range_to_status() to convert
+ * it to flash-chip-specific range bits, then sets into status register.
+ * Returns 0 if successful, -1 on error, and 1 if reading back was different.
+ */
+static int w25q_large_set_range(const struct flashctx *flash,
+ unsigned int start, unsigned int len)
+{
+ struct w25q_status_large status;
+ int tmp;
+ int expected = 0;
+
+ memset(&status, 0, sizeof(status));
+ tmp = do_read_status(flash);
+ memcpy(&status, &tmp, 1);
+ msg_cdbg("%s: old status: 0x%02x\n", __func__, tmp);
+
+ if (w25q_large_range_to_status(flash, start, len, &status))
+ return -1;
+
+ msg_cdbg("status.busy: %x\n", status.busy);
+ msg_cdbg("status.wel: %x\n", status.wel);
+ msg_cdbg("status.bp0: %x\n", status.bp0);
+ msg_cdbg("status.bp1: %x\n", status.bp1);
+ msg_cdbg("status.bp2: %x\n", status.bp2);
+ msg_cdbg("status.bp3: %x\n", status.bp3);
+ msg_cdbg("status.tb: %x\n", status.tb);
+ msg_cdbg("status.srp0: %x\n", status.srp0);
+
+ memcpy(&expected, &status, sizeof(status));
+ do_write_status(flash, expected);
+
+ tmp = do_read_status(flash);
+ msg_cdbg("%s: new status: 0x%02x\n", __func__, tmp);
+ if ((tmp & MASK_WP_AREA_LARGE) != (expected & MASK_WP_AREA_LARGE)) {
+ msg_cerr("expected=0x%02x, but actual=0x%02x.\n",
+ expected, tmp);
+ return 1;
+ }
+
+ return 0;
+}
+
+static int w25q_large_wp_status(const struct flashctx *flash)
+{
+ struct w25q_status_large sr1;
+ struct w25q_status_2 sr2;
+ uint8_t tmp[2];
+ unsigned int start, len;
+ int ret = 0;
+
+ memset(&sr1, 0, sizeof(sr1));
+ tmp[0] = do_read_status(flash);
+ memcpy(&sr1, &tmp[0], 1);
+
+ memset(&sr2, 0, sizeof(sr2));
+ tmp[1] = w25q_read_status_register_2(flash);
+ memcpy(&sr2, &tmp[1], 1);
+
+ msg_cinfo("WP: status: 0x%02x%02x\n", tmp[1], tmp[0]);
+ msg_cinfo("WP: status.srp0: %x\n", sr1.srp0);
+ msg_cinfo("WP: status.srp1: %x\n", sr2.srp1);
+ msg_cinfo("WP: write protect is %s.\n",
+ (sr1.srp0 || sr2.srp1) ? "enabled" : "disabled");
+
+ msg_cinfo("WP: write protect range: ");
+ if (w25_large_status_to_range(flash, &sr1, &start, &len)) {
+ msg_cinfo("(cannot resolve the range)\n");
+ ret = -1;
+ } else {
+ msg_cinfo("start=0x%08x, len=0x%08x\n", start, len);
+ }
+
+ return ret;
+}
+
+/* Set/clear the SRP0 bit in the status register. */
+static int w25_set_srp0(const struct flashctx *flash, int enable)
+{
+ struct w25q_status status;
+ int tmp = 0;
+ int expected = 0;
+
+ memset(&status, 0, sizeof(status));
+ tmp = do_read_status(flash);
+ /* FIXME: this is NOT endian-free copy. */
+ memcpy(&status, &tmp, 1);
+ msg_cdbg("%s: old status: 0x%02x\n", __func__, tmp);
+
+ status.srp0 = enable ? 1 : 0;
+ memcpy(&expected, &status, sizeof(status));
+ do_write_status(flash, expected);
+
+ tmp = do_read_status(flash);
+ msg_cdbg("%s: new status: 0x%02x\n", __func__, tmp);
+ if ((tmp & MASK_WP_AREA) != (expected & MASK_WP_AREA))
+ return 1;
+
+ return 0;
+}
+
+static int w25_enable_writeprotect(const struct flashctx *flash,
+ enum wp_mode wp_mode)
+{
+ int ret;
+
+ if (wp_mode != WP_MODE_HARDWARE) {
+ msg_cerr("%s(): unsupported write-protect mode\n", __func__);
+ return 1;
+ }
+
+ ret = w25_set_srp0(flash, 1);
+ if (ret)
+ msg_cerr("%s(): error=%d.\n", __func__, ret);
+ return ret;
+}
+
+static int w25_disable_writeprotect(const struct flashctx *flash)
+{
+ int ret;
+
+ ret = w25_set_srp0(flash, 0);
+ if (ret)
+ msg_cerr("%s(): error=%d.\n", __func__, ret);
+
+ return ret;
+}
+
+static int w25_list_ranges(const struct flashctx *flash)
+{
+ struct wp_range_descriptor *descrs;
+ int i, num_entries;
+
+ if (w25_range_table(flash, &descrs, &num_entries))
+ return -1;
+
+ for (i = 0; i < num_entries; i++) {
+ msg_cinfo("start: 0x%06x, length: 0x%06x\n",
+ descrs[i].range.start,
+ descrs[i].range.len);
+ }
+
+ return 0;
+}
+
+static int w25q_wp_status(const struct flashctx *flash)
+{
+ struct w25q_status sr1;
+ struct w25q_status_2 sr2;
+ uint8_t tmp[2];
+ unsigned int start, len;
+ int ret = 0;
+
+ memset(&sr1, 0, sizeof(sr1));
+ tmp[0] = do_read_status(flash);
+ memcpy(&sr1, &tmp[0], 1);
+
+ memset(&sr2, 0, sizeof(sr2));
+ tmp[1] = w25q_read_status_register_2(flash);
+ memcpy(&sr2, &tmp[1], 1);
+
+ msg_cinfo("WP: status: 0x%02x%02x\n", tmp[1], tmp[0]);
+ msg_cinfo("WP: status.srp0: %x\n", sr1.srp0);
+ msg_cinfo("WP: status.srp1: %x\n", sr2.srp1);
+ msg_cinfo("WP: write protect is %s.\n",
+ (sr1.srp0 || sr2.srp1) ? "enabled" : "disabled");
+
+ msg_cinfo("WP: write protect range: ");
+ if (w25_status_to_range(flash, &sr1, &start, &len)) {
+ msg_cinfo("(cannot resolve the range)\n");
+ ret = -1;
+ } else {
+ msg_cinfo("start=0x%08x, len=0x%08x\n", start, len);
+ }
+
+ return ret;
+}
+
+/*
+ * W25Q adds an optional byte to the standard WRSR opcode. If /CS is
+ * de-asserted after the first byte, then it acts like a JEDEC-standard
+ * WRSR command. if /CS is asserted, then the next data byte is written
+ * into status register 2.
+ */
+#define W25Q_WRSR_OUTSIZE 0x03
+static int w25q_write_status_register_WREN(const struct flashctx *flash, uint8_t s1, uint8_t s2)
+{
+ int result;
+ struct spi_command cmds[] = {
+ {
+ /* FIXME: WRSR requires either EWSR or WREN depending on chip type. */
+ .writecnt = JEDEC_WREN_OUTSIZE,
+ .writearr = (const unsigned char[]){ JEDEC_WREN },
+ .readcnt = 0,
+ .readarr = NULL,
+ }, {
+ .writecnt = W25Q_WRSR_OUTSIZE,
+ .writearr = (const unsigned char[]){ JEDEC_WRSR, s1, s2 },
+ .readcnt = 0,
+ .readarr = NULL,
+ }, {
+ .writecnt = 0,
+ .writearr = NULL,
+ .readcnt = 0,
+ .readarr = NULL,
+ }};
+
+ result = spi_send_multicommand(flash, cmds);
+ if (result) {
+ msg_cerr("%s failed during command execution\n",
+ __func__);
+ }
+
+ /* WRSR performs a self-timed erase before the changes take effect. */
+ programmer_delay(100 * 1000);
+
+ return result;
+}
+
+/*
+ * Set/clear the SRP1 bit in status register 2.
+ * FIXME: make this more generic if other chips use the same SR2 layout
+ */
+static int w25q_set_srp1(const struct flashctx *flash, int enable)
+{
+ struct w25q_status sr1;
+ struct w25q_status_2 sr2;
+ uint8_t tmp, expected;
+
+ tmp = do_read_status(flash);
+ memcpy(&sr1, &tmp, 1);
+ tmp = w25q_read_status_register_2(flash);
+ memcpy(&sr2, &tmp, 1);
+
+ msg_cdbg("%s: old status 2: 0x%02x\n", __func__, tmp);
+
+ sr2.srp1 = enable ? 1 : 0;
+
+ memcpy(&expected, &sr2, 1);
+ w25q_write_status_register_WREN(flash, *((uint8_t *)&sr1), *((uint8_t *)&sr2));
+
+ tmp = w25q_read_status_register_2(flash);
+ msg_cdbg("%s: new status 2: 0x%02x\n", __func__, tmp);
+ if ((tmp & MASK_WP2_AREA) != (expected & MASK_WP2_AREA))
+ return 1;
+
+ return 0;
+}
+
+enum wp_mode get_wp_mode(const char *mode_str)
+{
+ enum wp_mode wp_mode = WP_MODE_UNKNOWN;
+
+ if (!strcasecmp(mode_str, "hardware"))
+ wp_mode = WP_MODE_HARDWARE;
+ else if (!strcasecmp(mode_str, "power_cycle"))
+ wp_mode = WP_MODE_POWER_CYCLE;
+ else if (!strcasecmp(mode_str, "permanent"))
+ wp_mode = WP_MODE_PERMANENT;
+
+ return wp_mode;
+}
+
+static int w25q_disable_writeprotect(const struct flashctx *flash,
+ enum wp_mode wp_mode)
+{
+ int ret = 1;
+ struct w25q_status_2 sr2;
+ uint8_t tmp;
+
+ switch (wp_mode) {
+ case WP_MODE_HARDWARE:
+ ret = w25_set_srp0(flash, 0);
+ break;
+ case WP_MODE_POWER_CYCLE:
+ tmp = w25q_read_status_register_2(flash);
+ memcpy(&sr2, &tmp, 1);
+ if (sr2.srp1) {
+ msg_cerr("%s(): must disconnect power to disable "
+ "write-protection\n", __func__);
+ } else {
+ ret = 0;
+ }
+ break;
+ case WP_MODE_PERMANENT:
+ msg_cerr("%s(): cannot disable permanent write-protection\n",
+ __func__);
+ break;
+ default:
+ msg_cerr("%s(): invalid mode specified\n", __func__);
+ break;
+ }
+
+ if (ret)
+ msg_cerr("%s(): error=%d.\n", __func__, ret);
+
+ return ret;
+}
+
+static int w25q_disable_writeprotect_default(const struct flashctx *flash)
+{
+ return w25q_disable_writeprotect(flash, WP_MODE_HARDWARE);
+}
+
+static int w25q_enable_writeprotect(const struct flashctx *flash,
+ enum wp_mode wp_mode)
+{
+ int ret = 1;
+ struct w25q_status sr1;
+ struct w25q_status_2 sr2;
+ uint8_t tmp;
+
+ switch (wp_mode) {
+ case WP_MODE_HARDWARE:
+ if (w25q_disable_writeprotect(flash, WP_MODE_POWER_CYCLE)) {
+ msg_cerr("%s(): cannot disable power cycle WP mode\n",
+ __func__);
+ break;
+ }
+
+ tmp = do_read_status(flash);
+ memcpy(&sr1, &tmp, 1);
+ if (sr1.srp0)
+ ret = 0;
+ else
+ ret = w25_set_srp0(flash, 1);
+
+ break;
+ case WP_MODE_POWER_CYCLE:
+ if (w25q_disable_writeprotect(flash, WP_MODE_HARDWARE)) {
+ msg_cerr("%s(): cannot disable hardware WP mode\n",
+ __func__);
+ break;
+ }
+
+ tmp = w25q_read_status_register_2(flash);
+ memcpy(&sr2, &tmp, 1);
+ if (sr2.srp1)
+ ret = 0;
+ else
+ ret = w25q_set_srp1(flash, 1);
+
+ break;
+ case WP_MODE_PERMANENT:
+ tmp = do_read_status(flash);
+ memcpy(&sr1, &tmp, 1);
+ if (sr1.srp0 == 0) {
+ ret = w25_set_srp0(flash, 1);
+ if (ret) {
+ msg_perr("%s(): cannot enable SRP0 for "
+ "permanent WP\n", __func__);
+ break;
+ }
+ }
+
+ tmp = w25q_read_status_register_2(flash);
+ memcpy(&sr2, &tmp, 1);
+ if (sr2.srp1 == 0) {
+ ret = w25q_set_srp1(flash, 1);
+ if (ret) {
+ msg_perr("%s(): cannot enable SRP1 for "
+ "permanent WP\n", __func__);
+ break;
+ }
+ }
+
+ break;
+ default:
+ msg_perr("%s(): invalid mode %d\n", __func__, wp_mode);
+ break;
+ }
+
+ if (ret)
+ msg_cerr("%s(): error=%d.\n", __func__, ret);
+ return ret;
+}
+
+/* W25P, W25X, and many flash chips from various vendors */
+struct wp wp_w25 = {
+ .list_ranges = w25_list_ranges,
+ .set_range = w25_set_range,
+ .enable = w25_enable_writeprotect,
+ .disable = w25_disable_writeprotect,
+ .wp_status = w25_wp_status,
+
+};
+
+/* W25Q series has features such as a second status register and SFDP */
+struct wp wp_w25q = {
+ .list_ranges = w25_list_ranges,
+ .set_range = w25_set_range,
+ .enable = w25q_enable_writeprotect,
+ /*
+ * By default, disable hardware write-protection. We may change
+ * this later if we want to add fine-grained write-protect disable
+ * as a command-line option.
+ */
+ .disable = w25q_disable_writeprotect_default,
+ .wp_status = w25q_wp_status,
+};
+
+/* W25Q large series has 4 block-protect bits */
+struct wp wp_w25q_large = {
+ .list_ranges = w25_list_ranges,
+ .set_range = w25q_large_set_range,
+ .enable = w25q_enable_writeprotect,
+ /*
+ * By default, disable hardware write-protection. We may change
+ * this later if we want to add fine-grained write-protect disable
+ * as a command-line option.
+ */
+ .disable = w25q_disable_writeprotect_default,
+ .wp_status = w25q_large_wp_status,
+};
+
+struct wp_range_descriptor gd25q32_cmp0_ranges[] = {
+ /* none, bp4 and bp3 => don't care */
+ { { }, 0x00, {0, 0} },
+ { { }, 0x08, {0, 0} },
+ { { }, 0x10, {0, 0} },
+ { { }, 0x18, {0, 0} },
+
+ { { }, 0x01, {0x3f0000, 64 * 1024} },
+ { { }, 0x02, {0x3e0000, 128 * 1024} },
+ { { }, 0x03, {0x3c0000, 256 * 1024} },
+ { { }, 0x04, {0x380000, 512 * 1024} },
+ { { }, 0x05, {0x300000, 1024 * 1024} },
+ { { }, 0x06, {0x200000, 2048 * 1024} },
+
+ { { }, 0x09, {0x000000, 64 * 1024} },
+ { { }, 0x0a, {0x000000, 128 * 1024} },
+ { { }, 0x0b, {0x000000, 256 * 1024} },
+ { { }, 0x0c, {0x000000, 512 * 1024} },
+ { { }, 0x0d, {0x000000, 1024 * 1024} },
+ { { }, 0x0e, {0x000000, 2048 * 1024} },
+
+ /* all, bp4 and bp3 => don't care */
+ { { }, 0x07, {0x000000, 4096 * 1024} },
+ { { }, 0x0f, {0x000000, 4096 * 1024} },
+ { { }, 0x17, {0x000000, 4096 * 1024} },
+ { { }, 0x1f, {0x000000, 4096 * 1024} },
+
+ { { }, 0x11, {0x3ff000, 4 * 1024} },
+ { { }, 0x12, {0x3fe000, 8 * 1024} },
+ { { }, 0x13, {0x3fc000, 16 * 1024} },
+ { { }, 0x14, {0x3f8000, 32 * 1024} }, /* bp0 => don't care */
+ { { }, 0x15, {0x3f8000, 32 * 1024} }, /* bp0 => don't care */
+ { { }, 0x16, {0x3f8000, 32 * 1024} },
+
+ { { }, 0x19, {0x000000, 4 * 1024} },
+ { { }, 0x1a, {0x000000, 8 * 1024} },
+ { { }, 0x1b, {0x000000, 16 * 1024} },
+ { { }, 0x1c, {0x000000, 32 * 1024} }, /* bp0 => don't care */
+ { { }, 0x1d, {0x000000, 32 * 1024} }, /* bp0 => don't care */
+ { { }, 0x1e, {0x000000, 32 * 1024} },
+};
+
+struct wp_range_descriptor gd25q32_cmp1_ranges[] = {
+ /* All, bp4 and bp3 => don't care */
+ { { }, 0x00, {0x000000, 4096 * 1024} }, /* All */
+ { { }, 0x08, {0x000000, 4096 * 1024} },
+ { { }, 0x10, {0x000000, 4096 * 1024} },
+ { { }, 0x18, {0x000000, 4096 * 1024} },
+
+ { { }, 0x01, {0x000000, 4032 * 1024} },
+ { { }, 0x02, {0x000000, 3968 * 1024} },
+ { { }, 0x03, {0x000000, 3840 * 1024} },
+ { { }, 0x04, {0x000000, 3584 * 1024} },
+ { { }, 0x05, {0x000000, 3 * 1024 * 1024} },
+ { { }, 0x06, {0x000000, 2 * 1024 * 1024} },
+
+ { { }, 0x09, {0x010000, 4032 * 1024} },
+ { { }, 0x0a, {0x020000, 3968 * 1024} },
+ { { }, 0x0b, {0x040000, 3840 * 1024} },
+ { { }, 0x0c, {0x080000, 3584 * 1024} },
+ { { }, 0x0d, {0x100000, 3 * 1024 * 1024} },
+ { { }, 0x0e, {0x200000, 2 * 1024 * 1024} },
+
+ /* None, bp4 and bp3 => don't care */
+ { { }, 0x07, {0, 0} }, /* None */
+ { { }, 0x0f, {0, 0} },
+ { { }, 0x17, {0, 0} },
+ { { }, 0x1f, {0, 0} },
+
+ { { }, 0x11, {0x000000, 4092 * 1024} },
+ { { }, 0x12, {0x000000, 4088 * 1024} },
+ { { }, 0x13, {0x000000, 4080 * 1024} },
+ { { }, 0x14, {0x000000, 4064 * 1024} }, /* bp0 => don't care */
+ { { }, 0x15, {0x000000, 4064 * 1024} }, /* bp0 => don't care */
+ { { }, 0x16, {0x000000, 4064 * 1024} },
+
+ { { }, 0x19, {0x001000, 4092 * 1024} },
+ { { }, 0x1a, {0x002000, 4088 * 1024} },
+ { { }, 0x1b, {0x040000, 4080 * 1024} },
+ { { }, 0x1c, {0x080000, 4064 * 1024} }, /* bp0 => don't care */
+ { { }, 0x1d, {0x080000, 4064 * 1024} }, /* bp0 => don't care */
+ { { }, 0x1e, {0x080000, 4064 * 1024} },
+};
+
+static struct wp_context gd25q32_wp = {
+ /* TODO: map second status register */
+ .sr1 = { .bp0_pos = 2, .bp_bits = 5, .srp_pos = 7 },
+};
+
+struct wp_range_descriptor gd25q128_cmp0_ranges[] = {
+ /* none, bp4 and bp3 => don't care, others = 0 */
+ { { .tb = 0 }, 0x00, {0, 0} },
+ { { .tb = 0 }, 0x08, {0, 0} },
+ { { .tb = 0 }, 0x10, {0, 0} },
+ { { .tb = 0 }, 0x18, {0, 0} },
+
+ { { .tb = 0 }, 0x01, {0xfc0000, 256 * 1024} },
+ { { .tb = 0 }, 0x02, {0xf80000, 512 * 1024} },
+ { { .tb = 0 }, 0x03, {0xf00000, 1024 * 1024} },
+ { { .tb = 0 }, 0x04, {0xe00000, 2048 * 1024} },
+ { { .tb = 0 }, 0x05, {0xc00000, 4096 * 1024} },
+ { { .tb = 0 }, 0x06, {0x800000, 8192 * 1024} },
+
+ { { .tb = 0 }, 0x09, {0x000000, 256 * 1024} },
+ { { .tb = 0 }, 0x0a, {0x000000, 512 * 1024} },
+ { { .tb = 0 }, 0x0b, {0x000000, 1024 * 1024} },
+ { { .tb = 0 }, 0x0c, {0x000000, 2048 * 1024} },
+ { { .tb = 0 }, 0x0d, {0x000000, 4096 * 1024} },
+ { { .tb = 0 }, 0x0e, {0x000000, 8192 * 1024} },
+
+ /* all, bp4 and bp3 => don't care, others = 1 */
+ { { .tb = 0 }, 0x07, {0x000000, 16384 * 1024} },
+ { { .tb = 0 }, 0x0f, {0x000000, 16384 * 1024} },
+ { { .tb = 0 }, 0x17, {0x000000, 16384 * 1024} },
+ { { .tb = 0 }, 0x1f, {0x000000, 16384 * 1024} },
+
+ { { .tb = 0 }, 0x11, {0xfff000, 4 * 1024} },
+ { { .tb = 0 }, 0x12, {0xffe000, 8 * 1024} },
+ { { .tb = 0 }, 0x13, {0xffc000, 16 * 1024} },
+ { { .tb = 0 }, 0x14, {0xff8000, 32 * 1024} }, /* bp0 => don't care */
+ { { .tb = 0 }, 0x15, {0xff8000, 32 * 1024} }, /* bp0 => don't care */
+
+ { { .tb = 0 }, 0x19, {0x000000, 4 * 1024} },
+ { { .tb = 0 }, 0x1a, {0x000000, 8 * 1024} },
+ { { .tb = 0 }, 0x1b, {0x000000, 16 * 1024} },
+ { { .tb = 0 }, 0x1c, {0x000000, 32 * 1024} }, /* bp0 => don't care */
+ { { .tb = 0 }, 0x1d, {0x000000, 32 * 1024} }, /* bp0 => don't care */
+ { { .tb = 0 }, 0x1e, {0x000000, 32 * 1024} },
+};
+
+struct wp_range_descriptor gd25q128_cmp1_ranges[] = {
+ /* none, bp4 and bp3 => don't care, others = 0 */
+ { { .tb = 1 }, 0x00, {0x000000, 16384 * 1024} },
+ { { .tb = 1 }, 0x08, {0x000000, 16384 * 1024} },
+ { { .tb = 1 }, 0x10, {0x000000, 16384 * 1024} },
+ { { .tb = 1 }, 0x18, {0x000000, 16384 * 1024} },
+
+ { { .tb = 1 }, 0x01, {0x000000, 16128 * 1024} },
+ { { .tb = 1 }, 0x02, {0x000000, 15872 * 1024} },
+ { { .tb = 1 }, 0x03, {0x000000, 15360 * 1024} },
+ { { .tb = 1 }, 0x04, {0x000000, 14336 * 1024} },
+ { { .tb = 1 }, 0x05, {0x000000, 12288 * 1024} },
+ { { .tb = 1 }, 0x06, {0x000000, 8192 * 1024} },
+
+ { { .tb = 1 }, 0x09, {0x000000, 16128 * 1024} },
+ { { .tb = 1 }, 0x0a, {0x000000, 15872 * 1024} },
+ { { .tb = 1 }, 0x0b, {0x000000, 15360 * 1024} },
+ { { .tb = 1 }, 0x0c, {0x000000, 14336 * 1024} },
+ { { .tb = 1 }, 0x0d, {0x000000, 12288 * 1024} },
+ { { .tb = 1 }, 0x0e, {0x000000, 8192 * 1024} },
+
+ /* none, bp4 and bp3 => don't care, others = 1 */
+ { { .tb = 1 }, 0x07, {0x000000, 16384 * 1024} },
+ { { .tb = 1 }, 0x08, {0x000000, 16384 * 1024} },
+ { { .tb = 1 }, 0x0f, {0x000000, 16384 * 1024} },
+ { { .tb = 1 }, 0x17, {0x000000, 16384 * 1024} },
+ { { .tb = 1 }, 0x1f, {0x000000, 16384 * 1024} },
+
+ { { .tb = 1 }, 0x11, {0x000000, 16380 * 1024} },
+ { { .tb = 1 }, 0x12, {0x000000, 16376 * 1024} },
+ { { .tb = 1 }, 0x13, {0x000000, 16368 * 1024} },
+ { { .tb = 1 }, 0x14, {0x000000, 16352 * 1024} }, /* bp0 => don't care */
+ { { .tb = 1 }, 0x15, {0x000000, 16352 * 1024} }, /* bp0 => don't care */
+
+ { { .tb = 1 }, 0x19, {0x001000, 16380 * 1024} },
+ { { .tb = 1 }, 0x1a, {0x002000, 16376 * 1024} },
+ { { .tb = 1 }, 0x1b, {0x004000, 16368 * 1024} },
+ { { .tb = 1 }, 0x1c, {0x008000, 16352 * 1024} }, /* bp0 => don't care */
+ { { .tb = 1 }, 0x1d, {0x008000, 16352 * 1024} }, /* bp0 => don't care */
+ { { .tb = 1 }, 0x1e, {0x008000, 16352 * 1024} },
+};
+
+static struct wp_context gd25q128_wp = {
+ /* TODO: map second and third status registers */
+ .sr1 = { .bp0_pos = 2, .bp_bits = 5, .srp_pos = 7 },
+};
+
+/* FIXME: MX25L6406 has same ID as MX25L6405D */
+struct wp_range_descriptor mx25l6406e_ranges[] = {
+ { { }, 0, {0, 0} }, /* none */
+ { { }, 0x1, {0x7e0000, 64 * 2 * 1024} }, /* blocks 126-127 */
+ { { }, 0x2, {0x7c0000, 64 * 4 * 1024} }, /* blocks 124-127 */
+ { { }, 0x3, {0x7a0000, 64 * 8 * 1024} }, /* blocks 120-127 */
+ { { }, 0x4, {0x700000, 64 * 16 * 1024} }, /* blocks 112-127 */
+ { { }, 0x5, {0x600000, 64 * 32 * 1024} }, /* blocks 96-127 */
+ { { }, 0x6, {0x400000, 64 * 64 * 1024} }, /* blocks 64-127 */
+
+ { { }, 0x7, {0x000000, 64 * 128 * 1024} }, /* all */
+ { { }, 0x8, {0x000000, 64 * 128 * 1024} }, /* all */
+ { { }, 0x9, {0x000000, 64 * 64 * 1024} }, /* blocks 0-63 */
+ { { }, 0xa, {0x000000, 64 * 96 * 1024} }, /* blocks 0-95 */
+ { { }, 0xb, {0x000000, 64 * 112 * 1024} }, /* blocks 0-111 */
+ { { }, 0xc, {0x000000, 64 * 120 * 1024} }, /* blocks 0-119 */
+ { { }, 0xd, {0x000000, 64 * 124 * 1024} }, /* blocks 0-123 */
+ { { }, 0xe, {0x000000, 64 * 126 * 1024} }, /* blocks 0-125 */
+ { { }, 0xf, {0x000000, 64 * 128 * 1024} }, /* all */
+};
+
+static struct wp_context mx25l6406e_wp = {
+ .sr1 = { .bp0_pos = 2, .bp_bits = 4, .srp_pos = 7 },
+ .descrs = &mx25l6406e_ranges[0],
+};
+
+struct wp_range_descriptor mx25l6495f_tb0_ranges[] = {
+ { { }, 0, {0, 0} }, /* none */
+ { { }, 0x1, {0x7f0000, 64 * 1 * 1024} }, /* block 127 */
+ { { }, 0x2, {0x7e0000, 64 * 2 * 1024} }, /* blocks 126-127 */
+ { { }, 0x3, {0x7c0000, 64 * 4 * 1024} }, /* blocks 124-127 */
+
+ { { }, 0x4, {0x780000, 64 * 8 * 1024} }, /* blocks 120-127 */
+ { { }, 0x5, {0x700000, 64 * 16 * 1024} }, /* blocks 112-127 */
+ { { }, 0x6, {0x600000, 64 * 32 * 1024} }, /* blocks 96-127 */
+ { { }, 0x7, {0x400000, 64 * 64 * 1024} }, /* blocks 64-127 */
+ { { }, 0x8, {0x000000, 64 * 128 * 1024} }, /* all */
+ { { }, 0x9, {0x000000, 64 * 128 * 1024} }, /* all */
+ { { }, 0xa, {0x000000, 64 * 128 * 1024} }, /* all */
+ { { }, 0xb, {0x000000, 64 * 128 * 1024} }, /* all */
+ { { }, 0xc, {0x000000, 64 * 128 * 1024} }, /* all */
+ { { }, 0xd, {0x000000, 64 * 128 * 1024} }, /* all */
+ { { }, 0xe, {0x000000, 64 * 128 * 1024} }, /* all */
+ { { }, 0xf, {0x000000, 64 * 128 * 1024} }, /* all */
+};
+
+struct wp_range_descriptor mx25l6495f_tb1_ranges[] = {
+ { { }, 0, {0, 0} }, /* none */
+ { { }, 0x1, {0x000000, 64 * 1 * 1024} }, /* block 0 */
+ { { }, 0x2, {0x000000, 64 * 2 * 1024} }, /* blocks 0-1 */
+ { { }, 0x3, {0x000000, 64 * 4 * 1024} }, /* blocks 0-3 */
+ { { }, 0x4, {0x000000, 64 * 8 * 1024} }, /* blocks 0-7 */
+ { { }, 0x5, {0x000000, 64 * 16 * 1024} }, /* blocks 0-15 */
+ { { }, 0x6, {0x000000, 64 * 32 * 1024} }, /* blocks 0-31 */
+ { { }, 0x7, {0x000000, 64 * 64 * 1024} }, /* blocks 0-63 */
+ { { }, 0x8, {0x000000, 64 * 128 * 1024} }, /* all */
+ { { }, 0x9, {0x000000, 64 * 128 * 1024} }, /* all */
+ { { }, 0xa, {0x000000, 64 * 128 * 1024} }, /* all */
+ { { }, 0xb, {0x000000, 64 * 128 * 1024} }, /* all */
+ { { }, 0xc, {0x000000, 64 * 128 * 1024} }, /* all */
+ { { }, 0xd, {0x000000, 64 * 128 * 1024} }, /* all */
+ { { }, 0xe, {0x000000, 64 * 128 * 1024} }, /* all */
+ { { }, 0xf, {0x000000, 64 * 128 * 1024} }, /* all */
+};
+
+static struct wp_context mx25l6495f_wp = {
+ .sr1 = { .bp0_pos = 2, .bp_bits = 4, .srp_pos = 7 },
+};
+
+struct wp_range_descriptor mx25l25635f_tb0_ranges[] = {
+ { { }, 0, {0, 0} }, /* none */
+ { { }, 0x1, {0x1ff0000, 64 * 1 * 1024} }, /* block 511 */
+ { { }, 0x2, {0x1fe0000, 64 * 2 * 1024} }, /* blocks 510-511 */
+ { { }, 0x3, {0x1fc0000, 64 * 4 * 1024} }, /* blocks 508-511 */
+ { { }, 0x4, {0x1f80000, 64 * 8 * 1024} }, /* blocks 504-511 */
+ { { }, 0x5, {0x1f00000, 64 * 16 * 1024} }, /* blocks 496-511 */
+ { { }, 0x6, {0x1e00000, 64 * 32 * 1024} }, /* blocks 480-511 */
+ { { }, 0x7, {0x1c00000, 64 * 64 * 1024} }, /* blocks 448-511 */
+ { { }, 0x8, {0x1800000, 64 * 128 * 1024} }, /* blocks 384-511 */
+ { { }, 0x9, {0x1000000, 64 * 256 * 1024} }, /* blocks 256-511 */
+ { { }, 0xa, {0x0000000, 64 * 512 * 1024} }, /* all */
+ { { }, 0xb, {0x0000000, 64 * 512 * 1024} }, /* all */
+ { { }, 0xc, {0x0000000, 64 * 512 * 1024} }, /* all */
+ { { }, 0xd, {0x0000000, 64 * 512 * 1024} }, /* all */
+ { { }, 0xe, {0x0000000, 64 * 512 * 1024} }, /* all */
+ { { }, 0xf, {0x0000000, 64 * 512 * 1024} }, /* all */
+};
+
+struct wp_range_descriptor mx25l25635f_tb1_ranges[] = {
+ { { }, 0, {0, 0} }, /* none */
+ { { }, 0x1, {0x000000, 64 * 1 * 1024} }, /* block 0 */
+ { { }, 0x2, {0x000000, 64 * 2 * 1024} }, /* blocks 0-1 */
+ { { }, 0x3, {0x000000, 64 * 4 * 1024} }, /* blocks 0-3 */
+ { { }, 0x4, {0x000000, 64 * 8 * 1024} }, /* blocks 0-7 */
+ { { }, 0x5, {0x000000, 64 * 16 * 1024} }, /* blocks 0-15 */
+ { { }, 0x6, {0x000000, 64 * 32 * 1024} }, /* blocks 0-31 */
+ { { }, 0x7, {0x000000, 64 * 64 * 1024} }, /* blocks 0-63 */
+ { { }, 0x8, {0x000000, 64 * 128 * 1024} }, /* blocks 0-127 */
+ { { }, 0x9, {0x000000, 64 * 256 * 1024} }, /* blocks 0-255 */
+ { { }, 0xa, {0x000000, 64 * 512 * 1024} }, /* all */
+ { { }, 0xb, {0x000000, 64 * 512 * 1024} }, /* all */
+ { { }, 0xc, {0x000000, 64 * 512 * 1024} }, /* all */
+ { { }, 0xd, {0x000000, 64 * 512 * 1024} }, /* all */
+ { { }, 0xe, {0x000000, 64 * 512 * 1024} }, /* all */
+ { { }, 0xf, {0x000000, 64 * 512 * 1024} }, /* all */
+};
+
+static struct wp_context mx25l25635f_wp = {
+ .sr1 = { .bp0_pos = 2, .bp_bits = 4, .srp_pos = 7 },
+};
+
+#if 0
+struct wp_range_descriptor s25fs128s_ranges[] = {
+ { { .tb = 1 }, 0, {0, 0} }, /* none */
+ { { .tb = 1 }, 0x1, {0x000000, 256 * 1024} }, /* lower 64th */
+ { { .tb = 1 }, 0x2, {0x000000, 512 * 1024} }, /* lower 32nd */
+ { { .tb = 1 }, 0x3, {0x000000, 1024 * 1024} }, /* lower 16th */
+ { { .tb = 1 }, 0x4, {0x000000, 2048 * 1024} }, /* lower 8th */
+ { { .tb = 1 }, 0x5, {0x000000, 4096 * 1024} }, /* lower 4th */
+ { { .tb = 1 }, 0x6, {0x000000, 8192 * 1024} }, /* lower half */
+ { { .tb = 1 }, 0x7, {0x000000, 16384 * 1024} }, /* all */
+
+ { { .tb = 0 }, 0, {0, 0} }, /* none */
+ { { .tb = 0 }, 0x1, {0xfc0000, 256 * 1024} }, /* upper 64th */
+ { { .tb = 0 }, 0x2, {0xf80000, 512 * 1024} }, /* upper 32nd */
+ { { .tb = 0 }, 0x3, {0xf00000, 1024 * 1024} }, /* upper 16th */
+ { { .tb = 0 }, 0x4, {0xe00000, 2048 * 1024} }, /* upper 8th */
+ { { .tb = 0 }, 0x5, {0xc00000, 4096 * 1024} }, /* upper 4th */
+ { { .tb = 0 }, 0x6, {0x800000, 8192 * 1024} }, /* upper half */
+ { { .tb = 0 }, 0x7, {0x000000, 16384 * 1024} }, /* all */
+};
+
+static struct wp_context s25fs128s_wp = {
+ .sr1 = { .bp0_pos = 2, .bp_bits = 3, .srp_pos = 7 },
+ .get_modifier_bits = s25f_get_modifier_bits,
+ .set_modifier_bits = s25f_set_modifier_bits,
+};
+
+
+struct wp_range_descriptor s25fl256s_ranges[] = {
+ { { .tb = 1 }, 0, {0, 0} }, /* none */
+ { { .tb = 1 }, 0x1, {0x000000, 512 * 1024} }, /* lower 64th */
+ { { .tb = 1 }, 0x2, {0x000000, 1024 * 1024} }, /* lower 32nd */
+ { { .tb = 1 }, 0x3, {0x000000, 2048 * 1024} }, /* lower 16th */
+ { { .tb = 1 }, 0x4, {0x000000, 4096 * 1024} }, /* lower 8th */
+ { { .tb = 1 }, 0x5, {0x000000, 8192 * 1024} }, /* lower 4th */
+ { { .tb = 1 }, 0x6, {0x000000, 16384 * 1024} }, /* lower half */
+ { { .tb = 1 }, 0x7, {0x000000, 32768 * 1024} }, /* all */
+
+ { { .tb = 0 }, 0, {0, 0} }, /* none */
+ { { .tb = 0 }, 0x1, {0x1f80000, 512 * 1024} }, /* upper 64th */
+ { { .tb = 0 }, 0x2, {0x1f00000, 1024 * 1024} }, /* upper 32nd */
+ { { .tb = 0 }, 0x3, {0x1e00000, 2048 * 1024} }, /* upper 16th */
+ { { .tb = 0 }, 0x4, {0x1c00000, 4096 * 1024} }, /* upper 8th */
+ { { .tb = 0 }, 0x5, {0x1800000, 8192 * 1024} }, /* upper 4th */
+ { { .tb = 0 }, 0x6, {0x1000000, 16384 * 1024} }, /* upper half */
+ { { .tb = 0 }, 0x7, {0x000000, 32768 * 1024} }, /* all */
+};
+
+static struct wp_context s25fl256s_wp = {
+ .sr1 = { .bp0_pos = 2, .bp_bits = 3, .srp_pos = 7 },
+ .get_modifier_bits = s25f_get_modifier_bits,
+ .set_modifier_bits = s25f_set_modifier_bits,
+};
+#endif
+
+/* Given a flash chip, this function returns its writeprotect info. */
+static int generic_range_table(const struct flashctx *flash,
+ struct wp_context **wp,
+ int *num_entries)
+{
+ *wp = NULL;
+ *num_entries = 0;
+
+ switch (flash->chip->manufacture_id) {
+ case GIGADEVICE_ID:
+ switch(flash->chip->model_id) {
+
+ case GIGADEVICE_GD25LQ32:
+ case GIGADEVICE_GD25Q32: {
+ uint8_t sr1 = w25q_read_status_register_2(flash);
+ *wp = &gd25q32_wp;
+
+ if (!(sr1 & (1 << 6))) { /* CMP == 0 */
+ (*wp)->descrs = &gd25q32_cmp0_ranges[0];
+ *num_entries = ARRAY_SIZE(gd25q32_cmp0_ranges);
+ } else { /* CMP == 1 */
+ (*wp)->descrs = &gd25q32_cmp1_ranges[0];
+ *num_entries = ARRAY_SIZE(gd25q32_cmp1_ranges);
+ }
+
+ break;
+ }
+ case GIGADEVICE_GD25Q128:
+ case GIGADEVICE_GD25LQ128CD: {
+ uint8_t sr1 = w25q_read_status_register_2(flash);
+ *wp = &gd25q128_wp;
+
+ if (!(sr1 & (1 << 6))) { /* CMP == 0 */
+ (*wp)->descrs = &gd25q128_cmp0_ranges[0];
+ *num_entries = ARRAY_SIZE(gd25q128_cmp0_ranges);
+ } else { /* CMP == 1 */
+ (*wp)->descrs = &gd25q128_cmp1_ranges[0];
+ *num_entries = ARRAY_SIZE(gd25q128_cmp1_ranges);
+ }
+
+ break;
+ }
+ default:
+ msg_cerr("%s() %d: GigaDevice flash chip mismatch"
+ " (0x%04x), aborting\n", __func__, __LINE__,
+ flash->chip->model_id);
+ return -1;
+ }
+ break;
+ case MACRONIX_ID:
+ switch (flash->chip->model_id) {
+ case MACRONIX_MX25L6405:
+ /* FIXME: MX25L64* chips have mixed capabilities and
+ share IDs */
+ *wp = &mx25l6406e_wp;
+ *num_entries = ARRAY_SIZE(mx25l6406e_ranges);
+ break;
+ case MACRONIX_MX25L6495F: {
+ uint8_t cr = mx25l_read_config_register(flash);
+
+ *wp = &mx25l6495f_wp;
+ if (!(cr & (1 << 3))) { /* T/B == 0 */
+ (*wp)->descrs = &mx25l6495f_tb0_ranges[0];
+ *num_entries = ARRAY_SIZE(mx25l6495f_tb0_ranges);
+ } else { /* T/B == 1 */
+ (*wp)->descrs = &mx25l6495f_tb1_ranges[0];
+ *num_entries = ARRAY_SIZE(mx25l6495f_tb1_ranges);
+ }
+ break;
+ }
+ case MACRONIX_MX25L25635F: {
+ uint8_t cr = mx25l_read_config_register(flash);
+
+ *wp = &mx25l25635f_wp;
+ if (!(cr & (1 << 3))) { /* T/B == 0 */
+ (*wp)->descrs = &mx25l25635f_tb0_ranges[0];
+ *num_entries = ARRAY_SIZE(mx25l25635f_tb0_ranges);
+ } else { /* T/B == 1 */
+ (*wp)->descrs = &mx25l25635f_tb1_ranges[0];
+ *num_entries = ARRAY_SIZE(mx25l25635f_tb1_ranges);
+ }
+ break;
+ }
+ default:
+ msg_cerr("%s():%d: MXIC flash chip mismatch (0x%04x)"
+ ", aborting\n", __func__, __LINE__,
+ flash->chip->model_id);
+ return -1;
+ }
+ break;
+ //case SPANSION_ID:
+ // switch (flash->chip->model_id) {
+ // case SPANSION_S25FS128S_L:
+ // case SPANSION_S25FS128S_S: {
+ // *wp = &s25fs128s_wp;
+ // (*wp)->descrs = s25fs128s_ranges;
+ // *num_entries = ARRAY_SIZE(s25fs128s_ranges);
+ // break;
+ // }
+ // case SPANSION_S25FL256S_UL:
+ // case SPANSION_S25FL256S_US: {
+ // *wp = &s25fl256s_wp;
+ // (*wp)->descrs = s25fl256s_ranges;
+ // *num_entries = ARRAY_SIZE(s25fl256s_ranges);
+ // break;
+ // }
+ // default:
+ // msg_cerr("%s():%d Spansion flash chip mismatch (0x%04x)"
+ // ", aborting\n", __func__, __LINE__,
+ // flash->chip->model_id);
+ // return -1;
+ // }
+ // break;
+ default:
+ msg_cerr("%s: flash vendor (0x%x) not found, aborting\n",
+ __func__, flash->chip->manufacture_id);
+ return -1;
+ }
+
+ return 0;
+}
+
+static uint8_t generic_get_bp_mask(struct wp_context *wp)
+{
+ return ((1 << (wp->sr1.bp0_pos + wp->sr1.bp_bits)) - 1) ^ \
+ ((1 << wp->sr1.bp0_pos) - 1);
+}
+
+static uint8_t generic_get_status_check_mask(struct wp_context *wp)
+{
+ return generic_get_bp_mask(wp) | 1 << wp->sr1.srp_pos;
+}
+
+/* Given a [start, len], this function finds a block protect bit combination
+ * (if possible) and sets the corresponding bits in "status". Remaining bits
+ * are preserved. */
+static int generic_range_to_status(const struct flashctx *flash,
+ unsigned int start, unsigned int len,
+ uint8_t *status, uint8_t *check_mask)
+{
+ struct wp_context *wp;
+ struct wp_range_descriptor *r;
+ int i, range_found = 0, num_entries;
+ uint8_t bp_mask;
+
+ if (generic_range_table(flash, &wp, &num_entries))
+ return -1;
+
+ bp_mask = generic_get_bp_mask(wp);
+
+ for (i = 0, r = &wp->descrs[0]; i < num_entries; i++, r++) {
+ msg_cspew("comparing range 0x%x 0x%x / 0x%x 0x%x\n",
+ start, len, r->range.start, r->range.len);
+ if ((start == r->range.start) && (len == r->range.len)) {
+ *status &= ~(bp_mask);
+ *status |= r->bp << (wp->sr1.bp0_pos);
+
+ if (wp->set_modifier_bits) {
+ if (wp->set_modifier_bits(flash, &r->m) < 0) {
+ msg_cerr("error setting modifier "
+ "bits for range.\n");
+ return -1;
+ }
+ }
+
+ range_found = 1;
+ break;
+ }
+ }
+
+ if (!range_found) {
+ msg_cerr("%s: matching range not found\n", __func__);
+ return -1;
+ }
+
+ *check_mask = generic_get_status_check_mask(wp);
+ return 0;
+}
+
+static int generic_status_to_range(const struct flashctx *flash,
+ const uint8_t sr1, unsigned int *start, unsigned int *len)
+{
+ struct wp_context *wp;
+ struct wp_range_descriptor *r;
+ int num_entries, i, status_found = 0;
+ uint8_t sr1_bp;
+ struct modifier_bits m;
+
+ if (generic_range_table(flash, &wp, &num_entries))
+ return -1;
+
+ /* modifier bits may be compared more than once, so get them here */
+ if (wp->get_modifier_bits && wp->get_modifier_bits(flash, &m) < 0)
+ return -1;
+
+ sr1_bp = (sr1 >> wp->sr1.bp0_pos) & ((1 << wp->sr1.bp_bits) - 1);
+
+ for (i = 0, r = &wp->descrs[0]; i < num_entries; i++, r++) {
+ if (wp->get_modifier_bits) {
+ if (memcmp(&m, &r->m, sizeof(m)))
+ continue;
+ }
+ msg_cspew("comparing 0x%02x 0x%02x\n", sr1_bp, r->bp);
+ if (sr1_bp == r->bp) {
+ *start = r->range.start;
+ *len = r->range.len;
+ status_found = 1;
+ break;
+ }
+ }
+
+ if (!status_found) {
+ msg_cerr("matching status not found\n");
+ return -1;
+ }
+
+ return 0;
+}
+
+/* Given a [start, len], this function calls generic_range_to_status() to
+ * convert it to flash-chip-specific range bits, then sets into status register.
+ */
+static int generic_set_range(const struct flashctx *flash,
+ unsigned int start, unsigned int len)
+{
+ uint8_t status, expected, check_mask;
+
+ status = do_read_status(flash);
+ msg_cdbg("%s: old status: 0x%02x\n", __func__, status);
+
+ expected = status; /* preserve non-bp bits */
+ if (generic_range_to_status(flash, start, len, &expected, &check_mask))
+ return -1;
+
+ do_write_status(flash, expected);
+
+ status = do_read_status(flash);
+ msg_cdbg("%s: new status: 0x%02x\n", __func__, status);
+ if ((status & check_mask) != (expected & check_mask)) {
+ msg_cerr("expected=0x%02x, but actual=0x%02x. check mask=0x%02x\n",
+ expected, status, check_mask);
+ return 1;
+ }
+ return 0;
+}
+
+/* Set/clear the status regsiter write protect bit in SR1. */
+static int generic_set_srp0(const struct flashctx *flash, int enable)
+{
+ uint8_t status, expected, check_mask;
+ struct wp_context *wp;
+ int num_entries;
+
+ if (generic_range_table(flash, &wp, &num_entries))
+ return -1;
+
+ expected = do_read_status(flash);
+ msg_cdbg("%s: old status: 0x%02x\n", __func__, expected);
+
+ if (enable)
+ expected |= 1 << wp->sr1.srp_pos;
+ else
+ expected &= ~(1 << wp->sr1.srp_pos);
+
+ do_write_status(flash, expected);
+
+ status = do_read_status(flash);
+ msg_cdbg("%s: new status: 0x%02x\n", __func__, status);
+
+ check_mask = generic_get_status_check_mask(wp);
+ msg_cdbg("%s: check mask: 0x%02x\n", __func__, check_mask);
+ if ((status & check_mask) != (expected & check_mask)) {
+ msg_cerr("expected=0x%02x, but actual=0x%02x. check mask=0x%02x\n",
+ expected, status, check_mask);
+ return -1;
+ }
+
+ return 0;
+}
+
+static int generic_enable_writeprotect(const struct flashctx *flash,
+ enum wp_mode wp_mode)
+{
+ int ret;
+
+ if (wp_mode != WP_MODE_HARDWARE) {
+ msg_cerr("%s(): unsupported write-protect mode\n", __func__);
+ return 1;
+ }
+
+ ret = generic_set_srp0(flash, 1);
+ if (ret)
+ msg_cerr("%s(): error=%d.\n", __func__, ret);
+
+ return ret;
+}
+
+static int generic_disable_writeprotect(const struct flashctx *flash)
+{
+ int ret;
+
+ ret = generic_set_srp0(flash, 0);
+ if (ret)
+ msg_cerr("%s(): error=%d.\n", __func__, ret);
+
+ return ret;
+}
+
+static int generic_list_ranges(const struct flashctx *flash)
+{
+ struct wp_context *wp;
+ struct wp_range_descriptor *r;
+ int i, num_entries;
+
+ if (generic_range_table(flash, &wp, &num_entries))
+ return -1;
+
+ r = &wp->descrs[0];
+ for (i = 0; i < num_entries; i++) {
+ msg_cinfo("start: 0x%06x, length: 0x%06x\n",
+ r->range.start, r->range.len);
+ r++;
+ }
+
+ return 0;
+}
+
+static int wp_context_status(const struct flashctx *flash)
+{
+ uint8_t sr1;
+ unsigned int start, len;
+ int ret = 0;
+ struct wp_context *wp;
+ int num_entries, wp_en;
+
+ if (generic_range_table(flash, &wp, &num_entries))
+ return -1;
+
+ sr1 = do_read_status(flash);
+ wp_en = (sr1 >> wp->sr1.srp_pos) & 1;
+
+ msg_cinfo("WP: status: 0x%04x\n", sr1);
+ msg_cinfo("WP: status.srp0: %x\n", wp_en);
+ /* FIXME: SRP1 is not really generic, but we probably should print
+ * it anyway to have consistent output. #legacycruft */
+ msg_cinfo("WP: status.srp1: %x\n", 0);
+ msg_cinfo("WP: write protect is %s.\n",
+ wp_en ? "enabled" : "disabled");
+
+ msg_cinfo("WP: write protect range: ");
+ if (generic_status_to_range(flash, sr1, &start, &len)) {
+ msg_cinfo("(cannot resolve the range)\n");
+ ret = -1;
+ } else {
+ msg_cinfo("start=0x%08x, len=0x%08x\n", start, len);
+ }
+
+ return ret;
+}
+
+struct wp wp_generic = {
+ .list_ranges = generic_list_ranges,
+ .set_range = generic_set_range,
+ .enable = generic_enable_writeprotect,
+ .disable = generic_disable_writeprotect,
+ .wp_status = wp_context_status,
+};
diff --git a/writeprotect.h b/writeprotect.h
new file mode 100644
index 0000000..d39b993
--- /dev/null
+++ b/writeprotect.h
@@ -0,0 +1,57 @@
+/*
+ * This file is part of the flashrom project.
+ *
+ * Copyright (C) 2010 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __WRITEPROTECT_H__
+#define __WRITEPROTECT_H__ 1
+
+enum wp_mode {
+ WP_MODE_UNKNOWN = -1,
+ WP_MODE_HARDWARE, /* hardware WP pin determines status */
+ WP_MODE_POWER_CYCLE, /* WP active until power off/on cycle */
+ WP_MODE_PERMANENT, /* status register permanently locked,
+ WP permanently enabled */
+};
+
+struct wp {
+ int (*list_ranges)(const struct flashctx *flash);
+ int (*set_range)(const struct flashctx *flash,
+ unsigned int start, unsigned int len);
+ int (*enable)(const struct flashctx *flash, enum wp_mode mode);
+ int (*disable)(const struct flashctx *flash);
+ int (*wp_status)(const struct flashctx *flash);
+};
+
+/* winbond w25-series */
+extern struct wp wp_w25; /* older winbond chips (w25p, w25x, etc) */
+extern struct wp wp_w25q;
+extern struct wp wp_w25q_large; /* large winbond chips (>= 32MB) */
+
+extern struct wp wp_generic;
+extern struct wp wp_wpce775x;
+
+enum wp_mode get_wp_mode(const char *mode_str);
+
+/*
+ * Generic write-protect stuff
+ */
+
+struct modifier_bits {
+ int sec; /* if 1, bp bits describe sectors */
+ int tb; /* value of top/bottom select bit */
+};
+
+#endif /* !__WRITEPROTECT_H__ */
--
To view, visit https://review.coreboot.org/c/flashrom/+/40325
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Gerrit-Project: flashrom
Gerrit-Branch: master
Gerrit-Change-Id: Id93b5a1cb2da476fa8a7dde41d7b963024117474
Gerrit-Change-Number: 40325
Gerrit-PatchSet: 1
Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org>
Gerrit-MessageType: newchange
2 months
- 6
- 24
Change in flashrom[master]: flashchips: Added missing voltages
by Name of user not set (Code Review)
roman.stingler(a)gmail.com has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/40432 )
Change subject: flashchips: Added missing voltages
......................................................................
flashchips: Added missing voltages
Signed-off-by: Roman Stingler <roman.stingler(a)gmail.com>
Change-Id: I0825ab11e53c0b018b49173907e2b274a4cf1fab
---
M flashchips.c
1 file changed, 9 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/32/40432/1
diff --git a/flashchips.c b/flashchips.c
index b4006df..f2d9fc1 100644
--- a/flashchips.c
+++ b/flashchips.c
@@ -7650,6 +7650,7 @@
},
.write = write_82802ab,
.read = read_memmapped,
+ .voltage = {4500, 5500},
},
{
@@ -7677,6 +7678,7 @@
},
.write = write_82802ab,
.read = read_memmapped,
+ .voltage = {4500, 5500},
},
{
@@ -7704,6 +7706,7 @@
},
.write = write_82802ab,
.read = read_memmapped,
+ .voltage = {4500, 5500},
},
{
@@ -7727,6 +7730,7 @@
.unlock = unlock_28f004s5,
.write = write_82802ab,
.read = read_memmapped,
+ .voltage = {2700, 3600},
},
{
@@ -7755,6 +7759,7 @@
},
.write = write_82802ab,
.read = read_memmapped,
+ .voltage = {4500, 5500},
},
{
@@ -7783,6 +7788,7 @@
},
.write = write_82802ab,
.read = read_memmapped,
+ .voltage = {4500, 5500},
},
{
@@ -9972,6 +9978,7 @@
.unlock = spi_disable_blockprotect_bp3_srwd,
.write = spi_chip_write_256,
.read = spi_chip_read,
+ .voltage = {2700, 3600},
},
{
@@ -17550,6 +17557,7 @@
},
.write = write_jedec,
.read = read_memmapped,
+ .voltage = {4500, 5500},
},
{
@@ -17573,6 +17581,7 @@
},
.write = write_jedec,
.read = read_memmapped,
+ .voltage = {4500, 5500},
},
{
--
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Gerrit-Project: flashrom
Gerrit-Branch: master
Gerrit-Change-Id: I0825ab11e53c0b018b49173907e2b274a4cf1fab
Gerrit-Change-Number: 40432
Gerrit-PatchSet: 1
Gerrit-Owner: roman.stingler(a)gmail.com
Gerrit-MessageType: newchange
2 months
- 3
- 5
Change in ...flashrom[master]: dediprog: Use 4BA page program without 0x12
by David Hendricks (Code Review)
David Hendricks has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/30521
Change subject: dediprog: Use 4BA page program without 0x12
......................................................................
dediprog: Use 4BA page program without 0x12
It's not clear exactly what the difference is between
WRITE_MODE_4B_ADDR_256B_PAGE_PGM with and without _0x12 from the SF600
command spec, but the former seems to work more reliably.
Tested using an SF600 (FW v7.2.21), IS25LP256D, W25Q256JV, and
MX25L25735.
Change-Id: I3cb37ec8838f5bb02948ed52b4a2906fa033cf83
Signed-off-by: David Hendricks <david.hendricks(a)gmail.com>
---
M dediprog.c
1 file changed, 2 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/21/30521/1
diff --git a/dediprog.c b/dediprog.c
index 2a190d2..303f1d5 100644
--- a/dediprog.c
+++ b/dediprog.c
@@ -398,7 +398,8 @@
}
} else if (dedi_spi_cmd == WRITE_MODE_PAGE_PGM) {
if (flash->chip->feature_bits & FEATURE_4BA_WRITE) {
- data_packet[3] = WRITE_MODE_4B_ADDR_256B_PAGE_PGM_0x12;
+// data_packet[3] = WRITE_MODE_4B_ADDR_256B_PAGE_PGM_0x12;
+ data_packet[3] = WRITE_MODE_4B_ADDR_256B_PAGE_PGM;
data_packet[4] = JEDEC_BYTE_PROGRAM_4BA;
use_4ba = true;
} else if (flash->in_4ba_mode) {
--
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Gerrit-Project: flashrom
Gerrit-Branch: master
Gerrit-Change-Id: I3cb37ec8838f5bb02948ed52b4a2906fa033cf83
Gerrit-Change-Number: 30521
Gerrit-PatchSet: 1
Gerrit-Owner: David Hendricks <david.hendricks(a)gmail.com>
Gerrit-MessageType: newchange
3 months
- 1
- 1
Change in flashrom[master]: udelay.c: Enable providing delay calibration value through CLI
by Hrvoje Čavrak (Code Review)
Hrvoje Čavrak has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/39841 )
Change subject: udelay.c: Enable providing delay calibration value through CLI
......................................................................
udelay.c: Enable providing delay calibration value through CLI
This commit implements --delay option to retrieve and provide the calibration
loop delay through the command line. The delay calibration procedure can take
up to few seconds, which adds up when executed a number of times consecutively.
Therefore, this provides a means to execute it only once, and then re-use the
calibrated value on subsequent runs. Also, it implements a sanity check,
expecting the value to land within 10% of the theoretical delay expectance,
otherwise it ignores the provided value and runs the calibration procedure
instead.
modified: cli_classic.c
modified: flashrom.8.tmpl
modified: programmer.h
modified: udelay.c
Change-Id: Iea2a7f62300663bc0a32ed4abced57c8c55c90c8
Signed-off-by: Hrvoje Cavrak <hrvoje(a)hrvoje.org>
---
M cli_classic.c
M flashrom.8.tmpl
M programmer.h
M udelay.c
4 files changed, 51 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/41/39841/1
diff --git a/cli_classic.c b/cli_classic.c
index 73cc417..f0842d4 100644
--- a/cli_classic.c
+++ b/cli_classic.c
@@ -63,6 +63,8 @@
" -o | --output <logfile> log output to <logfile>\n"
" --flash-contents <ref-file> assume flash contents to be <ref-file>\n"
" -L | --list-supported print supported devices\n"
+ " -d | --loop-delay <value> set loop delay calibration manually\n"
+ " --loop-delay get show loop delay calibration\n"
#if CONFIG_PRINT_WIKI == 1
" -z | --list-supported-wiki print supported devices in wiki syntax\n"
#endif
@@ -118,6 +120,7 @@
int flash_name = 0, flash_size = 0;
int read_it = 0, write_it = 0, erase_it = 0, verify_it = 0;
int dont_verify_it = 0, dont_verify_all = 0, list_supported = 0, operation_specified = 0;
+ unsigned long provided_delay = 0;
struct flashrom_layout *layout = NULL;
enum programmer prog = PROGRAMMER_INVALID;
enum {
@@ -130,7 +133,7 @@
};
int ret = 0;
- static const char optstring[] = "r:Rw:v:nNVEfc:l:i:p:Lzho:";
+ static const char optstring[] = "r:Rw:v:nNVEfc:l:i:p:Lzho:d:";
static const struct option long_options[] = {
{"read", 1, NULL, 'r'},
{"write", 1, NULL, 'w'},
@@ -156,6 +159,7 @@
{"help", 0, NULL, 'h'},
{"version", 0, NULL, 'R'},
{"output", 1, NULL, 'o'},
+ {"delay", 1, NULL, 'd'},
{NULL, 0, NULL, 0},
};
@@ -362,6 +366,14 @@
}
#endif /* STANDALONE */
break;
+ case 'd':
+ provided_delay = strtoul(strdup(optarg), NULL, 0);
+ if (!provided_delay) {
+ /* Make it easy for scripts to parse this by omitting anything else */
+ msg_pinfo("%lu\n", get_calibration_value());
+ exit(0);
+ }
+ break;
default:
cli_classic_abort_usage(NULL);
break;
@@ -454,7 +466,10 @@
}
/* FIXME: Delay calibration should happen in programmer code. */
- myusec_calibrate_delay();
+ if (provided_delay)
+ set_external_calibration(provided_delay);
+ else
+ myusec_calibrate_delay();
if (programmer_init(prog, pparam)) {
msg_perr("Error: Programmer initialization failed.\n");
diff --git a/flashrom.8.tmpl b/flashrom.8.tmpl
index fde98c0..c14f2de 100644
--- a/flashrom.8.tmpl
+++ b/flashrom.8.tmpl
@@ -50,7 +50,7 @@
[\fB\-E\fR|\fB\-r\fR <file>|\fB\-w\fR <file>|\fB\-v\fR <file>]
[(\fB\-l\fR <file>|\fB\-\-ifd|\fB \-\-fmap\fR|\fB\-\-fmap-file\fR <file>) [\fB\-i\fR <image>]]
[\fB\-n\fR] [\fB\-N\fR] [\fB\-f\fR])]
- [\fB\-V\fR[\fBV\fR[\fBV\fR]]] [\fB-o\fR <logfile>]
+ [\fB\-V\fR[\fBV\fR[\fBV\fR]]] [\fB-o\fR <logfile>] [\fB-d\fR get | <value>]
.SH DESCRIPTION
.B flashrom
is a utility for detecting, reading, writing, verifying and erasing flash
@@ -364,6 +364,18 @@
.TP
.B "\-R, \-\-version"
Show version information and exit.
+.TP
+.B "\-d, \-\-loop\-delay"
+Retrieve the loop calibration delay value or provide one externally. Calibrate
+delay procedure can take a few seconds and for repeated execution on a large
+number of hosts it can provide a significant overhead. Therefore, this argument
+makes it possible to provide the calibration delay through the command line
+option.
+
+To retrieve the value, run
+.BR "flashrom \-\-loop\-delay get " "and to provide it during programming, add "
+.BR "\-\-loop\-delay <value> " "to your command."
+
.SH PROGRAMMER-SPECIFIC INFORMATION
Some programmer drivers accept further parameters to set programmer-specific
parameters. These parameters are separated from the programmer name by a
diff --git a/programmer.h b/programmer.h
index 08500c6..a659a18 100644
--- a/programmer.h
+++ b/programmer.h
@@ -277,6 +277,8 @@
void myusec_calibrate_delay(void);
void internal_sleep(unsigned int usecs);
void internal_delay(unsigned int usecs);
+unsigned long get_calibration_value(void);
+void set_external_calibration(unsigned long external_micro);
#if CONFIG_INTERNAL == 1
/* board_enable.c */
diff --git a/udelay.c b/udelay.c
index 6c0efc4..90c4c9e 100644
--- a/udelay.c
+++ b/udelay.c
@@ -221,6 +221,25 @@
msg_pinfo("OK.\n");
}
+void set_external_calibration(unsigned long external_micro)
+{
+ micro = external_micro;
+ unsigned long elapsed = measure_delay(100000);
+ /* Do a sanity check if the provided parameter makes loops fall within 10% of
+ * the desired value. Otherwise, ignore provided value and recalibrate.
+ */
+ if (elapsed > 90000 && elapsed < 110000)
+ msg_pinfo("Provided delay is acceptable!\n");
+ else
+ myusec_calibrate_delay();
+}
+
+unsigned long get_calibration_value(void)
+{
+ myusec_calibrate_delay();
+ return micro;
+}
+
/* Not very precise sleep. */
void internal_sleep(unsigned int usecs)
{
--
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Gerrit-Project: flashrom
Gerrit-Branch: master
Gerrit-Change-Id: Iea2a7f62300663bc0a32ed4abced57c8c55c90c8
Gerrit-Change-Number: 39841
Gerrit-PatchSet: 1
Gerrit-Owner: Hrvoje Čavrak <github(a)hrvoje.org>
Gerrit-MessageType: newchange
3 months, 1 week
- 3
- 7
Change in flashrom[master]: dediprog: Fix SF600 4BA mode
by Patrick Rudolph (Code Review)
Hello Patrick Rudolph,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/flashrom/+/34629
to review the following change.
Change subject: dediprog: Fix SF600 4BA mode
......................................................................
dediprog: Fix SF600 4BA mode
Flash chips greater than 16MiB require 4BA mode support.
Current master doesn't support such mode as the SF600 uses
PROTOCOL_V3.
Fix protocol version check to support 4BA on PROTOCOL_V3, too.
Tested on SF600 V:7.2.45
Able to read and write "IS25WP256" (32768 kB, SPI).
Change-Id: I2d3089693fbd2f8f7717a8f71be242be131ce707
Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
---
M dediprog.c
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/29/34629/1
diff --git a/dediprog.c b/dediprog.c
index 3566109..add478d 100644
--- a/dediprog.c
+++ b/dediprog.c
@@ -1160,7 +1160,7 @@
if (dediprog_devicetype == DEV_SF100 && protocol() == PROTOCOL_V1)
spi_master_dediprog.features &= ~SPI_MASTER_NO_4BA_MODES;
- if (protocol() == PROTOCOL_V2)
+ if (protocol() >= PROTOCOL_V2)
spi_master_dediprog.features |= SPI_MASTER_4BA;
if (register_spi_master(&spi_master_dediprog) || dediprog_set_leds(LED_NONE))
--
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Gerrit-Project: flashrom
Gerrit-Branch: master
Gerrit-Change-Id: I2d3089693fbd2f8f7717a8f71be242be131ce707
Gerrit-Change-Number: 34629
Gerrit-PatchSet: 1
Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com>
Gerrit-MessageType: newchange
3 months, 2 weeks
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