David Hendricks has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/36986 )
Change subject: mysteries_intel: Add a section about SMM_BWP
mysteries_intel: Add a section about SMM_BWP
Something to point users to when SMM_BWP might be causing problems.
Signed-off-by: David Hendricks <david.hendricks(a)gmail.com>
1 file changed, 19 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/86/36986/1
diff --git a/Documentation/mysteries_intel.txt b/Documentation/mysteries_intel.txt
index 10cb37d..d6ceb6a 100644
@@ -5,6 +5,25 @@
A0h), so we have no clue if or where it is on ICH8. Out current policy is to
not touch it at all and assume/hope it is 0.
+= SMM BIOS write protection =
+Sometimes a hardware vendor will enable "SMM BIOS Write Protect" (SMM_BWP).
+The bits that control this are in the BIOS_CNTL register in the LPC interface.
+When enabled, the SPI flash can only be written when the system is operating in
+in System Management Mode (SMM). In other words, only code that was installed by
+the BIOS can write to the flash chip. Reads are still possible with code that
+runs outside of SMM, such as flashrom.
+Flashrom will attempt to detect this and print a message such as the following:
+"Warning: BIOS region SMM protection is enabled!"
+Many vendor-supplied firmware update utilities do not actually write to the ROM;
+instead they transfer data to/from memory which is read/written by a routine
+running in SMM and is responsible for writing to the firmware ROM. This causes
+severe system performance degradataion since all processors must be in SMM
+context (ring -2) instead of OS context (ring 0) while the firmware ROM is being
= Accesses beyond region bounds in descriptor mode =
Intel's flash image tool will always expand the last region so that it covers
the whole flash chip, but some boards ship with a different configuration.
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Gerrit-Owner: David Hendricks <david.hendricks(a)gmail.com>