Change in ...flashrom[master]: Add "--dangerous-bruteforce" mode for the unreliable ISP environments
by mikeb mikeb (Code Review)
Hello Mike Banon,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/flashrom/+/31830
to review the following change.
Change subject: Add "--dangerous-bruteforce" mode for the unreliable ISP environments
......................................................................
Add "--dangerous-bruteforce" mode for the unreliable ISP environments
Some in-system-programming environments are very unreliable, e.g.
when you connect a SOIC8 test clip to the flash chip of WR841ND v9
wireless router: because the low power SOC of this router becomes
powered and is constantly trying to boot, the router's flash chip
is correctly detected only 30% of times, and when it is detected
just 30% of the read operations are successful - the rest result in
zeroes or garbage data being read from a flash chip.
While in this new "--dangerous-bruteforce" mode, flashrom will be
constantly probing for a flash chip until it is correctly detected -
and then, depending on the operation selected by a user, at the
moments of chip availability it will be reading or writing by the
small chunks of 256 bytes maximum size, verifying each small chunk
and retrying the operation until the success or timeout (~ 60 sec).
Constant probing between the small chunk operations is also being
done - to avoid a possible situation where we have got two identical
blocks of zeroes while reading a chunk and erroneously accepted it.
Currently this mode is active only for those SPI25 chips which are
".write = spi_chip_write_256" and ".read = spi_chip_read", but later
could be expanded to more functions to become useful for more chips.
NOTE: this mode is experimental! Also, some targets like WR841ND v9
could block the ISP chip access completely if there is no bootable
firmware inside (e.g. after you've tried to erase the chip contents).
In such a situation it could be hard to recover the firmware without
desoldering a flash chip and flashing it separately. Please do not
erase or write to a flash chip using this mode if you are not sure.
Signed-off-by: Mike Banon <mikebdp2(a)gmail.com>
Change-Id: If47476793721a0061fd65bc6d1f98d48b03dc6c1
---
M cli_classic.c
M flash.h
M flashrom.c
M libflashrom.c
M libflashrom.h
M spi25.c
6 files changed, 148 insertions(+), 15 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/30/31830/1
diff --git a/cli_classic.c b/cli_classic.c
index ced08c6..454df2b 100644
--- a/cli_classic.c
+++ b/cli_classic.c
@@ -51,6 +51,7 @@
" -V | --verbose more verbose output\n"
" -c | --chip <chipname> probe only for specified flash chip\n"
" -f | --force force specific operations (see man page)\n"
+ " --dangerous-bruteforce verify each small chunk and probe constantly\n"
" -n | --noverify don't auto-verify\n"
" -N | --noverify-all verify included regions only (cf. -i)\n"
" -l | --layout <layoutfile> read ROM layout from <layoutfile>\n"
@@ -104,7 +105,7 @@
#if CONFIG_PRINT_WIKI == 1
int list_supported_wiki = 0;
#endif
- int read_it = 0, write_it = 0, erase_it = 0, verify_it = 0;
+ int read_it = 0, write_it = 0, erase_it = 0, verify_it = 0, bruteforce = 0, timeout = 30000;
int dont_verify_it = 0, dont_verify_all = 0, list_supported = 0, operation_specified = 0;
struct flashrom_layout *layout = NULL;
enum programmer prog = PROGRAMMER_INVALID;
@@ -113,6 +114,7 @@
OPTION_FMAP,
OPTION_FMAP_FILE,
OPTION_FLASH_CONTENTS,
+ OPTION_BRUTEFORCE,
};
int ret = 0;
@@ -127,6 +129,7 @@
{"chip", 1, NULL, 'c'},
{"verbose", 0, NULL, 'V'},
{"force", 0, NULL, 'f'},
+ {"dangerous-bruteforce", 0, NULL, OPTION_BRUTEFORCE},
{"layout", 1, NULL, 'l'},
{"ifd", 0, NULL, OPTION_IFD},
{"fmap", 0, NULL, OPTION_FMAP},
@@ -228,6 +231,9 @@
case 'f':
force = 1;
break;
+ case OPTION_BRUTEFORCE:
+ bruteforce = 1;
+ break;
case 'l':
if (layoutfile) {
fprintf(stderr, "Error: --layout specified "
@@ -503,16 +509,27 @@
msg_pdbg("The following protocols are supported: %s.\n", tempstr);
free(tempstr);
- for (j = 0; j < registered_master_count; j++) {
- startchip = 0;
- while (chipcount < ARRAY_SIZE(flashes)) {
- startchip = probe_flash(®istered_masters[j], startchip, &flashes[chipcount], 0);
- if (startchip == -1)
- break;
- chipcount++;
- startchip++;
+ do {
+ chipcount = 0;
+ for (j = 0; j < registered_master_count; j++) {
+ startchip = 0;
+ while (chipcount < ARRAY_SIZE(flashes)) {
+ startchip = probe_flash(®istered_masters[j], startchip, &flashes[chipcount], 0);
+ if (startchip == -1)
+ break;
+ chipcount++;
+ startchip++;
+ }
}
- }
+ timeout--;
+ if (!timeout) {
+ msg_cerr("Error: Timed out trying to detect a chip.\n");
+ ret = 1;
+ goto out_shutdown;
+ }
+ } while (bruteforce && ( !chipcount || // wait for the correct chip detection
+ ((flashes[0].chip->manufacture_id == GENERIC_MANUF_ID) ||
+ (flashes[0].chip->model_id == GENERIC_DEVICE_ID)) ) );
if (chipcount > 1) {
msg_cinfo("Multiple flash chip definitions match the detected chip(s): \"%s\"",
@@ -650,6 +667,7 @@
#if CONFIG_INTERNAL == 1
flashrom_flag_set(fill_flash, FLASHROM_FLAG_FORCE_BOARDMISMATCH, !!force_boardmismatch);
#endif
+ flashrom_flag_set(fill_flash, FLASHROM_FLAG_BRUTEFORCE, !!bruteforce);
flashrom_flag_set(fill_flash, FLASHROM_FLAG_VERIFY_AFTER_WRITE, !dont_verify_it);
flashrom_flag_set(fill_flash, FLASHROM_FLAG_VERIFY_WHOLE_CHIP, !dont_verify_all);
diff --git a/flash.h b/flash.h
index 911214c..6ba116e 100644
--- a/flash.h
+++ b/flash.h
@@ -256,6 +256,7 @@
struct {
bool force;
bool force_boardmismatch;
+ bool bruteforce;
bool verify_after_write;
bool verify_whole_chip;
} flags;
diff --git a/flashrom.c b/flashrom.c
index e82c32e..8f2c859 100644
--- a/flashrom.c
+++ b/flashrom.c
@@ -1641,6 +1641,8 @@
size_t i, j;
bool first = true;
struct block_eraser *const eraser = &flashctx->chip->block_erasers[erasefunction];
+ unsigned int bruteforce = flashrom_flag_get(flashctx, FLASHROM_FLAG_BRUTEFORCE);
+ int timeout;
info->erase_start = 0;
for (i = 0; i < NUM_ERASEREGIONS; ++i) {
@@ -1662,9 +1664,34 @@
msg_cdbg(", ");
msg_cdbg("0x%06x-0x%06x:", info->erase_start, info->erase_end);
- ret = per_blockfn(flashctx, info, eraser->block_erase);
- if (ret)
- return ret;
+ if (!bruteforce) {
+ ret = per_blockfn(flashctx, info, eraser->block_erase);
+ if (ret)
+ return ret;
+ } else {
+ timeout = 30000;
+ while(1) {
+ timeout--;
+ if (!timeout) {
+ msg_cerr("%s timeout during command execution\n", __func__);
+ return 2;
+ }
+
+ /* First probe. */
+ if (flashctx->chip->probe(flashctx) != 1)
+ continue;
+
+ ret = per_blockfn(flashctx, info, eraser->block_erase);
+ if (ret)
+ continue;
+
+ /* Second probe. */
+ if (flashctx->chip->probe(flashctx) != 1)
+ continue;
+
+ break;
+ }
+ }
}
if (info->region_end < info->erase_start)
break;
diff --git a/libflashrom.c b/libflashrom.c
index f90a22c..6dd0167 100644
--- a/libflashrom.c
+++ b/libflashrom.c
@@ -250,6 +250,7 @@
switch (flag) {
case FLASHROM_FLAG_FORCE: flashctx->flags.force = value; break;
case FLASHROM_FLAG_FORCE_BOARDMISMATCH: flashctx->flags.force_boardmismatch = value; break;
+ case FLASHROM_FLAG_BRUTEFORCE: flashctx->flags.bruteforce = value; break;
case FLASHROM_FLAG_VERIFY_AFTER_WRITE: flashctx->flags.verify_after_write = value; break;
case FLASHROM_FLAG_VERIFY_WHOLE_CHIP: flashctx->flags.verify_whole_chip = value; break;
}
@@ -267,6 +268,7 @@
switch (flag) {
case FLASHROM_FLAG_FORCE: return flashctx->flags.force;
case FLASHROM_FLAG_FORCE_BOARDMISMATCH: return flashctx->flags.force_boardmismatch;
+ case FLASHROM_FLAG_BRUTEFORCE: return flashctx->flags.bruteforce;
case FLASHROM_FLAG_VERIFY_AFTER_WRITE: return flashctx->flags.verify_after_write;
case FLASHROM_FLAG_VERIFY_WHOLE_CHIP: return flashctx->flags.verify_whole_chip;
default: return false;
diff --git a/libflashrom.h b/libflashrom.h
index 38c95d2..0f2ead8 100644
--- a/libflashrom.h
+++ b/libflashrom.h
@@ -51,6 +51,7 @@
enum flashrom_flag {
FLASHROM_FLAG_FORCE,
FLASHROM_FLAG_FORCE_BOARDMISMATCH,
+ FLASHROM_FLAG_BRUTEFORCE,
FLASHROM_FLAG_VERIFY_AFTER_WRITE,
FLASHROM_FLAG_VERIFY_WHOLE_CHIP,
};
diff --git a/spi25.c b/spi25.c
index 8b6c462..832c836 100644
--- a/spi25.c
+++ b/spi25.c
@@ -21,6 +21,7 @@
#include <stddef.h>
#include <string.h>
#include <stdbool.h>
+#include <stdlib.h>
#include "flash.h"
#include "flashchips.h"
#include "chipdrivers.h"
@@ -655,6 +656,48 @@
return spi_send_command(flash, 1 + addr_len, len, cmd, bytes);
}
+static int spi_rw_bruteforce(struct flashctx *flash, uint8_t *buf1, uint8_t *buf2,
+ unsigned int startrw_here, unsigned int torw_len, bool rw_flag) {
+ int rc = 0;
+ int timeout = 30000;
+ while (1) {
+ timeout--;
+ if (!timeout) {
+ msg_cerr("%s timeout during command execution\n", __func__);
+ return -1;
+ }
+
+ /* First probe. */
+ if (flash->chip->probe(flash) != 1)
+ continue;
+
+ /* First operation. */
+ if (rw_flag == 0)
+ rc = spi_nbyte_read(flash, startrw_here, buf1, torw_len);
+ else
+ rc = spi_nbyte_program(flash, startrw_here, buf1, torw_len);
+
+ if (rc != 0)
+ break;
+
+ /* Second probe. */
+ if (flash->chip->probe(flash) != 1)
+ continue;
+
+ /* Second operation. */
+ rc = spi_nbyte_read(flash, startrw_here, buf2, torw_len);
+ if (rc != 0)
+ break;
+
+ /* Compare two buffers. */
+ if (memcmp(buf1, buf2, torw_len))
+ continue;
+
+ break;
+ }
+ return rc;
+}
+
/*
* Read a part of the flash chip.
* FIXME: Use the chunk code from Michael Karcher instead.
@@ -668,6 +711,19 @@
/* Limit for multi-die 4-byte-addressing chips. */
unsigned int area_size = min(flash->chip->total_size * 1024, 16 * 1024 * 1024);
+ unsigned int bruteforce = flashrom_flag_get(flash, FLASHROM_FLAG_BRUTEFORCE);
+ uint8_t *const buf1 = bruteforce ? malloc(chunksize) : NULL;
+ uint8_t *const buf2 = bruteforce ? malloc(chunksize) : NULL;
+
+ if (bruteforce) {
+ if (!buf1 || !buf2) {
+ msg_gerr("Out of memory!\n");
+ goto _free_ret;
+ }
+ msg_cdbg("spi_read_chunked: chunksize %i ---> %i\n", chunksize, min(chunksize, 256));
+ chunksize = min(chunksize, 256);
+ }
+
/* Warning: This loop has a very unusual condition and body.
* The loop needs to go through each area with at least one affected
* byte. The lowest area number is (start / area_size) since that
@@ -685,7 +741,11 @@
lenhere = min(start + len, (i + 1) * area_size) - starthere;
for (j = 0; j < lenhere; j += chunksize) {
toread = min(chunksize, lenhere - j);
- rc = spi_nbyte_read(flash, starthere + j, buf + starthere - start + j, toread);
+ if (bruteforce) {
+ rc = spi_rw_bruteforce(flash, buf1, buf2, starthere + j, toread, 0 /* read */);
+ memcpy(buf + starthere - start + j, buf1, toread);
+ } else
+ rc = spi_nbyte_read(flash, starthere + j, buf + starthere - start + j, toread);
if (rc)
break;
}
@@ -693,6 +753,9 @@
break;
}
+_free_ret:
+ free(buf1);
+ free(buf2);
return rc;
}
@@ -712,6 +775,19 @@
*/
unsigned int page_size = flash->chip->page_size;
+ unsigned int bruteforce = flashrom_flag_get(flash, FLASHROM_FLAG_BRUTEFORCE);
+ uint8_t *const buf1 = bruteforce ? malloc(chunksize) : NULL;
+ uint8_t *const buf2 = bruteforce ? malloc(chunksize) : NULL;
+
+ if (bruteforce) {
+ if (!buf1 || !buf2) {
+ msg_gerr("Out of memory!\n");
+ goto _free_ret;
+ }
+ msg_cdbg("spi_write_chunked: chunksize %i ---> %i\n", chunksize, min(chunksize, 256));
+ chunksize = min(chunksize, 256);
+ }
+
/* Warning: This loop has a very unusual condition and body.
* The loop needs to go through each page with at least one affected
* byte. The lowest page number is (start / page_size) since that
@@ -731,12 +807,20 @@
int rc;
towrite = min(chunksize, lenhere - j);
- rc = spi_nbyte_program(flash, starthere + j, buf + starthere - start + j, towrite);
+ if (bruteforce) {
+ memcpy(buf1, buf + starthere - start + j, towrite);
+ rc = spi_rw_bruteforce(flash, buf1, buf2, starthere + j, towrite, 1 /* write */);
+ } else
+ rc = spi_nbyte_program(flash, starthere + j, buf + starthere - start + j, towrite);
+
if (rc)
return rc;
}
}
+_free_ret:
+ free(buf1);
+ free(buf2);
return 0;
}
--
To view, visit https://review.coreboot.org/c/flashrom/+/31830
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: flashrom
Gerrit-Branch: master
Gerrit-Change-Id: If47476793721a0061fd65bc6d1f98d48b03dc6c1
Gerrit-Change-Number: 31830
Gerrit-PatchSet: 1
Gerrit-Owner: mikeb mikeb <mikebdp2(a)gmail.com>
Gerrit-Reviewer: Mike Banon <mikebdp2(a)gmail.com>
Gerrit-MessageType: newchange
18 hours, 17 minutes
Change in flashrom[master]: chipset_enable: Mark Intel/CM246 as DEP
by Nico Huber (Code Review)
Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/34073 )
Change subject: chipset_enable: Mark Intel/CM246 as DEP
......................................................................
chipset_enable: Mark Intel/CM246 as DEP
The usual ME-lock limitations apply, so this is DEP instead
of OK.
Tested on Siemens/Field PG M6, and also regression tested on
Apollo Lake and Skylake. Flashrom works fine, and logs and
descriptor dumps look good. Also, register and descriptor
output agree on the flash layout and permissions.
Change-Id: I40db4773f127bec63e377e1d2ab402b47edf9a61
Signed-off-by: Nico Huber <nico.huber(a)secunet.com>
---
M chipset_enable.c
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/73/34073/1
diff --git a/chipset_enable.c b/chipset_enable.c
index 3773158..f75f94d 100644
--- a/chipset_enable.c
+++ b/chipset_enable.c
@@ -2044,7 +2044,7 @@
{0x8086, 0xa30a, B_S, NT, "Intel", "C242", enable_flash_pch300},
{0x8086, 0xa30c, B_S, NT, "Intel", "QM370", enable_flash_pch300},
{0x8086, 0xa30d, B_S, NT, "Intel", "HM370", enable_flash_pch300},
- {0x8086, 0xa30e, B_S, NT, "Intel", "CM246", enable_flash_pch300},
+ {0x8086, 0xa30e, B_S, DEP, "Intel", "CM246", enable_flash_pch300},
#endif
{0},
};
--
To view, visit https://review.coreboot.org/c/flashrom/+/34073
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: flashrom
Gerrit-Branch: master
Gerrit-Change-Id: I40db4773f127bec63e377e1d2ab402b47edf9a61
Gerrit-Change-Number: 34073
Gerrit-PatchSet: 1
Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>
Gerrit-MessageType: newchange
1 week, 4 days
Change in flashrom[master]: chipset_enable: Add support for Cannon Lake U Premium
by Matt DeVillier (Code Review)
Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/34076 )
Change subject: chipset_enable: Add support for Cannon Lake U Premium
......................................................................
chipset_enable: Add support for Cannon Lake U Premium
Add support for Cannon Lake U Premium (CFL-U/WHL-U).
Same as discrete 300-series CNP PCH.
Tested on out-of-tree WHL-U board.
Change-Id: I8a318d63cf408a3b2cec436a3fa6e26cf8552ead
Signed-off-by: Matt DeVillier <matt.devillier(a)puri.sm>
---
M chipset_enable.c
1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/76/34076/1
diff --git a/chipset_enable.c b/chipset_enable.c
index 3773158..e880e73 100644
--- a/chipset_enable.c
+++ b/chipset_enable.c
@@ -1995,6 +1995,7 @@
{0x8086, 0x9d53, B_S, NT, "Intel", "Kaby Lake U Base", enable_flash_pch100},
{0x8086, 0x9d56, B_S, NT, "Intel", "Kaby Lake Y Premium", enable_flash_pch100},
{0x8086, 0x9d58, B_S, NT, "Intel", "Kaby Lake U Premium", enable_flash_pch100},
+ {0x8086, 0x9d84, B_S, NT, "Intel", "Cannon Lake U Premium", enable_flash_pch300},
{0x8086, 0xa141, B_S, NT, "Intel", "Sunrise Point Desktop Sample", enable_flash_pch100},
{0x8086, 0xa142, B_S, NT, "Intel", "Sunrise Point Unknown Sample", enable_flash_pch100},
{0x8086, 0xa143, B_S, NT, "Intel", "H110", enable_flash_pch100},
--
To view, visit https://review.coreboot.org/c/flashrom/+/34076
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: flashrom
Gerrit-Branch: master
Gerrit-Change-Id: I8a318d63cf408a3b2cec436a3fa6e26cf8552ead
Gerrit-Change-Number: 34076
Gerrit-PatchSet: 1
Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>
Gerrit-MessageType: newchange
1 week, 4 days
Change in flashrom[master]: ichspi: Add support for discrete Cannon Lake PCHs
by Nico Huber (Code Review)
Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/34072 )
Change subject: ichspi: Add support for discrete Cannon Lake PCHs
......................................................................
ichspi: Add support for discrete Cannon Lake PCHs
Only minor differences in the Firmware Descriptor, compared to their
predecessors.
We extend our check on the `ICCRIBA` field in the descriptor to dis-
tinguish it from older generation. Alas, the `freq_read` field was
repurposed, so we can't use it as sanity check any more.
Change-Id: I1c2d1e8916cecd756e7ac1f0ba221d7cc361ba02
Signed-off-by: Nico Huber <nico.huber(a)secunet.com>
---
M chipset_enable.c
M ich_descriptors.c
M ich_descriptors.h
M ichspi.c
M util/ich_descriptors_tool/ich_descriptors_tool.c
5 files changed, 87 insertions(+), 32 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/72/34072/1
diff --git a/chipset_enable.c b/chipset_enable.c
index 4b0bab5..3773158 100644
--- a/chipset_enable.c
+++ b/chipset_enable.c
@@ -2035,16 +2035,16 @@
{0x8086, 0xa2c9, B_S, NT, "Intel", "Z370", enable_flash_pch100},
{0x8086, 0xa2d2, B_S, NT, "Intel", "X299", enable_flash_pch100},
{0x8086, 0x5ae8, B_S, DEP, "Intel", "Apollo Lake", enable_flash_apl},
- {0x8086, 0xa303, B_S, BAD, "Intel", "H310", enable_flash_pch300},
- {0x8086, 0xa304, B_S, BAD, "Intel", "H370", enable_flash_pch300},
- {0x8086, 0xa305, B_S, BAD, "Intel", "Z390", enable_flash_pch300},
- {0x8086, 0xa306, B_S, BAD, "Intel", "Q370", enable_flash_pch300},
- {0x8086, 0xa308, B_S, BAD, "Intel", "B360", enable_flash_pch300},
- {0x8086, 0xa309, B_S, BAD, "Intel", "C246", enable_flash_pch300},
- {0x8086, 0xa30a, B_S, BAD, "Intel", "C242", enable_flash_pch300},
- {0x8086, 0xa30c, B_S, BAD, "Intel", "QM370", enable_flash_pch300},
- {0x8086, 0xa30d, B_S, BAD, "Intel", "HM370", enable_flash_pch300},
- {0x8086, 0xa30e, B_S, BAD, "Intel", "CM246", enable_flash_pch300},
+ {0x8086, 0xa303, B_S, NT, "Intel", "H310", enable_flash_pch300},
+ {0x8086, 0xa304, B_S, NT, "Intel", "H370", enable_flash_pch300},
+ {0x8086, 0xa305, B_S, NT, "Intel", "Z390", enable_flash_pch300},
+ {0x8086, 0xa306, B_S, NT, "Intel", "Q370", enable_flash_pch300},
+ {0x8086, 0xa308, B_S, NT, "Intel", "B360", enable_flash_pch300},
+ {0x8086, 0xa309, B_S, NT, "Intel", "C246", enable_flash_pch300},
+ {0x8086, 0xa30a, B_S, NT, "Intel", "C242", enable_flash_pch300},
+ {0x8086, 0xa30c, B_S, NT, "Intel", "QM370", enable_flash_pch300},
+ {0x8086, 0xa30d, B_S, NT, "Intel", "HM370", enable_flash_pch300},
+ {0x8086, 0xa30e, B_S, NT, "Intel", "CM246", enable_flash_pch300},
#endif
{0},
};
diff --git a/ich_descriptors.c b/ich_descriptors.c
index a757add..9653d60 100644
--- a/ich_descriptors.c
+++ b/ich_descriptors.c
@@ -45,6 +45,7 @@
case CHIPSET_APOLLO_LAKE:
return 6;
case CHIPSET_C620_SERIES_LEWISBURG:
+ case CHIPSET_300_SERIES_CANNON_POINT:
return 16;
case CHIPSET_100_SERIES_SUNRISE_POINT:
return 10;
@@ -106,7 +107,7 @@
"5 series Ibex Peak", "6 series Cougar Point", "7 series Panther Point",
"8 series Lynx Point", "Baytrail", "8 series Lynx Point LP", "8 series Wellsburg",
"9 series Wildcat Point", "9 series Wildcat Point LP", "100 series Sunrise Point",
- "C620 series Lewisburg", "Apollo Lake",
+ "C620 series Lewisburg", "300 series Cannon Point", "Apollo Lake",
};
if (cs < CHIPSET_ICH8 || cs - CHIPSET_ICH8 + 1 >= ARRAY_SIZE(chipset_names))
cs = 0;
@@ -198,6 +199,7 @@
case CHIPSET_9_SERIES_WILDCAT_POINT_LP:
case CHIPSET_100_SERIES_SUNRISE_POINT:
case CHIPSET_C620_SERIES_LEWISBURG:
+ case CHIPSET_300_SERIES_CANNON_POINT:
case CHIPSET_APOLLO_LAKE: {
uint8_t size_enc;
if (idx == 0) {
@@ -265,6 +267,7 @@
return freq_str[0][value];
case CHIPSET_100_SERIES_SUNRISE_POINT:
case CHIPSET_C620_SERIES_LEWISBURG:
+ case CHIPSET_300_SERIES_CANNON_POINT:
return freq_str[1][value];
case CHIPSET_APOLLO_LAKE:
return freq_str[2][value];
@@ -281,6 +284,7 @@
switch (cs) {
case CHIPSET_100_SERIES_SUNRISE_POINT:
case CHIPSET_C620_SERIES_LEWISBURG:
+ case CHIPSET_300_SERIES_CANNON_POINT:
case CHIPSET_APOLLO_LAKE:
has_flill1 = true;
break;
@@ -398,7 +402,8 @@
msg_pdbg2("\n");
msg_pdbg2("--- Details ---\n");
- if (cs == CHIPSET_100_SERIES_SUNRISE_POINT) {
+ if (cs == CHIPSET_100_SERIES_SUNRISE_POINT ||
+ cs == CHIPSET_300_SERIES_CANNON_POINT) {
const char *const master_names[] = {
"BIOS", "ME", "GbE", "unknown", "EC",
};
@@ -408,14 +413,26 @@
return;
}
- msg_pdbg2(" FD BIOS ME GbE Pltf Reg5 Reg6 Reg7 EC Reg9\n");
+ size_t num_regions;
+ msg_pdbg2(" FD BIOS ME GbE Pltf Reg5 Reg6 Reg7 EC Reg9");
+ if (cs == CHIPSET_100_SERIES_SUNRISE_POINT) {
+ num_regions = 10;
+ msg_pdbg2("\n");
+ } else {
+ num_regions = 16;
+ msg_pdbg2(" RegA RegB RegC RegD RegE RegF\n");
+ }
for (i = 0; i < nm; i++) {
size_t j;
msg_pdbg2("%-4s", master_names[i]);
- for (j = 0; j < 10; j++)
+ for (j = 0; j < min(num_regions, 12); j++)
msg_pdbg2(" %c%c ",
desc->master.mstr[i].read & (1 << j) ? 'r' : ' ',
desc->master.mstr[i].write & (1 << j) ? 'w' : ' ');
+ for (; j < num_regions; j++)
+ msg_pdbg2(" %c%c ",
+ desc->master.mstr[i].ext_read & (1 << (j - 12)) ? 'r' : ' ',
+ desc->master.mstr[i].ext_write & (1 << (j - 12)) ? 'w' : ' ');
msg_pdbg2("\n");
}
} else if (cs == CHIPSET_C620_SERIES_LEWISBURG) {
@@ -919,10 +936,15 @@
return CHIPSET_8_SERIES_LYNX_POINT;
msg_pwarn("Peculiar firmware descriptor, assuming Wildcat Point compatibility.\n");
return CHIPSET_9_SERIES_WILDCAT_POINT;
- } else if (content->NM == 6) {
- return CHIPSET_C620_SERIES_LEWISBURG;
+ } else if (content->ICCRIBA < 0x34) {
+ if (content->NM == 6)
+ return CHIPSET_C620_SERIES_LEWISBURG;
+ else
+ return CHIPSET_100_SERIES_SUNRISE_POINT;
} else {
- return CHIPSET_100_SERIES_SUNRISE_POINT;
+ if (content->ICCRIBA > 0x34)
+ msg_pwarn("Unknown firmware descriptor, assuming 300 series compatibility.\n");
+ return CHIPSET_300_SERIES_CANNON_POINT;
}
}
@@ -938,6 +960,9 @@
const enum ich_chipset guess = guess_ich_chipset_from_content(content);
switch (guess) {
+ case CHIPSET_300_SERIES_CANNON_POINT:
+ /* `freq_read` was repurposed, so can't check on it any more. */
+ return guess;
case CHIPSET_100_SERIES_SUNRISE_POINT:
case CHIPSET_C620_SERIES_LEWISBURG:
case CHIPSET_APOLLO_LAKE:
@@ -1089,6 +1114,7 @@
case CHIPSET_9_SERIES_WILDCAT_POINT_LP:
case CHIPSET_100_SERIES_SUNRISE_POINT:
case CHIPSET_C620_SERIES_LEWISBURG:
+ case CHIPSET_300_SERIES_CANNON_POINT:
case CHIPSET_APOLLO_LAKE:
if (idx == 0) {
size_enc = desc->component.dens_new.comp1_density;
@@ -1123,6 +1149,7 @@
switch (cs) {
case CHIPSET_100_SERIES_SUNRISE_POINT:
case CHIPSET_C620_SERIES_LEWISBURG:
+ case CHIPSET_300_SERIES_CANNON_POINT:
case CHIPSET_APOLLO_LAKE:
mmio_le_writel(control, spibar + PCH100_REG_FDOC);
return mmio_le_readl(spibar + PCH100_REG_FDOD);
diff --git a/ich_descriptors.h b/ich_descriptors.h
index 4225286..c6bf5d8 100644
--- a/ich_descriptors.h
+++ b/ich_descriptors.h
@@ -170,8 +170,9 @@
* Chipset/Generation #FLREGs width (bits)
* ICH8 .. Panther Point/7 5 13
* Lynx Point/8 .. Wildcat Point/9 7 15
- * Sunrise Point/100 .. 10 15
+ * Sunrise Point/100 .. 200 Series 10 15
* Lewisburg/100 .. 16 15
+ * Cannon Point/300 .. 16 15
*/
union {
uint32_t FLREGs[MAX_NUM_FLREGS]; /* Flash Descriptor Regions */
@@ -234,9 +235,10 @@
};
/* From Skylake on */
struct {
- uint32_t :8,
- read :12,
- write :12;
+ uint32_t ext_read :4,
+ ext_write :4,
+ read :12,
+ write :12;
} mstr[MAX_NUM_MASTERS];
};
};
diff --git a/ichspi.c b/ichspi.c
index e1ede60..68bd5d7 100644
--- a/ichspi.c
+++ b/ichspi.c
@@ -395,15 +395,25 @@
pprint_reg(HSFS, FDONE, reg_val, ", ");
pprint_reg(HSFS, FCERR, reg_val, ", ");
pprint_reg(HSFS, AEL, reg_val, ", ");
- if (ich_generation != CHIPSET_100_SERIES_SUNRISE_POINT &&
- ich_generation != CHIPSET_C620_SERIES_LEWISBURG) {
+ switch (ich_generation) {
+ case CHIPSET_100_SERIES_SUNRISE_POINT:
+ case CHIPSET_C620_SERIES_LEWISBURG:
+ case CHIPSET_300_SERIES_CANNON_POINT:
+ break;
+ default:
pprint_reg(HSFS, BERASE, reg_val, ", ");
+ break;
}
pprint_reg(HSFS, SCIP, reg_val, ", ");
- if (ich_generation == CHIPSET_100_SERIES_SUNRISE_POINT ||
- ich_generation == CHIPSET_C620_SERIES_LEWISBURG) {
+ switch (ich_generation) {
+ case CHIPSET_100_SERIES_SUNRISE_POINT:
+ case CHIPSET_C620_SERIES_LEWISBURG:
+ case CHIPSET_300_SERIES_CANNON_POINT:
pprint_reg(HSFS, PRR34_LOCKDN, reg_val, ", ");
pprint_reg(HSFS, WRSDIS, reg_val, ", ");
+ break;
+ default:
+ break;
}
pprint_reg(HSFS, FDOPSS, reg_val, ", ");
pprint_reg(HSFS, FDV, reg_val, ", ");
@@ -414,12 +424,16 @@
{
msg_pdbg("HSFC: ");
pprint_reg(HSFC, FGO, reg_val, ", ");
- if (ich_generation != CHIPSET_100_SERIES_SUNRISE_POINT &&
- ich_generation != CHIPSET_C620_SERIES_LEWISBURG) {
- pprint_reg(HSFC, FCYCLE, reg_val, ", ");
- } else {
+ switch (ich_generation) {
+ case CHIPSET_100_SERIES_SUNRISE_POINT:
+ case CHIPSET_C620_SERIES_LEWISBURG:
+ case CHIPSET_300_SERIES_CANNON_POINT:
_pprint_reg(HSFC, PCH100_HSFC_FCYCLE, PCH100_HSFC_FCYCLE_OFF, reg_val, ", ");
pprint_reg(HSFC, WET, reg_val, ", ");
+ break;
+ default:
+ pprint_reg(HSFC, FCYCLE, reg_val, ", ");
+ break;
}
pprint_reg(HSFC, FDBC, reg_val, ", ");
pprint_reg(HSFC, SME, reg_val, "\n");
@@ -1567,9 +1581,10 @@
static enum ich_access_protection ich9_handle_frap(uint32_t frap, int i)
{
const int rwperms_unknown = ARRAY_SIZE(access_names);
- static const char *const region_names[6] = {
+ static const char *const region_names[] = {
"Flash Descriptor", "BIOS", "Management Engine",
"Gigabit Ethernet", "Platform Data", "Device Expansion",
+ "BIOS2", "unknown", "EC/BMC",
};
const char *const region_name = i < ARRAY_SIZE(region_names) ? region_names[i] : "unknown";
@@ -1724,6 +1739,7 @@
switch (ich_generation) {
case CHIPSET_100_SERIES_SUNRISE_POINT:
case CHIPSET_C620_SERIES_LEWISBURG:
+ case CHIPSET_300_SERIES_CANNON_POINT:
case CHIPSET_APOLLO_LAKE:
num_pr = 6; /* Includes GPR0 */
reg_pr0 = PCH100_REG_FPR0;
@@ -1754,6 +1770,7 @@
case CHIPSET_C620_SERIES_LEWISBURG:
num_freg = 12; /* 12 MMIO regs, but 16 regions in FD spec */
break;
+ case CHIPSET_300_SERIES_CANNON_POINT:
case CHIPSET_APOLLO_LAKE:
num_freg = 16;
break;
@@ -1848,6 +1865,7 @@
switch (ich_gen) {
case CHIPSET_100_SERIES_SUNRISE_POINT:
case CHIPSET_C620_SERIES_LEWISBURG:
+ case CHIPSET_300_SERIES_CANNON_POINT:
case CHIPSET_APOLLO_LAKE:
tmp = mmio_readl(ich_spibar + PCH100_REG_DLOCK);
msg_pdbg("0x0c: 0x%08x (DLOCK)\n", tmp);
@@ -1921,6 +1939,7 @@
case CHIPSET_ICH8:
case CHIPSET_100_SERIES_SUNRISE_POINT:
case CHIPSET_C620_SERIES_LEWISBURG:
+ case CHIPSET_300_SERIES_CANNON_POINT:
case CHIPSET_APOLLO_LAKE:
case CHIPSET_BAYTRAIL:
break;
@@ -1952,6 +1971,7 @@
case CHIPSET_ICH8:
case CHIPSET_100_SERIES_SUNRISE_POINT:
case CHIPSET_C620_SERIES_LEWISBURG:
+ case CHIPSET_300_SERIES_CANNON_POINT:
case CHIPSET_APOLLO_LAKE:
break;
default:
@@ -1981,8 +2001,10 @@
ich_spi_mode = ich_hwseq;
}
- if (ich_spi_mode == ich_auto && ich_gen == CHIPSET_100_SERIES_SUNRISE_POINT) {
- msg_pdbg("Enabling hardware sequencing by default for 100 series PCH.\n");
+ if (ich_spi_mode == ich_auto &&
+ (ich_gen == CHIPSET_100_SERIES_SUNRISE_POINT ||
+ ich_gen == CHIPSET_300_SERIES_CANNON_POINT)) {
+ msg_pdbg("Enabling hardware sequencing by default for 100+ series PCH.\n");
ich_spi_mode = ich_hwseq;
}
diff --git a/util/ich_descriptors_tool/ich_descriptors_tool.c b/util/ich_descriptors_tool/ich_descriptors_tool.c
index 2c7966d..2db0f62 100644
--- a/util/ich_descriptors_tool/ich_descriptors_tool.c
+++ b/util/ich_descriptors_tool/ich_descriptors_tool.c
@@ -133,6 +133,7 @@
"\t- \"8\" or \"lynx\" for Intel's 8 series chipsets.\n"
"\t- \"9\" or \"wildcat\" for Intel's 9 series chipsets.\n"
"\t- \"100\" or \"sunrise\" for Intel's 100 series chipsets.\n"
+"\t- \"300\" or \"cannon\" for Intel's 300 series chipsets.\n"
"If '-d' is specified some regions such as the BIOS image as seen by the CPU or\n"
"the GbE blob that is required to initialize the GbE are also dumped to files.\n",
argv[0], argv[0]);
@@ -221,6 +222,9 @@
else if ((strcmp(csn, "100") == 0) ||
(strcmp(csn, "sunrise") == 0))
cs = CHIPSET_100_SERIES_SUNRISE_POINT;
+ else if ((strcmp(csn, "300") == 0) ||
+ (strcmp(csn, "cannon") == 0))
+ cs = CHIPSET_300_SERIES_CANNON_POINT;
else if (strcmp(csn, "apollo") == 0)
cs = CHIPSET_APOLLO_LAKE;
}
--
To view, visit https://review.coreboot.org/c/flashrom/+/34072
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: flashrom
Gerrit-Branch: master
Gerrit-Change-Id: I1c2d1e8916cecd756e7ac1f0ba221d7cc361ba02
Gerrit-Change-Number: 34072
Gerrit-PatchSet: 1
Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>
Gerrit-MessageType: newchange
1 week, 4 days
Change in flashrom[master]: chipset_enable: Add support for discrete Cannon Lake PCHs
by Nico Huber (Code Review)
Hello Thomas Heijligen,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/flashrom/+/34071
to review the following change.
Change subject: chipset_enable: Add support for discrete Cannon Lake PCHs
......................................................................
chipset_enable: Add support for discrete Cannon Lake PCHs
The Cannon Lake "300 Series" PCHs [1,2] share the register layout of the
Skylake "100 Series". Mark them as BAD until `ichspi.c` is adapted.
[1] Intel® 300 Series and Intel® C240 Seri
Chipset Family Platform Controller Hub
Datasheet - Volume 1 of 2
Revison 4 (Dec 2018)
Document Number 337347
[2] Intel® 300 Series Chipset Families Platform Controller Hu
Datasheet - Volume 2 of 2
Revision 2? (Oct 2018)
Document Number 337348
Change-Id: If0b54799d5b93169ee660409bad57ae14677340c
Signed-off-by: Thomas Heijligen <thomas.heijligen(a)secunet.com>
Signed-off-by: Nico Huber <nico.huber(a)secunet.com>
---
M chipset_enable.c
M programmer.h
2 files changed, 19 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/71/34071/1
diff --git a/chipset_enable.c b/chipset_enable.c
index 08feda5..4b0bab5 100644
--- a/chipset_enable.c
+++ b/chipset_enable.c
@@ -598,6 +598,7 @@
break;
case CHIPSET_100_SERIES_SUNRISE_POINT:
case CHIPSET_C620_SERIES_LEWISBURG:
+ case CHIPSET_300_SERIES_CANNON_POINT:
case CHIPSET_APOLLO_LAKE:
reg_name = "BIOS_SPI_BC";
gcs = pci_read_long(dev, 0xdc);
@@ -692,6 +693,7 @@
case CHIPSET_9_SERIES_WILDCAT_POINT_LP:
case CHIPSET_100_SERIES_SUNRISE_POINT:
case CHIPSET_C620_SERIES_LEWISBURG:
+ case CHIPSET_300_SERIES_CANNON_POINT:
boot_straps = boot_straps_pch8_lp;
break;
case CHIPSET_APOLLO_LAKE:
@@ -719,6 +721,7 @@
break;
case CHIPSET_100_SERIES_SUNRISE_POINT:
case CHIPSET_C620_SERIES_LEWISBURG:
+ case CHIPSET_300_SERIES_CANNON_POINT:
case CHIPSET_APOLLO_LAKE:
bbs = (gcs >> 6) & 0x1;
break;
@@ -947,6 +950,11 @@
return enable_flash_pch100_or_c620(dev, name, 0x1f, 5, CHIPSET_C620_SERIES_LEWISBURG);
}
+static int enable_flash_pch300(struct pci_dev *const dev, const char *const name)
+{
+ return enable_flash_pch100_or_c620(dev, name, 0x1f, 5, CHIPSET_300_SERIES_CANNON_POINT);
+}
+
static int enable_flash_apl(struct pci_dev *const dev, const char *const name)
{
return enable_flash_pch100_or_c620(dev, name, 0x0d, 2, CHIPSET_APOLLO_LAKE);
@@ -2027,6 +2035,16 @@
{0x8086, 0xa2c9, B_S, NT, "Intel", "Z370", enable_flash_pch100},
{0x8086, 0xa2d2, B_S, NT, "Intel", "X299", enable_flash_pch100},
{0x8086, 0x5ae8, B_S, DEP, "Intel", "Apollo Lake", enable_flash_apl},
+ {0x8086, 0xa303, B_S, BAD, "Intel", "H310", enable_flash_pch300},
+ {0x8086, 0xa304, B_S, BAD, "Intel", "H370", enable_flash_pch300},
+ {0x8086, 0xa305, B_S, BAD, "Intel", "Z390", enable_flash_pch300},
+ {0x8086, 0xa306, B_S, BAD, "Intel", "Q370", enable_flash_pch300},
+ {0x8086, 0xa308, B_S, BAD, "Intel", "B360", enable_flash_pch300},
+ {0x8086, 0xa309, B_S, BAD, "Intel", "C246", enable_flash_pch300},
+ {0x8086, 0xa30a, B_S, BAD, "Intel", "C242", enable_flash_pch300},
+ {0x8086, 0xa30c, B_S, BAD, "Intel", "QM370", enable_flash_pch300},
+ {0x8086, 0xa30d, B_S, BAD, "Intel", "HM370", enable_flash_pch300},
+ {0x8086, 0xa30e, B_S, BAD, "Intel", "CM246", enable_flash_pch300},
#endif
{0},
};
diff --git a/programmer.h b/programmer.h
index f4e8b46..4a51243 100644
--- a/programmer.h
+++ b/programmer.h
@@ -626,6 +626,7 @@
CHIPSET_9_SERIES_WILDCAT_POINT_LP,
CHIPSET_100_SERIES_SUNRISE_POINT, /* also 6th/7th gen Core i/o (LP) variants */
CHIPSET_C620_SERIES_LEWISBURG,
+ CHIPSET_300_SERIES_CANNON_POINT,
CHIPSET_APOLLO_LAKE,
};
--
To view, visit https://review.coreboot.org/c/flashrom/+/34071
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: flashrom
Gerrit-Branch: master
Gerrit-Change-Id: If0b54799d5b93169ee660409bad57ae14677340c
Gerrit-Change-Number: 34071
Gerrit-PatchSet: 1
Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>
Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de>
Gerrit-MessageType: newchange
1 week, 4 days
Change in flashrom[master]: tree: Enable -Wwrite-strings
by Jacob Garber (Code Review)
Jacob Garber has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/34577 )
Change subject: tree: Enable -Wwrite-strings
......................................................................
tree: Enable -Wwrite-strings
When compiling, this warning gives string literals the type const char[]
to help catch accidental modification (which is undefined behaviour).
There currently aren't any instances of this in flashrom, so let's
enable this warning to keep it that way. This requires adding const
qualifiers to the declarations of several variables that work with
string literals.
Change-Id: I62d9bc194938a0c9a0e4cdff7ced8ea2e14cc1bc
Signed-off-by: Jacob Garber <jgarber1(a)ualberta.ca>
---
M Makefile
M buspirate_spi.c
M cli_classic.c
M dmi.c
M pony_spi.c
M util/ich_descriptors_tool/ich_descriptors_tool.c
6 files changed, 6 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/77/34577/1
diff --git a/Makefile b/Makefile
index 545e84a..1a20933 100644
--- a/Makefile
+++ b/Makefile
@@ -30,7 +30,7 @@
DIFF = diff
PREFIX ?= /usr/local
MANDIR ?= $(PREFIX)/share/man
-CFLAGS ?= -Os -Wall -Wshadow -Wmissing-prototypes
+CFLAGS ?= -Os -Wall -Wshadow -Wmissing-prototypes -Wwrite-strings
EXPORTDIR ?= .
RANLIB ?= ranlib
PKG_CONFIG ?= pkg-config
diff --git a/buspirate_spi.c b/buspirate_spi.c
index fb066c2..bc6776b 100644
--- a/buspirate_spi.c
+++ b/buspirate_spi.c
@@ -112,7 +112,7 @@
return 0;
}
-static int buspirate_wait_for_string(unsigned char *buf, char *key)
+static int buspirate_wait_for_string(unsigned char *buf, const char *key)
{
unsigned int keylen = strlen(key);
int ret;
diff --git a/cli_classic.c b/cli_classic.c
index 0591bfe..428efc1 100644
--- a/cli_classic.c
+++ b/cli_classic.c
@@ -77,7 +77,7 @@
exit(1);
}
-static int check_filename(char *filename, char *type)
+static int check_filename(char *filename, const char *type)
{
if (!filename || (filename[0] == '\0')) {
fprintf(stderr, "Error: No %s file specified.\n", type);
diff --git a/dmi.c b/dmi.c
index ae90f7c..6132b47 100644
--- a/dmi.c
+++ b/dmi.c
@@ -69,7 +69,7 @@
static const struct {
uint8_t type;
uint8_t is_laptop;
- char *name;
+ const char *name;
} dmi_chassis_types[] = {
{0x01, 2, "Other"},
{0x02, 2, "Unknown"},
diff --git a/pony_spi.c b/pony_spi.c
index 6c03308..ed9d326 100644
--- a/pony_spi.c
+++ b/pony_spi.c
@@ -115,7 +115,7 @@
int i, data_out;
char *arg = NULL;
enum pony_type type = TYPE_SI_PROG;
- char *name;
+ const char *name;
int have_device = 0;
int have_prog = 0;
diff --git a/util/ich_descriptors_tool/ich_descriptors_tool.c b/util/ich_descriptors_tool/ich_descriptors_tool.c
index 2c7966d..768401e 100644
--- a/util/ich_descriptors_tool/ich_descriptors_tool.c
+++ b/util/ich_descriptors_tool/ich_descriptors_tool.c
@@ -111,7 +111,7 @@
printf("\n");
}
-static void usage(char *argv[], char *error)
+static void usage(char *argv[], const char *error)
{
if (error != NULL) {
fprintf(stderr, "%s\n", error);
--
To view, visit https://review.coreboot.org/c/flashrom/+/34577
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: flashrom
Gerrit-Branch: master
Gerrit-Change-Id: I62d9bc194938a0c9a0e4cdff7ced8ea2e14cc1bc
Gerrit-Change-Number: 34577
Gerrit-PatchSet: 1
Gerrit-Owner: Jacob Garber <jgarber1(a)ualberta.ca>
Gerrit-MessageType: newchange
1 week, 6 days
Change in flashrom[master]: flashchips: Split MT25Q from N25Q
by Jacob Creedon (Code Review)
Jacob Creedon has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/34488 )
Change subject: flashchips: Split MT25Q from N25Q
......................................................................
flashchips: Split MT25Q from N25Q
The MT25Q is the successor to the N25Q from Micron/Numonyx/ST. The MT25Q
is almost entirely backwards compatible with the N25Q series, however,
the MT25Q has additional subsector erase commands available, and there
are differences in stacked devices in the higher capacity variants. The
N25Q devices are left with "Micron/Numonyx/ST" as the vendor and MT25Q
devices are set with "Micron" as the vendor.
Signed-off-by: Jacob Creedon <jcreedon(a)google.com>
Change-Id: I9d79978544b19cf9acd5f3ea6196cf6f3b3435ef
---
M flashchips.c
1 file changed, 82 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/88/34488/1
diff --git a/flashchips.c b/flashchips.c
index 166af6a..e6116ae 100644
--- a/flashchips.c
+++ b/flashchips.c
@@ -10544,8 +10544,88 @@
},
{
+ .vendor = "Micron/Numonyx/ST",
+ .name = "N25Q256..3E", /* ..3E = 3V, uniform 64KB/4KB blocks/sectors */
+ .bustype = BUS_SPI,
+ .manufacture_id = ST_ID,
+ .model_id = ST_N25Q256__3E,
+ .total_size = 32768,
+ .page_size = 256,
+ /* supports SFDP */
+ /* OTP: 64B total; read 0x4B, write 0x42 */
+ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_WREN,
+ .tested = TEST_UNTESTED,
+ .probe = probe_spi_rdid,
+ .probe_timing = TIMING_ZERO,
+ .block_erasers =
+ {
+ {
+ .eraseblocks = { {4 * 1024, 8192} },
+ .block_erase = spi_block_erase_21,
+ }, {
+ .eraseblocks = { {4 * 1024, 8192} },
+ .block_erase = spi_block_erase_20,
+ }, {
+ .eraseblocks = { {64 * 1024, 512} },
+ .block_erase = spi_block_erase_dc,
+ }, {
+ .eraseblocks = { {64 * 1024, 512} },
+ .block_erase = spi_block_erase_d8,
+ }, {
+ .eraseblocks = { {32768 * 1024, 1} },
+ .block_erase = spi_block_erase_c7,
+ }
+ },
+ .printlock = spi_prettyprint_status_register_n25q, /* TODO: config, lock, flag regs */
+ .unlock = spi_disable_blockprotect_n25q, /* TODO: per 64kB sector lock registers */
+ .write = spi_chip_write_256, /* Multi I/O supported */
+ .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */
+ .voltage = {2700, 3600},
+ },
+
+ {
+ .vendor = "Micron/Numonyx/ST",
+ .name = "N25Q512..3E", /* ..3E = 3V, uniform 64KB/4KB blocks/sectors */
+ .bustype = BUS_SPI,
+ .manufacture_id = ST_ID,
+ .model_id = ST_N25Q512__3E,
+ .total_size = 65536,
+ .page_size = 256,
+ /* supports SFDP */
+ /* OTP: 64B total; read 0x4B, write 0x42 */
+ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_WREN,
+ .tested = TEST_OK_PREW,
+ .probe = probe_spi_rdid,
+ .probe_timing = TIMING_ZERO,
+ .block_erasers =
+ {
+ {
+ .eraseblocks = { {4 * 1024, 16384} },
+ .block_erase = spi_block_erase_21,
+ }, {
+ .eraseblocks = { {4 * 1024, 16384} },
+ .block_erase = spi_block_erase_20,
+ }, {
+ .eraseblocks = { {64 * 1024, 1024} },
+ .block_erase = spi_block_erase_dc,
+ }, {
+ .eraseblocks = { {64 * 1024, 1024} },
+ .block_erase = spi_block_erase_d8,
+ }, {
+ .eraseblocks = { {65536 * 1024, 1} },
+ .block_erase = spi_block_erase_c7,
+ }
+ },
+ .printlock = spi_prettyprint_status_register_n25q, /* TODO: config, lock, flag regs */
+ .unlock = spi_disable_blockprotect_n25q, /* TODO: per 64kB sector lock registers */
+ .write = spi_chip_write_256, /* Multi I/O supported */
+ .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */
+ .voltage = {2700, 3600},
+ },
+
+ {
.vendor = "Micron",
- .name = "N25Q256..3E/MT25QL256", /* ..3E/L = 3V, uniform 64KB/4KB blocks/sectors */
+ .name = "MT25QL256", /* L = 3V, uniform 64KB/4KB blocks/sectors */
.bustype = BUS_SPI,
.manufacture_id = ST_ID,
.model_id = ST_N25Q256__3E,
@@ -10585,7 +10665,7 @@
{
.vendor = "Micron",
- .name = "N25Q512..3E/MT25QL512", /* ..3E/L = 3V, uniform 64KB/4KB blocks/sectors */
+ .name = "MT25QL512", /* L = 3V, uniform 64KB/4KB blocks/sectors */
.bustype = BUS_SPI,
.manufacture_id = ST_ID,
.model_id = ST_N25Q512__3E,
--
To view, visit https://review.coreboot.org/c/flashrom/+/34488
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: flashrom
Gerrit-Branch: master
Gerrit-Change-Id: I9d79978544b19cf9acd5f3ea6196cf6f3b3435ef
Gerrit-Change-Number: 34488
Gerrit-PatchSet: 1
Gerrit-Owner: Jacob Creedon <jcreedon(a)google.com>
Gerrit-MessageType: newchange
1 week, 6 days
Change in flashrom[master]: flashchips: Fix part names for N25Q512 and N25Q00A
by Jacob Creedon (Code Review)
Jacob Creedon has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/34520 )
Change subject: flashchips: Fix part names for N25Q512 and N25Q00A
......................................................................
flashchips: Fix part names for N25Q512 and N25Q00A
For the N25Q512 and N25Q00A, the 1G and 3G are used instead of 1E and 3E
to represent 1.8v and 3v respectively.
Signed-off-by: Jacob Creedon <jcreedon(a)google.com>
Change-Id: I289c33f7293f47b9449907350654cd6183c778d4
---
M flashchips.c
M flashchips.h
2 files changed, 12 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/20/34520/1
diff --git a/flashchips.c b/flashchips.c
index 3a0da8d..021ae6c 100644
--- a/flashchips.c
+++ b/flashchips.c
@@ -10625,10 +10625,10 @@
{
.vendor = "Micron/Numonyx/ST",
- .name = "N25Q512..1E", /* ..1E = 1.8V, uniform 64KB/4KB blocks/sectors */
+ .name = "N25Q512..1G", /* ..1G = 1.8V, uniform 64KB/4KB blocks/sectors */
.bustype = BUS_SPI,
.manufacture_id = ST_ID,
- .model_id = ST_N25Q512__1E,
+ .model_id = ST_N25Q512__1G,
.total_size = 65536,
.page_size = 256,
/* supports SFDP */
@@ -10665,10 +10665,10 @@
{
.vendor = "Micron/Numonyx/ST",
- .name = "N25Q512..3E", /* ..3E = 3V, uniform 64KB/4KB blocks/sectors */
+ .name = "N25Q512..3G", /* ..3G = 3V, uniform 64KB/4KB blocks/sectors */
.bustype = BUS_SPI,
.manufacture_id = ST_ID,
- .model_id = ST_N25Q512__3E,
+ .model_id = ST_N25Q512__3G,
.total_size = 65536,
.page_size = 256,
/* supports SFDP */
@@ -10708,7 +10708,7 @@
.name = "MT25QL01G", /* L = 3V, uniform 64KB/4KB blocks/sectors */
.bustype = BUS_SPI,
.manufacture_id = ST_ID,
- .model_id = ST_N25Q00A__3E,
+ .model_id = ST_N25Q00A__3G,
.total_size = 131072,
.page_size = 256,
/* supports SFDP */
@@ -10754,7 +10754,7 @@
.name = "MT25QU01G", /* U = 1.8V, uniform 64KB/4KB blocks/sectors */
.bustype = BUS_SPI,
.manufacture_id = ST_ID,
- .model_id = ST_N25Q00A__1E,
+ .model_id = ST_N25Q00A__1G,
.total_size = 131072,
.page_size = 256,
/* supports SFDP */
@@ -11070,7 +11070,7 @@
.name = "MT25QL512", /* L = 3V, uniform 64KB/4KB blocks/sectors */
.bustype = BUS_SPI,
.manufacture_id = ST_ID,
- .model_id = ST_N25Q512__3E,
+ .model_id = ST_N25Q512__3G,
.total_size = 65536,
.page_size = 256,
/* supports SFDP */
@@ -11119,7 +11119,7 @@
.name = "MT25QU512", /* U = 1.8V, uniform 64KB/4KB blocks/sectors */
.bustype = BUS_SPI,
.manufacture_id = ST_ID,
- .model_id = ST_N25Q512__1E,
+ .model_id = ST_N25Q512__1G,
.total_size = 65536,
.page_size = 256,
/* supports SFDP */
diff --git a/flashchips.h b/flashchips.h
index e53e0df..0dcf735 100644
--- a/flashchips.h
+++ b/flashchips.h
@@ -866,10 +866,10 @@
#define ST_N25Q128__1E 0xBB18 /* N25Q128/MT25QU128, 1.8V, (uniform sectors expected) */
#define ST_N25Q256__3E 0xBA19 /* N25Q256/MT25QL256, 3.0V, (uniform sectors expected) */
#define ST_N25Q256__1E 0xBB19 /* N25Q256/MT25QU256, 1.8V, (uniform sectors expected) */
-#define ST_N25Q512__3E 0xBA20 /* N25Q512/MT25QL512, 3.0V, (uniform sectors expected) */
-#define ST_N25Q512__1E 0xBB20 /* N25Q512/MT25QU512, 1.8V, (uniform sectors expected) */
-#define ST_N25Q00A__3E 0xBA21 /* N25Q00A/MT25QL01G, 3.0V, (uniform sectors expected) */
-#define ST_N25Q00A__1E 0xBB21 /* N25Q00A/MT25QU01G, 1.8V, (uniform sectors expected) */
+#define ST_N25Q512__3G 0xBA20 /* N25Q512/MT25QL512, 3.0V, (uniform sectors expected) */
+#define ST_N25Q512__1G 0xBB20 /* N25Q512/MT25QU512, 1.8V, (uniform sectors expected) */
+#define ST_N25Q00A__3G 0xBA21 /* N25Q00A/MT25QL01G, 3.0V, (uniform sectors expected) */
+#define ST_N25Q00A__1G 0xBB21 /* N25Q00A/MT25QU01G, 1.8V, (uniform sectors expected) */
#define ST_MT25QL02G 0xBA22 /* MT25QL02G, 3.0V, (uniform sectors expected) */
#define ST_MT25QU02G 0xBB22 /* MT25QU02G, 1.8V, (uniform sectors expected) */
#define ST_NP5Q032 0xDA16 /* Phase-change memory (PCM), 3V */
--
To view, visit https://review.coreboot.org/c/flashrom/+/34520
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: flashrom
Gerrit-Branch: master
Gerrit-Change-Id: I289c33f7293f47b9449907350654cd6183c778d4
Gerrit-Change-Number: 34520
Gerrit-PatchSet: 1
Gerrit-Owner: Jacob Creedon <jcreedon(a)google.com>
Gerrit-MessageType: newchange
2 weeks
Change in flashrom[master]: flashchips: Add missing MT25Q erase commands
by Jacob Creedon (Code Review)
Jacob Creedon has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/34490 )
Change subject: flashchips: Add missing MT25Q erase commands
......................................................................
flashchips: Add missing MT25Q erase commands
This adds additional 32KiB subsecor erase commands 0x5c and 0x52 and an
additional bulk erase command of 0x60.
Signed-off-by: Jacob Creedon <jcreedon(a)google.com>
Change-Id: I5307c4b96cbd62203f5bad0c94737180fda621aa
---
M flashchips.c
1 file changed, 18 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/90/34490/1
diff --git a/flashchips.c b/flashchips.c
index 78873eb..d25f7a2 100644
--- a/flashchips.c
+++ b/flashchips.c
@@ -10646,6 +10646,12 @@
.eraseblocks = { {4 * 1024, 8192} },
.block_erase = spi_block_erase_20,
}, {
+ .eraseblocks = { {32 * 1024, 1024} },
+ .block_erase = spi_block_erase_5c,
+ }, {
+ .eraseblocks = { {32 * 1024, 1024} },
+ .block_erase = spi_block_erase_52,
+ }, {
.eraseblocks = { {64 * 1024, 512} },
.block_erase = spi_block_erase_dc,
}, {
@@ -10654,6 +10660,9 @@
}, {
.eraseblocks = { {32768 * 1024, 1} },
.block_erase = spi_block_erase_c7,
+ }, {
+ .eraseblocks = { {32768 * 1024, 1} },
+ .block_erase = spi_block_erase_60,
}
},
.printlock = spi_prettyprint_status_register_n25q, /* TODO: config, lock, flag regs */
@@ -10686,6 +10695,12 @@
.eraseblocks = { {4 * 1024, 16384} },
.block_erase = spi_block_erase_20,
}, {
+ .eraseblocks = { {32 * 1024, 2048} },
+ .block_erase = spi_block_erase_5c,
+ }, {
+ .eraseblocks = { {32 * 1024, 2048} },
+ .block_erase = spi_block_erase_52,
+ }, {
.eraseblocks = { {64 * 1024, 1024} },
.block_erase = spi_block_erase_dc,
}, {
@@ -10694,6 +10709,9 @@
}, {
.eraseblocks = { {65536 * 1024, 1} },
.block_erase = spi_block_erase_c7,
+ }, {
+ .eraseblocks = { {65536 * 1024, 1} },
+ .block_erase = spi_block_erase_60,
}
},
.printlock = spi_prettyprint_status_register_n25q, /* TODO: config, lock, flag regs */
--
To view, visit https://review.coreboot.org/c/flashrom/+/34490
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: flashrom
Gerrit-Branch: master
Gerrit-Change-Id: I5307c4b96cbd62203f5bad0c94737180fda621aa
Gerrit-Change-Number: 34490
Gerrit-PatchSet: 1
Gerrit-Owner: Jacob Creedon <jcreedon(a)google.com>
Gerrit-MessageType: newchange
2 weeks
Change in flashrom[master]: flashchips: Fix N25Q512 bulk erase
by Jacob Creedon (Code Review)
Jacob Creedon has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/34489 )
Change subject: flashchips: Fix N25Q512 bulk erase
......................................................................
flashchips: Fix N25Q512 bulk erase
The N25Q is a stacked device, so it requires 0xC4 to perform a die
erase.
Signed-off-by: Jacob Creedon <jcreedon(a)google.com>
Change-Id: Ib408fbe5633abd8b657e3907142b997e88b33f84
---
M flashchips.c
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/89/34489/1
diff --git a/flashchips.c b/flashchips.c
index e6116ae..78873eb 100644
--- a/flashchips.c
+++ b/flashchips.c
@@ -10613,7 +10613,7 @@
.block_erase = spi_block_erase_d8,
}, {
.eraseblocks = { {65536 * 1024, 1} },
- .block_erase = spi_block_erase_c7,
+ .block_erase = spi_block_erase_c4,
}
},
.printlock = spi_prettyprint_status_register_n25q, /* TODO: config, lock, flag regs */
--
To view, visit https://review.coreboot.org/c/flashrom/+/34489
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: flashrom
Gerrit-Branch: master
Gerrit-Change-Id: Ib408fbe5633abd8b657e3907142b997e88b33f84
Gerrit-Change-Number: 34489
Gerrit-PatchSet: 1
Gerrit-Owner: Jacob Creedon <jcreedon(a)google.com>
Gerrit-MessageType: newchange
2 weeks