February 2020 - flashrom-gerrit

Change in flashrom[master]: Install the man file when using meson as a buildsystem

by Richard Hughes (Code Review)

Richard Hughes has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/38939 ) Change subject: Install the man file when using meson as a buildsystem ...................................................................... Install the man file when using meson as a buildsystem This fixes a regression with the Fedora package. Change-Id: I881bd5002a842072ce9dadea033c51a2668f9e7c Signed-off-by: Richard Hughes <richard(a)hughsie.com> --- M meson.build 1 file changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/39/38939/1 diff --git a/meson.build b/meson.build index 375089c..df39290 100644 --- a/meson.build +++ b/meson.build @@ -299,6 +299,7 @@ prefix = get_option('prefix') sbindir = join_paths(prefix, get_option('sbindir')) libdir = join_paths(prefix, get_option('libdir')) +mandir = join_paths(prefix, get_option('mandir')) install_headers([ 'libflashrom.h', @@ -372,6 +373,14 @@ description : 'library to interact with flashrom', ) +configure_file( + input : 'flashrom.8.tmpl', + output : 'flashrom.8', + copy: true, + install: true, + install_dir: join_paths(mandir, 'man8'), +) + flashrom_dep = declare_dependency( link_with : flashrom, include_directories : include_directories('.'), -- To view, visit https://review.coreboot.org/c/flashrom/+/38939 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I881bd5002a842072ce9dadea033c51a2668f9e7c Gerrit-Change-Number: 38939 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Hughes <richard(a)hughsie.com> Gerrit-MessageType: newchange

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Change in ...flashrom[master]: cli_classic: Report the gathered layout entries at level dbg

by Nico Huber (Code Review)

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/31012 Change subject: cli_classic: Report the gathered layout entries at level dbg ...................................................................... cli_classic: Report the gathered layout entries at level dbg Change-Id: I7678ba5138f0d722ee44747fe123f192abdd0ffd Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M cli_classic.c M layout.c M layout.h 3 files changed, 18 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/12/31012/1 diff --git a/cli_classic.c b/cli_classic.c index ced08c6..536ef24 100644 --- a/cli_classic.c +++ b/cli_classic.c @@ -645,6 +645,8 @@ goto out_shutdown; } + report_layout(layout); + flashrom_layout_set(fill_flash, layout); flashrom_flag_set(fill_flash, FLASHROM_FLAG_FORCE, !!force); #if CONFIG_INTERNAL == 1 diff --git a/layout.c b/layout.c index fa66238..c589d17 100644 --- a/layout.c +++ b/layout.c @@ -229,3 +229,17 @@ return ret; } + +void report_layout(const struct flashrom_layout *const l) +{ + unsigned int i; + + if (!l) + return; + + msg_gdbg("Gathered %zu layout entries:\n", l->num_entries); + for (i = 0; i < l->num_entries; ++i) { + msg_gdbg("%08"PRIx32":%08"PRIx32" %s\n", + l->entries[i].start, l->entries[i].end, l->entries[i].name); + } +} diff --git a/layout.h b/layout.h index eb54a4f..61311bc 100644 --- a/layout.h +++ b/layout.h @@ -59,4 +59,6 @@ int process_include_args(struct flashrom_layout *); +void report_layout(const struct flashrom_layout *); + #endif /* !__LAYOUT_H__ */ -- To view, visit https://review.coreboot.org/c/flashrom/+/31012 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I7678ba5138f0d722ee44747fe123f192abdd0ffd Gerrit-Change-Number: 31012 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

2 weeks, 1 day

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Change in flashrom[master]: sb600spi -> fchspi: Rename AMD SPI programmer

by Edward O'Callaghan (Code Review)

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/36434 ) Change subject: sb600spi -> fchspi: Rename AMD SPI programmer ...................................................................... sb600spi -> fchspi: Rename AMD SPI programmer The AMD FCH controller has two main SPI ip core variants, the so-called 'sb600' variant and the newer 'spi100' variant. The sb600spi.c driver supports both variants and so its name isn't very general. Here we rename it to be more general. Change-Id: Iad92fb224954d66968e7aeb75cb515f075a26ac8 Signed-off-by: Edward O'Callaghan <quasisec(a)chromium.org> --- M Makefile M chipset_enable.c R fchspi.c M meson.build M programmer.h 5 files changed, 11 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/34/36434/1 diff --git a/Makefile b/Makefile index f0a1b61..143a8c1 100644 --- a/Makefile +++ b/Makefile @@ -767,7 +767,7 @@ FEATURE_CFLAGS += -D'CONFIG_INTERNAL=1' PROGRAMMER_OBJS += processor_enable.o chipset_enable.o board_enable.o cbtable.o internal.o ifeq ($(ARCH), x86) -PROGRAMMER_OBJS += it87spi.o it85spi.o sb600spi.o amd_imc.o wbsio_spi.o mcp6x_spi.o +PROGRAMMER_OBJS += it87spi.o it85spi.o fchspi.o amd_imc.o wbsio_spi.o mcp6x_spi.o PROGRAMMER_OBJS += ichspi.o dmi.o ifeq ($(CONFIG_INTERNAL_DMI), yes) FEATURE_CFLAGS += -D'CONFIG_INTERNAL_DMI=1' diff --git a/chipset_enable.c b/chipset_enable.c index b55852c..e57a18e 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -1297,7 +1297,7 @@ return enable_flash_amd_via(dev, name, 0xE0); } -static int enable_flash_sb600(struct pci_dev *dev, const char *name) +static int enable_flash_fch(struct pci_dev *dev, const char *name) { uint32_t prot; uint8_t reg; @@ -1330,7 +1330,7 @@ internal_buses_supported &= BUS_LPC | BUS_FWH; - ret = sb600_probe_spi(dev); + ret = fch_probe_spi(dev); /* Read ROM strap override register. */ OUTB(0x8f, 0xcd6); @@ -1685,16 +1685,16 @@ const struct penable chipset_enables[] = { #if defined(__i386__) || defined(__x86_64__) {0x1002, 0x4377, B_PFL, OK, "ATI", "SB400", enable_flash_sb400}, - {0x1002, 0x438d, B_FLS, OK, "AMD", "SB600", enable_flash_sb600}, - {0x1002, 0x439d, B_FLS, OK, "AMD", "SB7x0/SB8x0/SB9x0", enable_flash_sb600}, + {0x1002, 0x438d, B_FLS, OK, "AMD", "SB600", enable_flash_fch}, + {0x1002, 0x439d, B_FLS, OK, "AMD", "SB7x0/SB8x0/SB9x0", enable_flash_fch}, {0x100b, 0x0510, B_PFL, NT, "AMD", "SC1100", enable_flash_sc1100}, {0x1022, 0x2080, B_PFL, OK, "AMD", "CS5536", enable_flash_cs5536}, {0x1022, 0x2090, B_PFL, OK, "AMD", "CS5536", enable_flash_cs5536}, {0x1022, 0x3000, B_PFL, OK, "AMD", "Elan SC520", get_flashbase_sc520}, {0x1022, 0x7440, B_PFL, OK, "AMD", "AMD-768", enable_flash_amd_768_8111}, {0x1022, 0x7468, B_PFL, OK, "AMD", "AMD-8111", enable_flash_amd_768_8111}, - {0x1022, 0x780e, B_FLS, OK, "AMD", "FCH", enable_flash_sb600}, - {0x1022, 0x790e, B_FLS, OK, "AMD", "FP4", enable_flash_sb600}, + {0x1022, 0x780e, B_FLS, OK, "AMD", "FCH", enable_flash_fch}, + {0x1022, 0x790e, B_FLS, OK, "AMD", "FP4", enable_flash_fch}, {0x1039, 0x0406, B_PFL, NT, "SiS", "501/5101/5501", enable_flash_sis501}, {0x1039, 0x0496, B_PFL, NT, "SiS", "85C496+497", enable_flash_sis85c496}, {0x1039, 0x0530, B_PFL, OK, "SiS", "530", enable_flash_sis530}, diff --git a/sb600spi.c b/fchspi.c similarity index 99% rename from sb600spi.c rename to fchspi.c index 7bdd11f..e0eab07 100644 --- a/sb600spi.c +++ b/fchspi.c @@ -579,7 +579,7 @@ return amd_imc_shutdown(dev); } -int sb600_probe_spi(struct pci_dev *dev) +int fch_probe_spi(struct pci_dev *dev) { struct pci_dev *smbus_dev; uint32_t tmp; diff --git a/meson.build b/meson.build index d1f663f..d4bbff7 100644 --- a/meson.build +++ b/meson.build @@ -182,7 +182,7 @@ srcs += 'it85spi.c' srcs += 'it87spi.c' srcs += 'mcp6x_spi.c' - srcs += 'sb600spi.c' + srcs += 'fchspi.c' srcs += 'wbsio_spi.c' endif config_bitbang_spi = true diff --git a/programmer.h b/programmer.h index e42c6bb..e2cadd9 100644 --- a/programmer.h +++ b/programmer.h @@ -657,8 +657,8 @@ /* mcp6x_spi.c */ int mcp6x_spi_init(int want_spi); -/* sb600spi.c */ -int sb600_probe_spi(struct pci_dev *dev); +/* fchspi.c */ +int fch_probe_spi(struct pci_dev *dev); /* wbsio_spi.c */ int wbsio_check_for_spi(void); -- To view, visit https://review.coreboot.org/c/flashrom/+/36434 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Iad92fb224954d66968e7aeb75cb515f075a26ac8 Gerrit-Change-Number: 36434 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

2 weeks, 6 days

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Change in flashrom[master]: sb600spi.c: Remove 'amd_gen' out of global state.

by Edward O'Callaghan (Code Review)

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/36432 ) Change subject: sb600spi.c: Remove 'amd_gen' out of global state. ...................................................................... sb600spi.c: Remove 'amd_gen' out of global state. Have 'determine_generation()' explicitly return 'amd_gen' and then pass the state into what requires it. Thus making the code more pure, easier to read and more unit-testable. Change-Id: I99fbad9486123c6b921eab83756de54a53ddfa7a Signed-off-by: Edward O'Callaghan <quasisec(a)chromium.org> --- M sb600spi.c 1 file changed, 12 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/32/36432/1 diff --git a/sb600spi.c b/sb600spi.c index 8daaf03..23b36ee 100644 --- a/sb600spi.c +++ b/sb600spi.c @@ -51,7 +51,6 @@ CHIPSET_YANGTZE, CHIPSET_PROMONTORY, }; -static enum amd_chipset amd_gen = CHIPSET_AMD_UNKNOWN; #define FIFO_SIZE_OLD 8 #define FIFO_SIZE_YANGTZE 71 @@ -110,7 +109,7 @@ /* Determine the chipset's version and identify the respective SMBUS device. */ static int determine_generation(struct pci_dev *dev) { - amd_gen = CHIPSET_AMD_UNKNOWN; + enum amd_chipset amd_gen = CHIPSET_AMD_UNKNOWN; msg_pdbg2("Trying to determine the generation of the SPI interface... "); if (dev->device_id == 0x438d) { amd_gen = CHIPSET_SB6XX; @@ -173,11 +172,10 @@ "Please report this to flashrom(a)flashrom.org and include this log and\n" "the output of lspci -nnvx, thanks!\n", __func__, dev->vendor_id, dev->device_id); - if (amd_gen == CHIPSET_AMD_UNKNOWN) { + if (amd_gen == CHIPSET_AMD_UNKNOWN) msg_perr("Could not determine chipset generation."); - return -1; - } - return 0; + + return amd_gen; } static void reset_internal_fifo_pointer(void) @@ -373,7 +371,7 @@ { "800 kHz", 0x07 }, }; -static int set_speed(struct pci_dev *dev, const struct spispeed *spispeed) +static int set_speed(struct pci_dev *dev, enum amd_chipset amd_gen, const struct spispeed *spispeed) { bool success = false; uint8_t speed = spispeed->speed; @@ -407,7 +405,7 @@ return 0; } -static int handle_speed(struct pci_dev *dev) +static int handle_speed(struct pci_dev *dev, enum amd_chipset amd_gen) { uint32_t tmp; uint8_t spispeed_idx = 3; /* Default to 16.5 MHz */ @@ -496,10 +494,10 @@ tmp = (mmio_readb(sb600_spibar + 0xd) >> 4) & 0x3; msg_pdbg("NormSpeed is %s\n", spispeeds[tmp].name); } - return set_speed(dev, &spispeeds[spispeed_idx]); + return set_speed(dev, amd_gen, &spispeeds[spispeed_idx]); } -static int handle_imc(struct pci_dev *dev) +static int handle_imc(struct pci_dev *dev, enum amd_chipset amd_gen) { /* Handle IMC everywhere but sb600 which does not have one. */ if (amd_gen == CHIPSET_SB6XX) @@ -592,7 +590,8 @@ */ sb600_spibar += tmp & 0xfff; - if (determine_generation(dev) < 0) + int amd_gen = determine_generation(dev); + if (amd_gen < 0) return ERROR_NONFATAL; /* How to read the following table and similar ones in this file: @@ -725,10 +724,10 @@ return 0; } - if (handle_speed(dev) != 0) + if (handle_speed(dev, amd_gen) != 0) return ERROR_FATAL; - if (handle_imc(dev) != 0) + if (handle_imc(dev, amd_gen) != 0) return ERROR_FATAL; /* Starting with Yangtze the SPI controller got a different interface with a much bigger buffer. */ -- To view, visit https://review.coreboot.org/c/flashrom/+/36432 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I99fbad9486123c6b921eab83756de54a53ddfa7a Gerrit-Change-Number: 36432 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

2 weeks, 6 days

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Change in flashrom[master]: sb600spi.c: Improve IMC runtime detection in handle_imc()

by Edward O'Callaghan (Code Review)

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/36424 ) Change subject: sb600spi.c: Improve IMC runtime detection in handle_imc() ...................................................................... sb600spi.c: Improve IMC runtime detection in handle_imc() The IMC detection in sb600spi is very rudimentary and incomplete. This expands it so that it can actually detect not only whether an IMC is in the system, but whether it's active or not. This is based off ChromiumOS's fork of flashrom where the solution looks to be originally authored by Martin Roth in b/62141938. Change-Id: I13fb2300475c06aad09a4f0e8cd032e212556b14 Signed-off-by: Edward O'Callaghan <quasisec(a)chromium.org> --- M sb600spi.c 1 file changed, 34 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/24/36424/1 diff --git a/sb600spi.c b/sb600spi.c index c89d5a9..3c83b7b 100644 --- a/sb600spi.c +++ b/sb600spi.c @@ -55,6 +55,15 @@ #define FIFO_SIZE_OLD 8 #define FIFO_SIZE_YANGTZE 71 +#define PM_INDEX 0xCD6 +#define PM_DATA 0xCD7 +#define ISA_CONTROL 0x04 +#define MMIO_EN 0x02 +#define ACPI_MMIO_BASE 0xFED80000 +#define MISC_BASE 0xE00 +#define STRAP_STATUS 0x80 +#define EC_ENABLE_STRAP 0x04 + static int sb600_spi_send_command(struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); static int spi100_spi_send_command(struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, @@ -80,6 +89,12 @@ .write_aai = default_spi_write_aai, }; +static uint8_t pm_ioread(uint8_t addr) +{ + OUTB(addr, PM_INDEX); + return INB(PM_DATA); +} + static int find_smbus_dev(uint16_t vendor, uint16_t device) { struct pci_dev *smbus_dev = pci_dev_find(vendor, device); @@ -522,6 +537,25 @@ return 0; } + /* On Yangtze and newer chips, check the EcEnableStrap bit */ + if ((amd_gen >= CHIPSET_YANGTZE) && (pm_ioread(ISA_CONTROL) & MMIO_EN )) { + uint8_t *AcpiMMIO = rphysmap("AMD ACPI registers", ACPI_MMIO_BASE & 0xfffff000, 0x1000); + if (AcpiMMIO != ERROR_PTR) { + AcpiMMIO += MISC_BASE + STRAP_STATUS; + uint32_t straps = mmio_readl(AcpiMMIO); + if ((straps & EC_ENABLE_STRAP) == 0){ + msg_pinfo("IMC is not active.\n"); + return 0; + } else { + msg_pinfo("IMC IS active! Straps: %08x (%p)\n", straps, (void *)AcpiMMIO); + msg_pinfo("StrapOverride: %08x\n", mmio_readl(AcpiMMIO + 4)); + } + + } else { + msg_pinfo("Error reading AMD ACPI registers.\n"); + } + } + if (!amd_imc_force) programmer_may_write = 0; msg_pinfo("Writes have been disabled for safety reasons because the presence of the IMC\n" -- To view, visit https://review.coreboot.org/c/flashrom/+/36424 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I13fb2300475c06aad09a4f0e8cd032e212556b14 Gerrit-Change-Number: 36424 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

2 weeks, 6 days

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Change in flashrom[master]: [WIP] Add .clang-format to help with patch formatting

by David Hendricks (Code Review)

Hello Vadim Bendebury, I'd like you to do a code review. Please visit https://review.coreboot.org/c/flashrom/+/38673 to review the following change. Change subject: [WIP] Add .clang-format to help with patch formatting ...................................................................... [WIP] Add .clang-format to help with patch formatting This is based on CB:38208 by Vadim, but with a few added changes. Here is the original commit message. This is a copy from the coreboot tree, could be tweaked to better match the flashrom tree if there are any differences. Once this file is in place a script could be deployed which would format only new/changed lines in git patches. Change-Id: I1fe22809c4a2d73fa02f4de55290d990a9750b86 Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Signed-off-by: David Hendricks <david.hendricks(a)gmail.com> --- A .clang-format 1 file changed, 21 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/73/38673/1 diff --git a/.clang-format b/.clang-format new file mode 100644 index 0000000..45c116b --- /dev/null +++ b/.clang-format @@ -0,0 +1,21 @@ +BasedOnStyle: LLVM +Language: Cpp +IndentWidth: 8 +UseTab: Always +BreakBeforeBraces: Linux +AllowShortIfStatementsOnASingleLine: false +IndentCaseLabels: false +SortIncludes: false +ContinuationIndentWidth: 8 +ColumnLimit: 112 +AlwaysBreakBeforeMultilineStrings: true +AllowShortLoopsOnASingleLine: false +AllowShortFunctionsOnASingleLine: false +AlignEscapedNewlinesLeft: false +AlignTrailingComments: true +AllowAllParametersOfDeclarationOnNextLine: false +AlignAfterOpenBracket: true +SpaceAfterCStyleCast: false +MaxEmptyLinesToKeep: 2 +BreakBeforeBinaryOperators: NonAssignment +BreakStringLiterals: false -- To view, visit https://review.coreboot.org/c/flashrom/+/38673 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I1fe22809c4a2d73fa02f4de55290d990a9750b86 Gerrit-Change-Number: 38673 Gerrit-PatchSet: 1 Gerrit-Owner: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Vadim Bendebury <vbendeb(a)chromium.org> Gerrit-MessageType: newchange

3 weeks

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Change in flashrom[master]: Fix a handful of compiler warnings

by Ryan O'Leary (Code Review)

Ryan O'Leary has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/36946 ) Change subject: Fix a handful of compiler warnings ...................................................................... Fix a handful of compiler warnings These warnings (which I believe are not enabled by default) were generated by -Wformat-security and -Wenum-conversion. Change-Id: I3d01f4ff620f4c4111dd675d49ce3254f2360b29 Signed-off-by: Ryan O'Leary <ryanoleary(a)google.com> --- M libflashrom.c M print.c M programmer.h 3 files changed, 7 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/46/36946/1 diff --git a/libflashrom.c b/libflashrom.c index 0dec22e..b15b5f6 100644 --- a/libflashrom.c +++ b/libflashrom.c @@ -188,7 +188,8 @@ for (; i < boards_known_size; ++i) { supported_boards[i].vendor = binfo[i].vendor; supported_boards[i].name = binfo[i].name; - supported_boards[i].working = binfo[i].working; + supported_boards[i].working = + (enum flashrom_test_state)binfo[i].working; } } else { msg_gerr("Memory allocation error!\n"); @@ -226,8 +227,9 @@ supported_chipsets[i].chipset = chipset[i].device_name; supported_chipsets[i].vendor_id = chipset[i].vendor_id; supported_chipsets[i].chipset_id = chipset[i].device_id; - supported_chipsets[i].status = chipset[i].status; - } + supported_chipsets[i].status = + (enum flashrom_test_state)chipset[i].status; + } } else { msg_gerr("Memory allocation error!\n"); } diff --git a/print.c b/print.c index 596fc53..173c7da 100644 --- a/print.c +++ b/print.c @@ -401,7 +401,7 @@ for (i = 0; i < maxboardlen - strlen(b->name); i++) msg_ginfo(" "); - msg_pinfo(test_state_to_text(b->working)); + msg_pinfo("%s", test_state_to_text(b->working)); for (e = board_matches; e->vendor_name != NULL; e++) { if (strcmp(e->vendor_name, b->vendor) diff --git a/programmer.h b/programmer.h index 5a21b2e..96add05 100644 --- a/programmer.h +++ b/programmer.h @@ -307,7 +307,7 @@ /* cbtable.c */ int cb_parse_table(const char **vendor, const char **model); -int cb_check_image(const uint8_t *bios, unsigned int size); +int cb_check_image(const uint8_t *image, unsigned int size); /* dmi.c */ #if defined(__i386__) || defined(__x86_64__) -- To view, visit https://review.coreboot.org/c/flashrom/+/36946 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I3d01f4ff620f4c4111dd675d49ce3254f2360b29 Gerrit-Change-Number: 36946 Gerrit-PatchSet: 1 Gerrit-Owner: Ryan O'Leary <ryanoleary(a)google.com> Gerrit-MessageType: newchange

1 month, 2 weeks

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Change in flashrom[master]: Add support for Fudan SPI flash chips

by Angel Pons (Code Review)

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/38919 ) Change subject: Add support for Fudan SPI flash chips ...................................................................... Add support for Fudan SPI flash chips This includes the following chips: - FM25F005 - FM25F01 - FM25F02 and FM25F02A - FM25F04 and FM25F04A - FM25Q08 - FM25Q16 - FM25Q32 Change-Id: I11dd82f8c4003cc6f974981cb92dca084f1df1f0 Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> --- M flashchips.c M flashchips.h 2 files changed, 282 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/19/38919/1 diff --git a/flashchips.c b/flashchips.c index 58dd4f3..7ba3840 100644 --- a/flashchips.c +++ b/flashchips.c @@ -5691,6 +5691,278 @@ }, { + .vendor = "Fudan", + .name = "FM25F005", + .bustype = BUS_SPI, + .manufacture_id = FUDAN_ID_NOPREFIX, + .model_id = FUDAN_FM25F005, + .total_size = 64, + .page_size = 256, + /* OTP: 256B total; enter 0x3A */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = { + { + .eraseblocks = { {4 * 1024, 16} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 2} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 1} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {64 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {64 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_bp2_tb_bpl, + .unlock = spi_disable_blockprotect_bp2_srwd, + .write = spi_chip_write_256, + .read = spi_chip_read, /* Fast read (0x0B), dual I/O (0x3B) supported */ + .voltage = {2700, 3600}, /* 2.3-2.7V acceptable results in lower performance */ + }, + + { + .vendor = "Fudan", + .name = "FM25F01", + .bustype = BUS_SPI, + .manufacture_id = FUDAN_ID_NOPREFIX, + .model_id = FUDAN_FM25F01, + .total_size = 128, + .page_size = 256, + /* OTP: 256B total; enter 0x3A */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = { + { + .eraseblocks = { {4 * 1024, 32} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 4} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 2} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {128 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {128 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_bp2_tb_bpl, + .unlock = spi_disable_blockprotect_bp2_srwd, + .write = spi_chip_write_256, + .read = spi_chip_read, /* Fast read (0x0B), dual I/O (0x3B) supported */ + .voltage = {2700, 3600}, /* 2.3-2.7V acceptable results in lower performance */ + }, + + { + .vendor = "Fudan", + .name = "FM25F02(A)", + .bustype = BUS_SPI, + .manufacture_id = FUDAN_ID_NOPREFIX, + .model_id = FUDAN_FM25F02, + .total_size = 256, + .page_size = 256, + /* OTP: 256B total; enter 0x3A, (A version only:) read ID 0x4B */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = { + { + .eraseblocks = { {4 * 1024, 64} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 8} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 4} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {1024 * 256, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {1024 * 256, 1} }, + .block_erase = spi_block_erase_c7, + }, + }, + .printlock = spi_prettyprint_status_register_bp2_tb_bpl, + .unlock = spi_disable_blockprotect_bp2_srwd, + .write = spi_chip_write_256, + .read = spi_chip_read, /* Fast read (0x0B), dual I/O (0x3B) supported */ + .voltage = {2700, 3600}, /* 2.3-2.7V acceptable results in lower performance */ + }, + + { + .vendor = "Fudan", + .name = "FM25F04(A)", + .bustype = BUS_SPI, + .manufacture_id = FUDAN_ID_NOPREFIX, + .model_id = FUDAN_FM25F04, + .total_size = 512, + .page_size = 256, + /* OTP: 256B total; enter 0x3A, (A version only:) read ID 0x4B */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = { + { + .eraseblocks = { {4 * 1024, 128} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 16} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 8} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {1024 * 512, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {1024 * 512, 1} }, + .block_erase = spi_block_erase_c7, + }, + }, + .printlock = spi_prettyprint_status_register_bp2_tb_bpl, + .unlock = spi_disable_blockprotect_bp2_srwd, + .write = spi_chip_write_256, + .read = spi_chip_read, /* Fast read (0x0B), dual I/O (0x3B) supported */ + .voltage = {2700, 3600}, + }, + + { + .vendor = "Fudan", + .name = "FM25Q08", + .bustype = BUS_SPI, + .manufacture_id = FUDAN_ID_NOPREFIX, + .model_id = FUDAN_FM25Q08, + .total_size = 1024, + .page_size = 256, + /* supports SFDP */ + /* OTP: 1024B total; read 0x48; write 0x42, erase 0x44, read ID 0x4B */ + /* QPI enable 0x38, disable 0xFF */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = { + { + .eraseblocks = { {4 * 1024, 256} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 32} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 16} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + }, + }, + .printlock = spi_prettyprint_status_register_bp2_tb_bpl, /* bit6 selects size of protected blocks; TODO: SR2 */ + .unlock = spi_disable_blockprotect_bp2_srwd, + .write = spi_chip_write_256, + .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ + .voltage = {2700, 3600}, + }, + + { + .vendor = "Fudan", + .name = "FM25Q16", + .bustype = BUS_SPI, + .manufacture_id = FUDAN_ID_NOPREFIX, + .model_id = FUDAN_FM25Q16, + .total_size = 2048, + .page_size = 256, + /* supports SFDP */ + /* OTP: 1024B total; read 0x48; write 0x42, erase 0x44, read ID 0x4B */ + /* QPI enable 0x38, disable 0xFF */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = { + { + .eraseblocks = { {4 * 1024, 512} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 64} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 32} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {2 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {2 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_bp2_tb_bpl, /* bit6 selects size of protected blocks; TODO: SR2 */ + .unlock = spi_disable_blockprotect_bp2_srwd, + .write = spi_chip_write_256, + .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ + .voltage = {2700, 3600}, + }, + + { + .vendor = "Fudan", + .name = "FM25Q32", + .bustype = BUS_SPI, + .manufacture_id = FUDAN_ID_NOPREFIX, + .model_id = FUDAN_FM25Q32, + .total_size = 4096, + .page_size = 256, + /* supports SFDP */ + /* OTP: 1024B total; read 0x48; write 0x42, erase 0x44, read ID 0x4B */ + /* QPI enable 0x38, disable 0xFF */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = { + { + .eraseblocks = { {4 * 1024, 1024} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 128} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 64} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {4 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {4 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + }, + }, + .printlock = spi_prettyprint_status_register_bp2_tb_bpl, /* bit6 selects size of protected blocks; TODO: SR2 */ + .unlock = spi_disable_blockprotect_bp2_srwd, + .write = spi_chip_write_256, + .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ + .voltage = {2700, 3600}, + }, + + { .vendor = "Fujitsu", .name = "MBM29F004BC", .bustype = BUS_PARALLEL, diff --git a/flashchips.h b/flashchips.h index 14ab6de..bcd612c 100644 --- a/flashchips.h +++ b/flashchips.h @@ -329,6 +329,16 @@ #define FIDELIX_FM25Q32 0x3216 #define FIDELIX_FM25Q64 0x3217 +#define FUDAN_ID 0x7F7F7F7F7F7F7F4A /* Shanghai Fudan Microelectronics resides in bank 8 */ +#define FUDAN_ID_NOPREFIX 0x04 /* Fudan, missing 0x7F prefix */ +#define FUDAN_FM25F005 0x3110 +#define FUDAN_FM25F01 0x3111 +#define FUDAN_FM25F02 0x3112 /* Same as FM25F02A */ +#define FUDAN_FM25F04 0x3113 /* Same as FM25F04A */ +#define FUDAN_FM25Q08 0x4014 +#define FUDAN_FM25Q16 0x4015 +#define FUDAN_FM25Q32 0x4016 + #define FUJITSU_ID 0x04 /* Fujitsu */ #define FUJITSU_MBM29DL400BC 0x0F #define FUJITSU_MBM29DL400TC 0x0C -- To view, visit https://review.coreboot.org/c/flashrom/+/38919 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I11dd82f8c4003cc6f974981cb92dca084f1df1f0 Gerrit-Change-Number: 38919 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

1 month, 3 weeks

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Change in flashrom[master]: 82802ab.c: Remove duplicated check

by Angel Pons (Code Review)

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/38661 ) Change subject: 82802ab.c: Remove duplicated check ...................................................................... 82802ab.c: Remove duplicated check Change-Id: I5d511d7ec254bdbd9926e6d8efc308fb2339cb81 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M 82802ab.c 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/61/38661/1 diff --git a/82802ab.c b/82802ab.c index a44a66e..a13a4a0 100644 --- a/82802ab.c +++ b/82802ab.c @@ -89,9 +89,9 @@ chipaddr bios = flash->virtual_memory; chip_writeb(flash, 0x70, bios); - if ((chip_readb(flash, bios) & 0x80) == 0) { /* it's busy */ - while ((chip_readb(flash, bios) & 0x80) == 0) ; - } + + while ((chip_readb(flash, bios) & 0x80) == 0) /* it's busy */ + ; status = chip_readb(flash, bios); -- To view, visit https://review.coreboot.org/c/flashrom/+/38661 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I5d511d7ec254bdbd9926e6d8efc308fb2339cb81 Gerrit-Change-Number: 38661 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

2 months

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Change in flashrom[master]: chipset_enable.c: Add CMP-H IDs

by Gaggery Tsai (Code Review)

Gaggery Tsai has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/37677 ) Change subject: chipset_enable.c: Add CMP-H IDs ...................................................................... chipset_enable.c: Add CMP-H IDs This patch adds CMP-H support. They are HM470, WM490, QM480, W480, H470, Z490 and Q470. TEST=build flashrom and run on CML-S with CMP-H flashrom -p internal -w ./coreboot.rom reboot and check the code is flashed correctly Signed-off-by: Gaggery Tsai <gaggery.tsai(a)intel.com> Change-Id: Ic7f04fc5cbe3422cbd219c46586c32fc847c921f --- M chipset_enable.c 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/77/37677/1 diff --git a/chipset_enable.c b/chipset_enable.c index b55852c..62a19af 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -2046,6 +2046,13 @@ {0x8086, 0xa30c, B_S, NT, "Intel", "QM370", enable_flash_pch300}, {0x8086, 0xa30d, B_S, NT, "Intel", "HM370", enable_flash_pch300}, {0x8086, 0xa30e, B_S, DEP, "Intel", "CM246", enable_flash_pch300}, + {0x8086, 0x068d, B_S, NT, "Intel", "HM470", enable_flash_pch300}, + {0x8086, 0x068e, B_S, NT, "Intel", "WM490", enable_flash_pch300}, + {0x8086, 0x068c, B_S, NT, "Intel", "QM480", enable_flash_pch300}, + {0x8086, 0x0697, B_S, NT, "Intel", "W480", enable_flash_pch300}, + {0x8086, 0x0684, B_S, NT, "Intel", "H470", enable_flash_pch300}, + {0x8086, 0x0685, B_S, NT, "Intel", "Z490", enable_flash_pch300}, + {0x8086, 0x0687, B_S, NT, "Intel", "Q470", enable_flash_pch300}, #endif {0}, }; -- To view, visit https://review.coreboot.org/c/flashrom/+/37677 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ic7f04fc5cbe3422cbd219c46586c32fc847c921f Gerrit-Change-Number: 37677 Gerrit-PatchSet: 1 Gerrit-Owner: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-MessageType: newchange

2 months, 1 week

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flashrom-gerrit February 2020