April 2020 - flashrom-gerrit - mail.coreboot.org

Change in flashrom[master]: spi: add support for Winbond W25Q64JW
by Hung-Te Lin (Code Review) 09 Apr '20

09 Apr '20

Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/40275 ) Change subject: spi: add support for Winbond W25Q64JW ...................................................................... Patch Set 3: Code-Review+1 (1 comment) https://review.coreboot.org/c/flashrom/+/40275/3/flashchips.c File flashchips.c: https://review.coreboot.org/c/flashrom/+/40275/3/flashchips.c@17133 PS3, Line 17133: ZPIM I think you can't tell if this is ZPIM or SSIG from model id; so maybe just leave it as W25Q64JW? -- To view, visit https://review.coreboot.org/c/flashrom/+/40275 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I8637129421a3b0f96bd8dffa4f50783ea6931967 Gerrit-Change-Number: 40275 Gerrit-PatchSet: 3 Gerrit-Owner: Scott Chao <scott.chao(a)bitland.corp-partner.google.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Peichao Li <peichao.wang(a)bitland.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Casper Chang <casper.chang(a)bitland.corp-partner.google.com> Gerrit-CC: Paul Ma <magf(a)bitland.com.cn> Gerrit-Comment-Date: Thu, 09 Apr 2020 04:07:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in flashrom[master]: spi: add support for Winbond W25Q64JW
by Hung-Te Lin (Code Review) 09 Apr '20

09 Apr '20

Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/40275 ) Change subject: spi: add support for Winbond W25Q64JW ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/flashrom/+/40275 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I8637129421a3b0f96bd8dffa4f50783ea6931967 Gerrit-Change-Number: 40275 Gerrit-PatchSet: 3 Gerrit-Owner: Scott Chao <scott.chao(a)bitland.corp-partner.google.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Peichao Li <peichao.wang(a)bitland.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Casper Chang <casper.chang(a)bitland.corp-partner.google.com> Gerrit-CC: Paul Ma <magf(a)bitland.com.cn> Gerrit-Comment-Date: Thu, 09 Apr 2020 04:05:06 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in flashrom[master]: spi: add support for Winbond W25Q64JW
by Scott Chao (Code Review) 09 Apr '20

09 Apr '20

Hello Hung-Te Lin, build bot (Jenkins), Martin Roth, Patrick Georgi, Edward O'Callaghan, Peichao Li, Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/40275 to look at the new patch set (#2). Change subject: spi: add support for Winbond W25Q64JW ...................................................................... spi: add support for Winbond W25Q64JW BUG=b:153515968 BRANCH=kukui TEST=flash coreboot on kakadu and get successful result. Change-Id: I8637129421a3b0f96bd8dffa4f50783ea6931967 Signed-off-by: Scott Chao <scott.chao(a)bitland.corp-partner.google.com> --- M flashchips.c M flashchips.h 2 files changed, 86 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/75/40275/2 -- To view, visit https://review.coreboot.org/c/flashrom/+/40275 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I8637129421a3b0f96bd8dffa4f50783ea6931967 Gerrit-Change-Number: 40275 Gerrit-PatchSet: 2 Gerrit-Owner: Scott Chao <scott.chao(a)bitland.corp-partner.google.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Peichao Li <peichao.wang(a)bitland.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Casper Chang <casper.chang(a)bitland.corp-partner.google.com> Gerrit-CC: Paul Ma <magf(a)bitland.com.cn> Gerrit-MessageType: newpatchset

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Change in flashrom[master]: spi: add support for Winbond W25Q64JW
by Hung-Te Lin (Code Review) 09 Apr '20

09 Apr '20

Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/40275 ) Change subject: spi: add support for Winbond W25Q64JW ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/flashrom/+/40275 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I8637129421a3b0f96bd8dffa4f50783ea6931967 Gerrit-Change-Number: 40275 Gerrit-PatchSet: 1 Gerrit-Owner: Scott Chao <scott.chao(a)bitland.corp-partner.google.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Peichao Li <peichao.wang(a)bitland.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Casper Chang <casper.chang(a)bitland.corp-partner.google.com> Gerrit-CC: Paul Ma <magf(a)bitland.com.cn> Gerrit-Comment-Date: Thu, 09 Apr 2020 01:08:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in flashrom[master]: spi: add support for Winbond W25Q64JW
by Edward O'Callaghan (Code Review) 09 Apr '20

09 Apr '20

Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/40275 ) Change subject: spi: add support for Winbond W25Q64JW ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/flashrom/+/40275 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I8637129421a3b0f96bd8dffa4f50783ea6931967 Gerrit-Change-Number: 40275 Gerrit-PatchSet: 1 Gerrit-Owner: Scott Chao <scott.chao(a)bitland.corp-partner.google.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Peichao Li <peichao.wang(a)bitland.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Casper Chang <casper.chang(a)bitland.corp-partner.google.com> Gerrit-CC: Paul Ma <magf(a)bitland.com.cn> Gerrit-Comment-Date: Thu, 09 Apr 2020 00:35:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in flashrom[master]: spi: add support for Winbond W25Q64JW
by Peichao Li (Code Review) 09 Apr '20

09 Apr '20

Peichao Li has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/40275 ) Change subject: spi: add support for Winbond W25Q64JW ...................................................................... Patch Set 1: Need to fix conflict. -- To view, visit https://review.coreboot.org/c/flashrom/+/40275 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I8637129421a3b0f96bd8dffa4f50783ea6931967 Gerrit-Change-Number: 40275 Gerrit-PatchSet: 1 Gerrit-Owner: Scott Chao <scott.chao(a)bitland.corp-partner.google.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Peichao Li <peichao.wang(a)bitland.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Casper Chang <casper.chang(a)bitland.corp-partner.google.com> Gerrit-CC: Paul Ma <magf(a)bitland.com.cn> Gerrit-Comment-Date: Thu, 09 Apr 2020 00:22:52 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in flashrom[master]: flashchips: add W25M512JV
by Joel Stanley (Code Review) 08 Apr '20

08 Apr '20

Joel Stanley has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/34595 ) Change subject: flashchips: add W25M512JV ...................................................................... flashchips: add W25M512JV https://www.winbond.com/resource-files/w25m512jv%20revd%2009052017.pdf Change-Id: I8d16f0918785795cc49500435a03641b87d706e9 Signed-off-by: Joel Stanley <joel(a)jms.id.au> --- M flashchips.c M flashchips.h 2 files changed, 20 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/95/34595/1 diff --git a/flashchips.c b/flashchips.c index 166af6a..304ebe7 100644 --- a/flashchips.c +++ b/flashchips.c @@ -15902,6 +15902,25 @@ { .vendor = "Winbond", + .name = "W25Q512JV", + .bustype = BUS_SPI, + .manufacture_id = WINBOND_NEX_ID, + .model_id = WINBOND_NEX_W25Q512JV, + .total_size = 64 * 1024, + .page_size = 1024, + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA, + .tested = TEST_OK_PREW, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .printlock = spi_prettyprint_status_register_plain, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {2700, 3600}, + }, + + { + .vendor = "Winbond", .name = "W25Q256JV_M", .bustype = BUS_SPI, .manufacture_id = WINBOND_NEX_ID, diff --git a/flashchips.h b/flashchips.h index 006b95e..c606161 100644 --- a/flashchips.h +++ b/flashchips.h @@ -921,6 +921,7 @@ #define WINBOND_NEX_W25Q64_V 0x4017 /* W25Q64BV, W25Q64CV; W25Q64FV in SPI mode (default) */ #define WINBOND_NEX_W25Q128_V 0x4018 /* W25Q128BV; W25Q128FV in SPI mode (default) */ #define WINBOND_NEX_W25Q256_V 0x4019 /* W25Q256FV or W25Q256JV_Q (QE=1) */ +#define WINBOND_NEX_W25Q512JV 0x4020 /* W25Q512JV */ #define WINBOND_NEX_W25Q20_W 0x5012 /* W25Q20BW */ #define WINBOND_NEX_W25Q40BW 0x5013 /* W25Q40BW */ #define WINBOND_NEX_W25Q80BW 0x5014 /* W25Q80BW */ -- To view, visit https://review.coreboot.org/c/flashrom/+/34595 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I8d16f0918785795cc49500435a03641b87d706e9 Gerrit-Change-Number: 34595 Gerrit-PatchSet: 1 Gerrit-Owner: Joel Stanley Gerrit-MessageType: newchange

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Change in flashrom[master]: ft2232_spi.c - change the chunksize from 256 to 270 as this value mus...
by el-coder-sb (Code Review) 08 Apr '20

08 Apr '20

el-coder-sb has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/39632 ) Change subject: ft2232_spi.c - change the chunksize from 256 to 270 as this value must contain the address and cmd bytes to really make use of 256 raw data page write. ...................................................................... ft2232_spi.c - change the chunksize from 256 to 270 as this value must contain the address and cmd bytes to really make use of 256 raw data page write. For details check: https://mail.coreboot.org/hyperkitty/list/flashrom@flashrom.org/message/W2H… Signed-off-by: Simon Buhrow <simon.buhrow(a)posteo.de> Change-Id: Iac067a23025e9df053ab9cd4e82a98de70046c18 --- M ft2232_spi.c 1 file changed, 417 insertions(+), 417 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/32/39632/1 diff --git a/ft2232_spi.c b/ft2232_spi.c index 1a5b2fe..62cfabe 100644 --- a/ft2232_spi.c +++ b/ft2232_spi.c @@ -29,60 +29,60 @@ /* This is not defined in libftdi.h <0.20 (c7e4c09e68cfa6f5e112334aa1b3bb23401c8dc7 to be exact). * Some tests indicate that his is the only change that it is needed to support the FT232H in flashrom. */ #if !defined(HAVE_FT232H) -#define TYPE_232H 6 +#define TYPE_232H 6 #endif /* Please keep sorted by vendor ID, then device ID. */ -#define FTDI_VID 0x0403 -#define FTDI_FT2232H_PID 0x6010 -#define FTDI_FT4232H_PID 0x6011 -#define FTDI_FT232H_PID 0x6014 -#define TIAO_TUMPA_PID 0x8a98 -#define TIAO_TUMPA_LITE_PID 0x8a99 -#define AMONTEC_JTAGKEY_PID 0xCFF8 +#define FTDI_VID 0x0403 +#define FTDI_FT2232H_PID 0x6010 +#define FTDI_FT4232H_PID 0x6011 +#define FTDI_FT232H_PID 0x6014 +#define TIAO_TUMPA_PID 0x8a98 +#define TIAO_TUMPA_LITE_PID 0x8a99 +#define AMONTEC_JTAGKEY_PID 0xCFF8 -#define GOEPEL_VID 0x096C -#define GOEPEL_PICOTAP_PID 0x1449 +#define GOEPEL_VID 0x096C +#define GOEPEL_PICOTAP_PID 0x1449 -#define FIC_VID 0x1457 -#define OPENMOKO_DBGBOARD_PID 0x5118 +#define FIC_VID 0x1457 +#define OPENMOKO_DBGBOARD_PID 0x5118 -#define OLIMEX_VID 0x15BA -#define OLIMEX_ARM_OCD_PID 0x0003 -#define OLIMEX_ARM_TINY_PID 0x0004 -#define OLIMEX_ARM_OCD_H_PID 0x002B -#define OLIMEX_ARM_TINY_H_PID 0x002A +#define OLIMEX_VID 0x15BA +#define OLIMEX_ARM_OCD_PID 0x0003 +#define OLIMEX_ARM_TINY_PID 0x0004 +#define OLIMEX_ARM_OCD_H_PID 0x002B +#define OLIMEX_ARM_TINY_H_PID 0x002A -#define GOOGLE_VID 0x18D1 -#define GOOGLE_SERVO_PID 0x5001 -#define GOOGLE_SERVO_V2_PID0 0x5002 -#define GOOGLE_SERVO_V2_PID1 0x5003 +#define GOOGLE_VID 0x18D1 +#define GOOGLE_SERVO_PID 0x5001 +#define GOOGLE_SERVO_V2_PID0 0x5002 +#define GOOGLE_SERVO_V2_PID1 0x5003 const struct dev_entry devs_ft2232spi[] = { - {FTDI_VID, FTDI_FT2232H_PID, OK, "FTDI", "FT2232H"}, - {FTDI_VID, FTDI_FT4232H_PID, OK, "FTDI", "FT4232H"}, - {FTDI_VID, FTDI_FT232H_PID, OK, "FTDI", "FT232H"}, - {FTDI_VID, TIAO_TUMPA_PID, OK, "TIAO", "USB Multi-Protocol Adapter"}, - {FTDI_VID, TIAO_TUMPA_LITE_PID, OK, "TIAO", "USB Multi-Protocol Adapter Lite"}, - {FTDI_VID, AMONTEC_JTAGKEY_PID, OK, "Amontec", "JTAGkey"}, - {GOEPEL_VID, GOEPEL_PICOTAP_PID, OK, "GOEPEL", "PicoTAP"}, - {GOOGLE_VID, GOOGLE_SERVO_PID, OK, "Google", "Servo"}, - {GOOGLE_VID, GOOGLE_SERVO_V2_PID0, OK, "Google", "Servo V2 Legacy"}, - {GOOGLE_VID, GOOGLE_SERVO_V2_PID1, OK, "Google", "Servo V2"}, - {FIC_VID, OPENMOKO_DBGBOARD_PID, OK, "FIC", "OpenMoko Neo1973 Debug board (V2+)"}, - {OLIMEX_VID, OLIMEX_ARM_OCD_PID, OK, "Olimex", "ARM-USB-OCD"}, - {OLIMEX_VID, OLIMEX_ARM_TINY_PID, OK, "Olimex", "ARM-USB-TINY"}, - {OLIMEX_VID, OLIMEX_ARM_OCD_H_PID, OK, "Olimex", "ARM-USB-OCD-H"}, - {OLIMEX_VID, OLIMEX_ARM_TINY_H_PID, OK, "Olimex", "ARM-USB-TINY-H"}, + {FTDI_VID, FTDI_FT2232H_PID, OK, "FTDI", "FT2232H"}, + {FTDI_VID, FTDI_FT4232H_PID, OK, "FTDI", "FT4232H"}, + {FTDI_VID, FTDI_FT232H_PID, OK, "FTDI", "FT232H"}, + {FTDI_VID, TIAO_TUMPA_PID, OK, "TIAO", "USB Multi-Protocol Adapter"}, + {FTDI_VID, TIAO_TUMPA_LITE_PID, OK, "TIAO", "USB Multi-Protocol Adapter Lite"}, + {FTDI_VID, AMONTEC_JTAGKEY_PID, OK, "Amontec", "JTAGkey"}, + {GOEPEL_VID, GOEPEL_PICOTAP_PID, OK, "GOEPEL", "PicoTAP"}, + {GOOGLE_VID, GOOGLE_SERVO_PID, OK, "Google", "Servo"}, + {GOOGLE_VID, GOOGLE_SERVO_V2_PID0, OK, "Google", "Servo V2 Legacy"}, + {GOOGLE_VID, GOOGLE_SERVO_V2_PID1, OK, "Google", "Servo V2"}, + {FIC_VID, OPENMOKO_DBGBOARD_PID, OK, "FIC", "OpenMoko Neo1973 Debug board (V2+)"}, + {OLIMEX_VID, OLIMEX_ARM_OCD_PID, OK, "Olimex", "ARM-USB-OCD"}, + {OLIMEX_VID, OLIMEX_ARM_TINY_PID, OK, "Olimex", "ARM-USB-TINY"}, + {OLIMEX_VID, OLIMEX_ARM_OCD_H_PID, OK, "Olimex", "ARM-USB-OCD-H"}, + {OLIMEX_VID, OLIMEX_ARM_TINY_H_PID, OK, "Olimex", "ARM-USB-TINY-H"}, - {0}, + {0}, }; #define DEFAULT_DIVISOR 2 -#define BITMODE_BITBANG_NORMAL 1 -#define BITMODE_BITBANG_SPI 2 +#define BITMODE_BITBANG_NORMAL 1 +#define BITMODE_BITBANG_SPI 2 /* The variables cs_bits and pindir store the values for the "set data bits low byte" MPSSE command that * sets the initial state and the direction of the I/O pins. The pin offsets are as follows: @@ -108,442 +108,442 @@ static const char *get_ft2232_devicename(int ft2232_vid, int ft2232_type) { - int i; - for (i = 0; devs_ft2232spi[i].vendor_name != NULL; i++) { - if ((devs_ft2232spi[i].device_id == ft2232_type) && (devs_ft2232spi[i].vendor_id == ft2232_vid)) - return devs_ft2232spi[i].device_name; - } - return "unknown device"; + int i; + for (i = 0; devs_ft2232spi[i].vendor_name != NULL; i++) { + if ((devs_ft2232spi[i].device_id == ft2232_type) && (devs_ft2232spi[i].vendor_id == ft2232_vid)) + return devs_ft2232spi[i].device_name; + } + return "unknown device"; } static const char *get_ft2232_vendorname(int ft2232_vid, int ft2232_type) { - int i; - for (i = 0; devs_ft2232spi[i].vendor_name != NULL; i++) { - if ((devs_ft2232spi[i].device_id == ft2232_type) && (devs_ft2232spi[i].vendor_id == ft2232_vid)) - return devs_ft2232spi[i].vendor_name; - } - return "unknown vendor"; + int i; + for (i = 0; devs_ft2232spi[i].vendor_name != NULL; i++) { + if ((devs_ft2232spi[i].device_id == ft2232_type) && (devs_ft2232spi[i].vendor_id == ft2232_vid)) + return devs_ft2232spi[i].vendor_name; + } + return "unknown vendor"; } static int send_buf(struct ftdi_context *ftdic, const unsigned char *buf, - int size) + int size) { - int r; - r = ftdi_write_data(ftdic, (unsigned char *) buf, size); - if (r < 0) { - msg_perr("ftdi_write_data: %d, %s\n", r, ftdi_get_error_string(ftdic)); - return 1; - } - return 0; + int r; + r = ftdi_write_data(ftdic, (unsigned char *) buf, size); + if (r < 0) { + msg_perr("ftdi_write_data: %d, %s\n", r, ftdi_get_error_string(ftdic)); + return 1; + } + return 0; } static int get_buf(struct ftdi_context *ftdic, const unsigned char *buf, - int size) + int size) { - int r; + int r; - while (size > 0) { - r = ftdi_read_data(ftdic, (unsigned char *) buf, size); - if (r < 0) { - msg_perr("ftdi_read_data: %d, %s\n", r, ftdi_get_error_string(ftdic)); - return 1; - } - buf += r; - size -= r; - } - return 0; + while (size > 0) { + r = ftdi_read_data(ftdic, (unsigned char *) buf, size); + if (r < 0) { + msg_perr("ftdi_read_data: %d, %s\n", r, ftdi_get_error_string(ftdic)); + return 1; + } + buf += r; + size -= r; + } + return 0; } static int ft2232_spi_send_command(struct flashctx *flash, - unsigned int writecnt, unsigned int readcnt, - const unsigned char *writearr, - unsigned char *readarr); + unsigned int writecnt, unsigned int readcnt, + const unsigned char *writearr, + unsigned char *readarr); static const struct spi_master spi_master_ft2232 = { - .features = SPI_MASTER_4BA, - .max_data_read = 64 * 1024, - .max_data_write = 256, - .command = ft2232_spi_send_command, - .multicommand = default_spi_send_multicommand, - .read = default_spi_read, - .write_256 = default_spi_write_256, - .write_aai = default_spi_write_aai, + .features = SPI_MASTER_4BA, + .max_data_read = 64 * 1024, + .max_data_write = 256, + .command = ft2232_spi_send_command, + .multicommand = default_spi_send_multicommand, + .read = default_spi_read, + .write_256 = default_spi_write_256, + .write_aai = default_spi_write_aai, }; /* Returns 0 upon success, a negative number upon errors. */ int ft2232_spi_init(void) { - int ret = 0; - struct ftdi_context *ftdic = &ftdic_context; - unsigned char buf[512]; - int ft2232_vid = FTDI_VID; - int ft2232_type = FTDI_FT4232H_PID; - int channel_count = 4; /* Stores the number of channels of the device. */ - enum ftdi_interface ft2232_interface = INTERFACE_A; - /* - * The 'H' chips can run with an internal clock of either 12 MHz or 60 MHz, - * but the non-H chips can only run at 12 MHz. We enable the divide-by-5 - * prescaler on the former to run on the same speed. - */ - uint8_t clock_5x = 1; - /* In addition to the prescaler mentioned above there is also another - * configurable one on all versions of the chips. Its divisor div can be - * set by a 16 bit value x according to the following formula: - * div = (1 + x) * 2 <-> x = div / 2 - 1 - * Hence the expressible divisors are all even numbers between 2 and - * 2^17 (=131072) resulting in SCK frequencies of 6 MHz down to about - * 92 Hz for 12 MHz inputs. - */ - uint32_t divisor = DEFAULT_DIVISOR; - int f; - char *arg; - double mpsse_clk; + int ret = 0; + struct ftdi_context *ftdic = &ftdic_context; + unsigned char buf[512]; + int ft2232_vid = FTDI_VID; + int ft2232_type = FTDI_FT4232H_PID; + int channel_count = 4; /* Stores the number of channels of the device. */ + enum ftdi_interface ft2232_interface = INTERFACE_A; + /* + * The 'H' chips can run with an internal clock of either 12 MHz or 60 MHz, + * but the non-H chips can only run at 12 MHz. We enable the divide-by-5 + * prescaler on the former to run on the same speed. + */ + uint8_t clock_5x = 1; + /* In addition to the prescaler mentioned above there is also another + * configurable one on all versions of the chips. Its divisor div can be + * set by a 16 bit value x according to the following formula: + * div = (1 + x) * 2 <-> x = div / 2 - 1 + * Hence the expressible divisors are all even numbers between 2 and + * 2^17 (=131072) resulting in SCK frequencies of 6 MHz down to about + * 92 Hz for 12 MHz inputs. + */ + uint32_t divisor = DEFAULT_DIVISOR; + int f; + char *arg; + double mpsse_clk; - arg = extract_programmer_param("type"); - if (arg) { - if (!strcasecmp(arg, "2232H")) { - ft2232_type = FTDI_FT2232H_PID; - channel_count = 2; - } else if (!strcasecmp(arg, "4232H")) { - ft2232_type = FTDI_FT4232H_PID; - channel_count = 4; - } else if (!strcasecmp(arg, "232H")) { - ft2232_type = FTDI_FT232H_PID; - channel_count = 1; - } else if (!strcasecmp(arg, "jtagkey")) { - ft2232_type = AMONTEC_JTAGKEY_PID; - channel_count = 2; - /* JTAGkey(2) needs to enable its output via Bit4 / GPIOL0 - * value: 0x18 OE=high, CS=high, DI=low, DO=low, SK=low - * dir: 0x1b OE=output, CS=output, DI=input, DO=output, SK=output */ - cs_bits = 0x18; - pindir = 0x1b; - } else if (!strcasecmp(arg, "picotap")) { - ft2232_vid = GOEPEL_VID; - ft2232_type = GOEPEL_PICOTAP_PID; - channel_count = 2; - } else if (!strcasecmp(arg, "tumpa")) { - /* Interface A is SPI1, B is SPI2. */ - ft2232_type = TIAO_TUMPA_PID; - channel_count = 2; - } else if (!strcasecmp(arg, "tumpalite")) { - /* Only one channel is used on lite edition */ - ft2232_type = TIAO_TUMPA_LITE_PID; - channel_count = 1; - } else if (!strcasecmp(arg, "busblaster")) { - /* In its default configuration it is a jtagkey clone */ - ft2232_type = FTDI_FT2232H_PID; - channel_count = 2; - cs_bits = 0x18; - pindir = 0x1b; - } else if (!strcasecmp(arg, "openmoko")) { - ft2232_vid = FIC_VID; - ft2232_type = OPENMOKO_DBGBOARD_PID; - channel_count = 2; - } else if (!strcasecmp(arg, "arm-usb-ocd")) { - ft2232_vid = OLIMEX_VID; - ft2232_type = OLIMEX_ARM_OCD_PID; - channel_count = 2; - /* arm-usb-ocd(-h) has an output buffer that needs to be enabled by pulling ADBUS4 low. - * value: 0x08 #OE=low, CS=high, DI=low, DO=low, SK=low - * dir: 0x1b #OE=output, CS=output, DI=input, DO=output, SK=output */ - cs_bits = 0x08; - pindir = 0x1b; - } else if (!strcasecmp(arg, "arm-usb-tiny")) { - ft2232_vid = OLIMEX_VID; - ft2232_type = OLIMEX_ARM_TINY_PID; - channel_count = 2; - } else if (!strcasecmp(arg, "arm-usb-ocd-h")) { - ft2232_vid = OLIMEX_VID; - ft2232_type = OLIMEX_ARM_OCD_H_PID; - channel_count = 2; - /* See arm-usb-ocd */ - cs_bits = 0x08; - pindir = 0x1b; - } else if (!strcasecmp(arg, "arm-usb-tiny-h")) { - ft2232_vid = OLIMEX_VID; - ft2232_type = OLIMEX_ARM_TINY_H_PID; - channel_count = 2; - } else if (!strcasecmp(arg, "google-servo")) { - ft2232_vid = GOOGLE_VID; - ft2232_type = GOOGLE_SERVO_PID; - } else if (!strcasecmp(arg, "google-servo-v2")) { - ft2232_vid = GOOGLE_VID; - ft2232_type = GOOGLE_SERVO_V2_PID1; - /* Default divisor is too fast, and chip ID fails */ - divisor = 6; - } else if (!strcasecmp(arg, "google-servo-v2-legacy")) { - ft2232_vid = GOOGLE_VID; - ft2232_type = GOOGLE_SERVO_V2_PID0; - } else if (!strcasecmp(arg, "flyswatter")) { - ft2232_type = FTDI_FT2232H_PID; - channel_count = 2; - /* Flyswatter and Flyswatter-2 require GPIO bits 0x80 - * and 0x40 to be driven low to enable output buffers */ - pindir = 0xcb; - } else { - msg_perr("Error: Invalid device type specified.\n"); - free(arg); - return -1; - } - } - free(arg); + arg = extract_programmer_param("type"); + if (arg) { + if (!strcasecmp(arg, "2232H")) { + ft2232_type = FTDI_FT2232H_PID; + channel_count = 2; + } else if (!strcasecmp(arg, "4232H")) { + ft2232_type = FTDI_FT4232H_PID; + channel_count = 4; + } else if (!strcasecmp(arg, "232H")) { + ft2232_type = FTDI_FT232H_PID; + channel_count = 1; + } else if (!strcasecmp(arg, "jtagkey")) { + ft2232_type = AMONTEC_JTAGKEY_PID; + channel_count = 2; + /* JTAGkey(2) needs to enable its output via Bit4 / GPIOL0 + * value: 0x18 OE=high, CS=high, DI=low, DO=low, SK=low + * dir: 0x1b OE=output, CS=output, DI=input, DO=output, SK=output */ + cs_bits = 0x18; + pindir = 0x1b; + } else if (!strcasecmp(arg, "picotap")) { + ft2232_vid = GOEPEL_VID; + ft2232_type = GOEPEL_PICOTAP_PID; + channel_count = 2; + } else if (!strcasecmp(arg, "tumpa")) { + /* Interface A is SPI1, B is SPI2. */ + ft2232_type = TIAO_TUMPA_PID; + channel_count = 2; + } else if (!strcasecmp(arg, "tumpalite")) { + /* Only one channel is used on lite edition */ + ft2232_type = TIAO_TUMPA_LITE_PID; + channel_count = 1; + } else if (!strcasecmp(arg, "busblaster")) { + /* In its default configuration it is a jtagkey clone */ + ft2232_type = FTDI_FT2232H_PID; + channel_count = 2; + cs_bits = 0x18; + pindir = 0x1b; + } else if (!strcasecmp(arg, "openmoko")) { + ft2232_vid = FIC_VID; + ft2232_type = OPENMOKO_DBGBOARD_PID; + channel_count = 2; + } else if (!strcasecmp(arg, "arm-usb-ocd")) { + ft2232_vid = OLIMEX_VID; + ft2232_type = OLIMEX_ARM_OCD_PID; + channel_count = 2; + /* arm-usb-ocd(-h) has an output buffer that needs to be enabled by pulling ADBUS4 low. + * value: 0x08 #OE=low, CS=high, DI=low, DO=low, SK=low + * dir: 0x1b #OE=output, CS=output, DI=input, DO=output, SK=output */ + cs_bits = 0x08; + pindir = 0x1b; + } else if (!strcasecmp(arg, "arm-usb-tiny")) { + ft2232_vid = OLIMEX_VID; + ft2232_type = OLIMEX_ARM_TINY_PID; + channel_count = 2; + } else if (!strcasecmp(arg, "arm-usb-ocd-h")) { + ft2232_vid = OLIMEX_VID; + ft2232_type = OLIMEX_ARM_OCD_H_PID; + channel_count = 2; + /* See arm-usb-ocd */ + cs_bits = 0x08; + pindir = 0x1b; + } else if (!strcasecmp(arg, "arm-usb-tiny-h")) { + ft2232_vid = OLIMEX_VID; + ft2232_type = OLIMEX_ARM_TINY_H_PID; + channel_count = 2; + } else if (!strcasecmp(arg, "google-servo")) { + ft2232_vid = GOOGLE_VID; + ft2232_type = GOOGLE_SERVO_PID; + } else if (!strcasecmp(arg, "google-servo-v2")) { + ft2232_vid = GOOGLE_VID; + ft2232_type = GOOGLE_SERVO_V2_PID1; + /* Default divisor is too fast, and chip ID fails */ + divisor = 6; + } else if (!strcasecmp(arg, "google-servo-v2-legacy")) { + ft2232_vid = GOOGLE_VID; + ft2232_type = GOOGLE_SERVO_V2_PID0; + } else if (!strcasecmp(arg, "flyswatter")) { + ft2232_type = FTDI_FT2232H_PID; + channel_count = 2; + /* Flyswatter and Flyswatter-2 require GPIO bits 0x80 + * and 0x40 to be driven low to enable output buffers */ + pindir = 0xcb; + } else { + msg_perr("Error: Invalid device type specified.\n"); + free(arg); + return -1; + } + } + free(arg); - arg = extract_programmer_param("port"); - if (arg) { - switch (toupper((unsigned char)*arg)) { - case 'A': - ft2232_interface = INTERFACE_A; - break; - case 'B': - ft2232_interface = INTERFACE_B; - if (channel_count < 2) - channel_count = -1; - break; - case 'C': - ft2232_interface = INTERFACE_C; - if (channel_count < 3) - channel_count = -1; - break; - case 'D': - ft2232_interface = INTERFACE_D; - if (channel_count < 4) - channel_count = -1; - break; - default: - channel_count = -1; - break; - } - if (channel_count < 0 || strlen(arg) != 1) { - msg_perr("Error: Invalid channel/port/interface specified: \"%s\".\n", arg); - free(arg); - return -2; - } - } - free(arg); + arg = extract_programmer_param("port"); + if (arg) { + switch (toupper((unsigned char)*arg)) { + case 'A': + ft2232_interface = INTERFACE_A; + break; + case 'B': + ft2232_interface = INTERFACE_B; + if (channel_count < 2) + channel_count = -1; + break; + case 'C': + ft2232_interface = INTERFACE_C; + if (channel_count < 3) + channel_count = -1; + break; + case 'D': + ft2232_interface = INTERFACE_D; + if (channel_count < 4) + channel_count = -1; + break; + default: + channel_count = -1; + break; + } + if (channel_count < 0 || strlen(arg) != 1) { + msg_perr("Error: Invalid channel/port/interface specified: \"%s\".\n", arg); + free(arg); + return -2; + } + } + free(arg); - arg = extract_programmer_param("divisor"); - if (arg && strlen(arg)) { - unsigned int temp = 0; - char *endptr; - temp = strtoul(arg, &endptr, 10); - if (*endptr || temp < 2 || temp > 131072 || temp & 0x1) { - msg_perr("Error: Invalid SPI frequency divisor specified: \"%s\".\n" - "Valid are even values between 2 and 131072.\n", arg); - free(arg); - return -2; - } - divisor = (uint32_t)temp; - } - free(arg); + arg = extract_programmer_param("divisor"); + if (arg && strlen(arg)) { + unsigned int temp = 0; + char *endptr; + temp = strtoul(arg, &endptr, 10); + if (*endptr || temp < 2 || temp > 131072 || temp & 0x1) { + msg_perr("Error: Invalid SPI frequency divisor specified: \"%s\".\n" + "Valid are even values between 2 and 131072.\n", arg); + free(arg); + return -2; + } + divisor = (uint32_t)temp; + } + free(arg); - /* Allows setting multiple GPIOL states, for example: csgpiol=012 */ - arg = extract_programmer_param("csgpiol"); - if (arg) { - unsigned int ngpios = strlen(arg); - for (unsigned int i = 0; i <= ngpios; i++) { - int temp = arg[i] - '0'; - if (ngpios == 0 || (ngpios != i && (temp < 0 || temp > 3))) { - msg_perr("Error: Invalid GPIOLs specified: \"%s\".\n" - "Valid values are numbers between 0 and 3. " - "Multiple GPIOLs can be specified.\n", arg); - free(arg); - return -2; - } else { - unsigned int pin = temp + 4; - cs_bits |= 1 << pin; - pindir |= 1 << pin; - } - } - } - free(arg); + /* Allows setting multiple GPIOL states, for example: csgpiol=012 */ + arg = extract_programmer_param("csgpiol"); + if (arg) { + unsigned int ngpios = strlen(arg); + for (unsigned int i = 0; i <= ngpios; i++) { + int temp = arg[i] - '0'; + if (ngpios == 0 || (ngpios != i && (temp < 0 || temp > 3))) { + msg_perr("Error: Invalid GPIOLs specified: \"%s\".\n" + "Valid values are numbers between 0 and 3. " + "Multiple GPIOLs can be specified.\n", arg); + free(arg); + return -2; + } else { + unsigned int pin = temp + 4; + cs_bits |= 1 << pin; + pindir |= 1 << pin; + } + } + } + free(arg); - msg_pdbg("Using device type %s %s ", - get_ft2232_vendorname(ft2232_vid, ft2232_type), - get_ft2232_devicename(ft2232_vid, ft2232_type)); - msg_pdbg("channel %s.\n", - (ft2232_interface == INTERFACE_A) ? "A" : - (ft2232_interface == INTERFACE_B) ? "B" : - (ft2232_interface == INTERFACE_C) ? "C" : "D"); + msg_pdbg("Using device type %s %s ", + get_ft2232_vendorname(ft2232_vid, ft2232_type), + get_ft2232_devicename(ft2232_vid, ft2232_type)); + msg_pdbg("channel %s.\n", + (ft2232_interface == INTERFACE_A) ? "A" : + (ft2232_interface == INTERFACE_B) ? "B" : + (ft2232_interface == INTERFACE_C) ? "C" : "D"); - if (ftdi_init(ftdic) < 0) { - msg_perr("ftdi_init failed.\n"); - return -3; - } + if (ftdi_init(ftdic) < 0) { + msg_perr("ftdi_init failed.\n"); + return -3; + } - if (ftdi_set_interface(ftdic, ft2232_interface) < 0) { - msg_perr("Unable to select channel (%s).\n", ftdi_get_error_string(ftdic)); - } + if (ftdi_set_interface(ftdic, ft2232_interface) < 0) { + msg_perr("Unable to select channel (%s).\n", ftdi_get_error_string(ftdic)); + } - arg = extract_programmer_param("serial"); - f = ftdi_usb_open_desc(ftdic, ft2232_vid, ft2232_type, NULL, arg); - free(arg); + arg = extract_programmer_param("serial"); + f = ftdi_usb_open_desc(ftdic, ft2232_vid, ft2232_type, NULL, arg); + free(arg); - if (f < 0 && f != -5) { - msg_perr("Unable to open FTDI device: %d (%s).\n", f, ftdi_get_error_string(ftdic)); - return -4; - } + if (f < 0 && f != -5) { + msg_perr("Unable to open FTDI device: %d (%s).\n", f, ftdi_get_error_string(ftdic)); + return -4; + } - if (ftdic->type != TYPE_2232H && ftdic->type != TYPE_4232H && ftdic->type != TYPE_232H) { - msg_pdbg("FTDI chip type %d is not high-speed.\n", ftdic->type); - clock_5x = 0; - } + if (ftdic->type != TYPE_2232H && ftdic->type != TYPE_4232H && ftdic->type != TYPE_232H) { + msg_pdbg("FTDI chip type %d is not high-speed.\n", ftdic->type); + clock_5x = 0; + } - if (ftdi_usb_reset(ftdic) < 0) { - msg_perr("Unable to reset FTDI device (%s).\n", ftdi_get_error_string(ftdic)); - } + if (ftdi_usb_reset(ftdic) < 0) { + msg_perr("Unable to reset FTDI device (%s).\n", ftdi_get_error_string(ftdic)); + } - if (ftdi_set_latency_timer(ftdic, 2) < 0) { - msg_perr("Unable to set latency timer (%s).\n", ftdi_get_error_string(ftdic)); - } + if (ftdi_set_latency_timer(ftdic, 2) < 0) { + msg_perr("Unable to set latency timer (%s).\n", ftdi_get_error_string(ftdic)); + } - if (ftdi_write_data_set_chunksize(ftdic, 256)) { - msg_perr("Unable to set chunk size (%s).\n", ftdi_get_error_string(ftdic)); - } + if (ftdi_write_data_set_chunksize(ftdic, 270)) { + msg_perr("Unable to set chunk size (%s).\n", ftdi_get_error_string(ftdic)); + } - if (ftdi_set_bitmode(ftdic, 0x00, BITMODE_BITBANG_SPI) < 0) { - msg_perr("Unable to set bitmode to SPI (%s).\n", ftdi_get_error_string(ftdic)); - } + if (ftdi_set_bitmode(ftdic, 0x00, BITMODE_BITBANG_SPI) < 0) { + msg_perr("Unable to set bitmode to SPI (%s).\n", ftdi_get_error_string(ftdic)); + } - if (clock_5x) { - msg_pdbg("Disable divide-by-5 front stage\n"); - buf[0] = 0x8a; /* Disable divide-by-5. DIS_DIV_5 in newer libftdi */ - if (send_buf(ftdic, buf, 1)) { - ret = -5; - goto ftdi_err; - } - mpsse_clk = 60.0; - } else { - mpsse_clk = 12.0; - } + if (clock_5x) { + msg_pdbg("Disable divide-by-5 front stage\n"); + buf[0] = 0x8a; /* Disable divide-by-5. DIS_DIV_5 in newer libftdi */ + if (send_buf(ftdic, buf, 1)) { + ret = -5; + goto ftdi_err; + } + mpsse_clk = 60.0; + } else { + mpsse_clk = 12.0; + } - msg_pdbg("Set clock divisor\n"); - buf[0] = TCK_DIVISOR; - buf[1] = (divisor / 2 - 1) & 0xff; - buf[2] = ((divisor / 2 - 1) >> 8) & 0xff; - if (send_buf(ftdic, buf, 3)) { - ret = -6; - goto ftdi_err; - } + msg_pdbg("Set clock divisor\n"); + buf[0] = TCK_DIVISOR; + buf[1] = (divisor / 2 - 1) & 0xff; + buf[2] = ((divisor / 2 - 1) >> 8) & 0xff; + if (send_buf(ftdic, buf, 3)) { + ret = -6; + goto ftdi_err; + } - msg_pdbg("MPSSE clock: %f MHz, divisor: %u, SPI clock: %f MHz\n", - mpsse_clk, divisor, (double)(mpsse_clk / divisor)); + msg_pdbg("MPSSE clock: %f MHz, divisor: %u, SPI clock: %f MHz\n", + mpsse_clk, divisor, (double)(mpsse_clk / divisor)); - /* Disconnect TDI/DO to TDO/DI for loopback. */ - msg_pdbg("No loopback of TDI/DO TDO/DI\n"); - buf[0] = LOOPBACK_END; - if (send_buf(ftdic, buf, 1)) { - ret = -7; - goto ftdi_err; - } + /* Disconnect TDI/DO to TDO/DI for loopback. */ + msg_pdbg("No loopback of TDI/DO TDO/DI\n"); + buf[0] = LOOPBACK_END; + if (send_buf(ftdic, buf, 1)) { + ret = -7; + goto ftdi_err; + } - msg_pdbg("Set data bits\n"); - buf[0] = SET_BITS_LOW; - buf[1] = cs_bits; - buf[2] = pindir; - if (send_buf(ftdic, buf, 3)) { - ret = -8; - goto ftdi_err; - } + msg_pdbg("Set data bits\n"); + buf[0] = SET_BITS_LOW; + buf[1] = cs_bits; + buf[2] = pindir; + if (send_buf(ftdic, buf, 3)) { + ret = -8; + goto ftdi_err; + } - register_spi_master(&spi_master_ft2232); + register_spi_master(&spi_master_ft2232); - return 0; + return 0; ftdi_err: - if ((f = ftdi_usb_close(ftdic)) < 0) { - msg_perr("Unable to close FTDI device: %d (%s)\n", f, ftdi_get_error_string(ftdic)); - } - return ret; + if ((f = ftdi_usb_close(ftdic)) < 0) { + msg_perr("Unable to close FTDI device: %d (%s)\n", f, ftdi_get_error_string(ftdic)); + } + return ret; } /* Returns 0 upon success, a negative number upon errors. */ static int ft2232_spi_send_command(struct flashctx *flash, - unsigned int writecnt, unsigned int readcnt, - const unsigned char *writearr, - unsigned char *readarr) + unsigned int writecnt, unsigned int readcnt, + const unsigned char *writearr, + unsigned char *readarr) { - struct ftdi_context *ftdic = &ftdic_context; - static unsigned char *buf = NULL; - /* failed is special. We use bitwise ops, but it is essentially bool. */ - int i = 0, ret = 0, failed = 0; - int bufsize; - static int oldbufsize = 0; + struct ftdi_context *ftdic = &ftdic_context; + static unsigned char *buf = NULL; + /* failed is special. We use bitwise ops, but it is essentially bool. */ + int i = 0, ret = 0, failed = 0; + int bufsize; + static int oldbufsize = 0; - if (writecnt > 65536 || readcnt > 65536) - return SPI_INVALID_LENGTH; + if (writecnt > 65536 || readcnt > 65536) + return SPI_INVALID_LENGTH; - /* buf is not used for the response from the chip. */ - bufsize = max(writecnt + 9, 260 + 9); - /* Never shrink. realloc() calls are expensive. */ - if (bufsize > oldbufsize) { - buf = realloc(buf, bufsize); - if (!buf) { - msg_perr("Out of memory!\n"); - /* TODO: What to do with buf? */ - return SPI_GENERIC_ERROR; - } - oldbufsize = bufsize; - } + /* buf is not used for the response from the chip. */ + bufsize = max(writecnt + 9, 260 + 9); + /* Never shrink. realloc() calls are expensive. */ + if (bufsize > oldbufsize) { + buf = realloc(buf, bufsize); + if (!buf) { + msg_perr("Out of memory!\n"); + /* TODO: What to do with buf? */ + return SPI_GENERIC_ERROR; + } + oldbufsize = bufsize; + } - /* - * Minimize USB transfers by packing as many commands as possible - * together. If we're not expecting to read, we can assert CS#, write, - * and deassert CS# all in one shot. If reading, we do three separate - * operations. - */ - msg_pspew("Assert CS#\n"); - buf[i++] = SET_BITS_LOW; - buf[i++] = ~ 0x08 & cs_bits; /* assert CS (3rd) bit only */ - buf[i++] = pindir; + /* + * Minimize USB transfers by packing as many commands as possible + * together. If we're not expecting to read, we can assert CS#, write, + * and deassert CS# all in one shot. If reading, we do three separate + * operations. + */ + msg_pspew("Assert CS#\n"); + buf[i++] = SET_BITS_LOW; + buf[i++] = ~ 0x08 & cs_bits; /* assert CS (3rd) bit only */ + buf[i++] = pindir; - if (writecnt) { - buf[i++] = MPSSE_DO_WRITE | MPSSE_WRITE_NEG; - buf[i++] = (writecnt - 1) & 0xff; - buf[i++] = ((writecnt - 1) >> 8) & 0xff; - memcpy(buf + i, writearr, writecnt); - i += writecnt; - } + if (writecnt) { + buf[i++] = MPSSE_DO_WRITE | MPSSE_WRITE_NEG; + buf[i++] = (writecnt - 1) & 0xff; + buf[i++] = ((writecnt - 1) >> 8) & 0xff; + memcpy(buf + i, writearr, writecnt); + i += writecnt; + } - /* - * Optionally terminate this batch of commands with a - * read command, then do the fetch of the results. - */ - if (readcnt) { - buf[i++] = MPSSE_DO_READ; - buf[i++] = (readcnt - 1) & 0xff; - buf[i++] = ((readcnt - 1) >> 8) & 0xff; - ret = send_buf(ftdic, buf, i); - failed = ret; - /* We can't abort here, we still have to deassert CS#. */ - if (ret) - msg_perr("send_buf failed before read: %i\n", ret); - i = 0; - if (ret == 0) { - /* - * FIXME: This is unreliable. There's no guarantee that - * we read the response directly after sending the read - * command. We may be scheduled out etc. - */ - ret = get_buf(ftdic, readarr, readcnt); - failed |= ret; - /* We can't abort here either. */ - if (ret) - msg_perr("get_buf failed: %i\n", ret); - } - } + /* + * Optionally terminate this batch of commands with a + * read command, then do the fetch of the results. + */ + if (readcnt) { + buf[i++] = MPSSE_DO_READ; + buf[i++] = (readcnt - 1) & 0xff; + buf[i++] = ((readcnt - 1) >> 8) & 0xff; + ret = send_buf(ftdic, buf, i); + failed = ret; + /* We can't abort here, we still have to deassert CS#. */ + if (ret) + msg_perr("send_buf failed before read: %i\n", ret); + i = 0; + if (ret == 0) { + /* + * FIXME: This is unreliable. There's no guarantee that + * we read the response directly after sending the read + * command. We may be scheduled out etc. + */ + ret = get_buf(ftdic, readarr, readcnt); + failed |= ret; + /* We can't abort here either. */ + if (ret) + msg_perr("get_buf failed: %i\n", ret); + } + } - msg_pspew("De-assert CS#\n"); - buf[i++] = SET_BITS_LOW; - buf[i++] = cs_bits; - buf[i++] = pindir; - ret = send_buf(ftdic, buf, i); - failed |= ret; - if (ret) - msg_perr("send_buf failed at end: %i\n", ret); + msg_pspew("De-assert CS#\n"); + buf[i++] = SET_BITS_LOW; + buf[i++] = cs_bits; + buf[i++] = pindir; + ret = send_buf(ftdic, buf, i); + failed |= ret; + if (ret) + msg_perr("send_buf failed at end: %i\n", ret); - return failed ? -1 : 0; + return failed ? -1 : 0; } #endif -- To view, visit https://review.coreboot.org/c/flashrom/+/39632 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Iac067a23025e9df053ab9cd4e82a98de70046c18 Gerrit-Change-Number: 39632 Gerrit-PatchSet: 1 Gerrit-Owner: el-coder-sb Gerrit-MessageType: newchange

3 19

Change in flashrom[master]: spi: add support for Winbond W25Q64JW
by Scott Chao (Code Review) 08 Apr '20

08 Apr '20

Scott Chao has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/40275 ) Change subject: spi: add support for Winbond W25Q64JW ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/flashrom/+/40275 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I8637129421a3b0f96bd8dffa4f50783ea6931967 Gerrit-Change-Number: 40275 Gerrit-PatchSet: 1 Gerrit-Owner: Scott Chao <scott.chao(a)bitland.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Peichao Li <peichao.wang(a)bitland.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Casper Chang <casper.chang(a)bitland.corp-partner.google.com> Gerrit-CC: Paul Ma <magf(a)bitland.com.cn> Gerrit-Comment-Date: Wed, 08 Apr 2020 14:15:46 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in flashrom[master]: lspcon_i2c_spi.c: Add support for the i2c-controlled SPI master in PS...
by Shiyu Sun (Code Review) 01 Apr '20

01 Apr '20

Shiyu Sun has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/39687 ) Change subject: lspcon_i2c_spi.c: Add support for the i2c-controlled SPI master in PS175/176. ...................................................................... lspcon_i2c_spi.c: Add support for the i2c-controlled SPI master in PS175/176. Usage is as follows: flashrom -p lspcon_i2c_spi:bus=X where X is the bus number. Tested with following commands, read/write/erase works good. flashrom -p lspcon_i2c_spi:bus=7 -r /tmp/foo; flashrom -p lspcon_i2c_spi:bus=7 -E; flashrom -p lspcon_i2c_spi:bus=7 -w /tmp/foo; Change-Id: I039e683252cfaf1ffef8694a3e8081b1b6b944f7 Signed-off-by: Shiyu Sun <sshiyu(a)chromium.org> --- M Makefile M flashrom.c A lspcon_i2c_spi.c M meson.build M meson_options.txt M programmer.h 6 files changed, 548 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/87/39687/1 diff --git a/Makefile b/Makefile index aa77a64..298890e 100644 --- a/Makefile +++ b/Makefile @@ -195,6 +195,11 @@ else override CONFIG_STLINKV3_SPI = no endif +ifeq ($(CONFIG_LSPCON_I2C_SPI), yes) +UNSUPPORTED_FEATURES += CONFIG_LSPCON_I2C_SPI=yes +else +override CONFIG_LSPCON_I2C_SPI = no +endif # libjaylink is also not available for DOS ifeq ($(CONFIG_JLINK_SPI), yes) UNSUPPORTED_FEATURES += CONFIG_JLINK_SPI=yes @@ -306,6 +311,11 @@ else override CONFIG_SATAMV = no endif +ifeq ($(CONFIG_LSPCON_I2C_SPI), yes) +UNSUPPORTED_FEATURES += CONFIG_LSPCON_I2C_SPI=yes +else +override CONFIG_LSPCON_I2C_SPI = no +endif endif ifneq ($(TARGET_OS), MinGW) @@ -381,6 +391,11 @@ else override CONFIG_STLINKV3_SPI = no endif +ifeq ($(CONFIG_LSPCON_I2C_SPI), yes) +UNSUPPORTED_FEATURES += CONFIG_LSPCON_I2C_SPI=yes +else +override CONFIG_LSPCON_I2C_SPI = no +endif ifeq ($(CONFIG_CH341A_SPI), yes) UNSUPPORTED_FEATURES += CONFIG_CH341A_SPI=yes else @@ -656,6 +671,9 @@ # Always enable STLink V3 CONFIG_STLINKV3_SPI ?= yes +# Always enable I2C SPI +CONFIG_LSPCON_I2C_SPI ?= yes + # Always enable dummy tracing for now. CONFIG_DUMMY ?= yes @@ -735,6 +753,7 @@ override CONFIG_DEVELOPERBOX_SPI = no override CONFIG_PICKIT2_SPI = no override CONFIG_STLINKV3_SPI = no +override CONFIG_LSPCON_I2C_SPI = no endif ifeq ($(CONFIG_ENABLE_LIBPCI_PROGRAMMERS), no) override CONFIG_INTERNAL = no @@ -913,6 +932,12 @@ NEED_LIBUSB1 += CONFIG_STLINKV3_SPI endif +ifeq ($(CONFIG_LSPCON_I2C_SPI), yes) +FEATURE_CFLAGS += -D'CONFIG_LSPCON_I2C_SPI=1' +PROGRAMMER_OBJS += lspcon_i2c_spi.o +NEED_LIBUSB1 += CONFIG_LSPCON_I2C_SPI +endif + ifneq ($(NEED_LIBFTDI), ) FTDILIBS := $(call debug_shell,[ -n "$(PKG_CONFIG_LIBDIR)" ] && export PKG_CONFIG_LIBDIR="$(PKG_CONFIG_LIBDIR)" ; $(PKG_CONFIG) --libs libftdi1 || $(PKG_CONFIG) --libs libftdi || printf "%s" "-lftdi -lusb") FEATURE_CFLAGS += $(call debug_shell,grep -q "FT232H := yes" .features && printf "%s" "-D'HAVE_FT232H=1'") diff --git a/flashrom.c b/flashrom.c index e541b68..3fc705a 100644 --- a/flashrom.c +++ b/flashrom.c @@ -389,6 +389,18 @@ }, #endif +#if CONFIG_LSPCON_I2C_SPI == 1 + { + .name = "lspcon_i2c_spi", + .type = OTHER, + .devs.note = "Device files /dev/i2c-*.\n", + .init = lspcon_i2c_spi_init, + .map_flash_region = fallback_map, + .unmap_flash_region = fallback_unmap, + .delay = internal_delay, + }, +#endif + #if CONFIG_USBBLASTER_SPI == 1 { .name = "usbblaster_spi", diff --git a/lspcon_i2c_spi.c b/lspcon_i2c_spi.c new file mode 100644 index 0000000..d56da92 --- /dev/null +++ b/lspcon_i2c_spi.c @@ -0,0 +1,499 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2020 The Chromium OS Authors + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdlib.h> +#include <stdint.h> +#include <stdio.h> +#include <string.h> +#include <time.h> +#include <errno.h> + +#include "programmer.h" +#include "spi.h" +#include "i2c_helper.h" + +#define REGISTER_ADDRESS (0x94 >> 1) +#define PAGE_ADDRESS (0x9e >> 1) +#define PAGE_SIZE 256 +#define READ_SIZE 32 +#define MAX_SPI_WAIT_RETRIES 1000 +#define FUNCTION_ERR -1 + +#define CLT2_SPI 0x82 +#define SPIEDID_BASE_ADDR2 0x8d +#define ROMADDR_BYTE1 0x8e +#define ROMADDR_BYTE2 0x8f +#define SWSPI_WDATA 0x90 + #define SWSPI_WDATA_CLEAR_STATUS 0x00 + #define SWSPI_WDATA_WRITE_REGISTER 0x01 + #define SWSPI_WDATA_READ_REGISTER 0x05 + #define SWSPI_WDATA_ENABLE_REGISTER 0x06 + #define SWSPI_WDATA_SECTOR_ERASE 0x20 + #define SWSPI_WDATA_PROTECT_BP 0x8c +#define SWSPI_RDATA 0x91 +#define SWSPI_LEN 0x92 +#define SWSPICTL 0x93 + #define SWSPICTL_ACCESS_TRIGGER 1 + #define SWSPICTL_CLEAR_PTR (1 << 1) + #define SWSPICTL_NO_READ (1 << 2) + #define SWSPICTL_ENABLE_READBACK (1 << 3) + #define SWSPICTL_MOT (1 << 4) +#define SPISTATUS 0x9e + #define SPISTATUS_BYTE_PROGRAM_FINISHED 0 + #define SPISTATUS_BYTE_PROGRAM_IN_IF 1 + #define SPISTATUS_BYTE_PROGRAM_SEND_DONE (1 << 1) + #define SPISTATUS_SECTOR_ERASE_FINISHED 0 + #define SPISTATUS_SECTOR_ERASE_IN_IF (1 << 2) + #define SPISTATUS_SECTOR_ERASE_SEND_DONE (1 << 3) + #define SPISTATUS_CHIP_ERASE_FINISHED 0 + #define SPISTATUS_CHIP_ERASE_IN_IF (1 << 4) + #define SPISTATUS_CHIP_ERASE_SEND_DONE (1 << 5) + #define SPISTATUS_FW_UPDATE_ENABLE (1 << 6) +#define WRITE_PROTECTION 0xb3 + #define WRITE_PROTECTION_ON 0 + #define WRITE_PROTECTION_OFF 0x10 +#define MPU 0xbc +#define PAGE_HW_WRITE 0xda + #define PAGE_HW_WRITE_DISABLE 0 + #define PAGE_HW_COFIG_REGISTER 0xaa + #define PAGE_HW_WRITE_ENABLE 0x55 + +struct lspcon_i2c_spi_data { + int fd; +}; + +typedef struct { + uint8_t command; + uint8_t data_size; + const uint8_t *data; + uint8_t control; +} packet_t; + +static int lspcon_i2c_spi_write_data(int fd, uint16_t addr, void *buf, uint16_t len) +{ + i2c_buffer_t data; + if (i2c_buffer_t_fill(&data, buf, len)) + return FUNCTION_ERR; + + return i2c_write(fd, addr, &data) == len ? 0 : FUNCTION_ERR; +} + +static int lspcon_i2c_spi_read_data(int fd, uint16_t addr, void *buf, uint16_t len) +{ + i2c_buffer_t data; + if (i2c_buffer_t_fill(&data, buf, len)) + return FUNCTION_ERR; + + return i2c_read(fd, addr, &data) == len ? 0 : FUNCTION_ERR; +} + +static int get_fd_from_context(struct flashctx *flash) +{ + if (!flash || !flash->mst || !flash->mst->spi.data) { + msg_perr("Unable to extract fd from flash context.\n"); + return FUNCTION_ERR; + } + + return ((const struct lspcon_i2c_spi_data *)flash->mst->spi.data)->fd; +} + +static int lspcon_i2c_spi_write_register(int fd, uint8_t i2c_register, uint8_t value) +{ + uint8_t command[] = { i2c_register, value }; + return lspcon_i2c_spi_write_data(fd, REGISTER_ADDRESS, command, 2); +} + +static int lspcon_i2c_spi_read_register(int fd, uint8_t i2c_register, uint8_t *value) +{ + uint8_t command[] = { i2c_register }; + int ret = lspcon_i2c_spi_write_data(fd, REGISTER_ADDRESS, command, 1); + ret |= lspcon_i2c_spi_read_data(fd, REGISTER_ADDRESS, value, 1); + + return ret ? FUNCTION_ERR : 0; +} + +static int lspcon_i2c_spi_register_control(int fd, packet_t *packet) +{ + int i; + int ret = lspcon_i2c_spi_write_register(fd, SWSPI_WDATA, packet->command); + if (ret) + return ret; + + /* Higher 4 bits are read size. */ + int write_size = packet->data_size & 0x0f; + for (i = 0; i < write_size; ++i) { + ret |= lspcon_i2c_spi_write_register(fd, SWSPI_WDATA, packet->data[i]); + } + + ret |= lspcon_i2c_spi_write_register(fd, SWSPI_LEN, packet->data_size); + ret |= lspcon_i2c_spi_write_register(fd, SWSPICTL, packet->control); + + return ret; +} + +static int lspcon_i2c_spi_wait_command_done(int fd, unsigned int offset, int mask) +{ + uint8_t val; + int tried = 0; + int ret = 0; + do { + ret |= lspcon_i2c_spi_read_register(fd, offset, &val); + } while(!ret && (val & mask) && ++tried < MAX_SPI_WAIT_RETRIES); + + if (tried == MAX_SPI_WAIT_RETRIES) { + msg_perr("Error: Time out on sending command.\n"); + return -MAX_SPI_WAIT_RETRIES; + } + + return (val & mask) ? FUNCTION_ERR : ret; +} + +static int lspcon_i2c_spi_wait_rom_free(int fd) +{ + uint8_t val; + int tried = 0; + int ret = 0; + ret |= lspcon_i2c_spi_wait_command_done(fd, SPISTATUS, + SPISTATUS_SECTOR_ERASE_IN_IF | SPISTATUS_SECTOR_ERASE_SEND_DONE); + if (ret) + return ret; + + do { + packet_t packet = { SWSPI_WDATA_READ_REGISTER, 0, NULL, SWSPICTL_ACCESS_TRIGGER }; + ret |= lspcon_i2c_spi_register_control(fd, &packet); + ret |= lspcon_i2c_spi_wait_command_done(fd, SWSPICTL, SWSPICTL_ACCESS_TRIGGER); + ret |= lspcon_i2c_spi_read_register(fd, SWSPI_RDATA, &val); + } while (!ret && (val & SWSPICTL_ACCESS_TRIGGER) && ++tried < MAX_SPI_WAIT_RETRIES); + + if (tried == MAX_SPI_WAIT_RETRIES) { + msg_perr("Error: Time out on waiting ROM free.\n"); + return -MAX_SPI_WAIT_RETRIES; + } + + return (val & SWSPICTL_ACCESS_TRIGGER) ? FUNCTION_ERR : ret; +} + +static int lspcon_i2c_spi_toggle_register_protection(int fd, int toggle) +{ + return lspcon_i2c_spi_write_register(fd, WRITE_PROTECTION, + toggle ? WRITE_PROTECTION_OFF : WRITE_PROTECTION_ON); +} + +static int lspcon_i2c_spi_enable_write_status_register(int fd) +{ + int ret = lspcon_i2c_spi_toggle_register_protection(fd, 1); + packet_t packet = { + SWSPI_WDATA_ENABLE_REGISTER, 0, NULL, SWSPICTL_ACCESS_TRIGGER | SWSPICTL_NO_READ }; + ret |= lspcon_i2c_spi_register_control(fd, &packet); + ret |= lspcon_i2c_spi_toggle_register_protection(fd, 0); + + return ret; +} + +static int lspcon_i2c_spi_enable_write_status_register_protection(int fd) +{ + int ret = lspcon_i2c_spi_toggle_register_protection(fd, 1); + uint8_t data[] = { SWSPI_WDATA_PROTECT_BP }; + packet_t packet = { + SWSPI_WDATA_WRITE_REGISTER, 1, data, SWSPICTL_ACCESS_TRIGGER | SWSPICTL_NO_READ }; + ret |= lspcon_i2c_spi_register_control(fd, &packet); + ret |= lspcon_i2c_spi_toggle_register_protection(fd, 0); + + return ret; +} + +static int lspcon_i2c_spi_disable_protection(int fd) +{ + int ret = lspcon_i2c_spi_toggle_register_protection(fd, 1); + uint8_t data[] = { SWSPI_WDATA_CLEAR_STATUS }; + packet_t packet = { + SWSPI_WDATA_WRITE_REGISTER, 1, &data[0], SWSPICTL_ACCESS_TRIGGER | SWSPICTL_NO_READ }; + ret |= lspcon_i2c_spi_register_control(fd, &packet); + ret |= lspcon_i2c_spi_toggle_register_protection(fd, 0); + + return ret; +} + +static int lspcon_i2c_spi_disable_hw_write(int fd) +{ + return lspcon_i2c_spi_write_register(fd, PAGE_HW_WRITE, PAGE_HW_WRITE_DISABLE); +} + +static int lspcon_i2c_spi_enable_write_protection(int fd) +{ + int ret = lspcon_i2c_spi_enable_write_status_register(fd); + ret |= lspcon_i2c_spi_enable_write_status_register_protection(fd); + ret |= lspcon_i2c_spi_wait_rom_free(fd); + ret |= lspcon_i2c_spi_disable_hw_write(fd); + + return ret; +} + +static int lspcon_i2c_spi_disable_all_protection(int fd) +{ + int ret = lspcon_i2c_spi_enable_write_status_register(fd); + ret |= lspcon_i2c_spi_disable_protection(fd); + ret |= lspcon_i2c_spi_wait_rom_free(fd); + + return ret; +} + +static int lspcon_i2c_spi_send_command(struct flashctx *flash, + unsigned int writecnt, unsigned int readcnt, + const unsigned char *writearr, + unsigned char *readarr) +{ + unsigned int i; + if (writecnt > 16 || readcnt > 16 || writecnt == 0) { + msg_perr("Error: Invalid read/write count for send command.\n"); + return FUNCTION_ERR; + } + + int fd = get_fd_from_context(flash); + if (fd < 0) + return FUNCTION_ERR; + + int ret = lspcon_i2c_spi_disable_all_protection(fd); + ret |= lspcon_i2c_spi_enable_write_status_register(fd); + ret |= lspcon_i2c_spi_toggle_register_protection(fd, 1); + + /* First bit of writearr shuld be the command value, followed by the value to write. + Read length occupies 4 bit and represents 16 level, thus if read 1 bit, + read length should be set 0. */ + packet_t packet = { + writearr[0], (writecnt - 1) | ((readcnt - 1) << 4), &writearr[1], + SWSPICTL_ACCESS_TRIGGER | (readcnt ? 0 : SWSPICTL_NO_READ), + }; + + ret |= lspcon_i2c_spi_register_control(fd, &packet); + ret |= lspcon_i2c_spi_wait_command_done(fd, SWSPICTL, SWSPICTL_ACCESS_TRIGGER); + ret |= lspcon_i2c_spi_toggle_register_protection(fd, 0); + if (ret) + return ret; + + for (i = 0; i < readcnt; ++i) { + ret |= lspcon_i2c_spi_read_register(fd, SWSPI_RDATA, &readarr[i]); + } + + ret |= lspcon_i2c_spi_wait_rom_free(fd); + + return ret; +} + +static int lspcon_i2c_spi_enable_hw_write(int fd) +{ + int ret = 0; + ret |= lspcon_i2c_spi_write_register(fd, PAGE_HW_WRITE, PAGE_HW_COFIG_REGISTER); + ret |= lspcon_i2c_spi_write_register(fd, PAGE_HW_WRITE, PAGE_HW_WRITE_ENABLE); + ret |= lspcon_i2c_spi_write_register(fd, PAGE_HW_WRITE, 0x50); + ret |= lspcon_i2c_spi_write_register(fd, PAGE_HW_WRITE, 0x41); + ret |= lspcon_i2c_spi_write_register(fd, PAGE_HW_WRITE, 0x52); + ret |= lspcon_i2c_spi_write_register(fd, PAGE_HW_WRITE, 0x44); + + return ret; +} + +static int lspcon_i2c_clt2_spi_reset(int fd) +{ + int ret = 0; + ret |= lspcon_i2c_spi_write_register(fd, CLT2_SPI, 0x20); + struct timespec wait_100_ms = { 0, 100000000 }; + nanosleep(&wait_100_ms, NULL); + ret |= lspcon_i2c_spi_write_register(fd, CLT2_SPI, 0x00); + + return ret; +} + +static int lspcon_i2c_spi_reset_mpu_stop(int fd) +{ + int ret = 0; + ret |= lspcon_i2c_spi_write_register(fd, MPU, 0xc0); // cmd mode + ret |= lspcon_i2c_spi_write_register(fd, MPU, 0x40); // stop mcu + + return ret; +} + +static int lspcon_i2c_spi_map_page(int fd, unsigned int offset) +{ + /* Page number byte, need to / PAGE_SIZE. */ + uint8_t command_byte1[] = { ROMADDR_BYTE1, (offset >> 8) & 0xff }; + uint8_t command_byte2[] = { ROMADDR_BYTE2, (offset >> 16) }; + int ret = 0; + ret |= lspcon_i2c_spi_write_data(fd, REGISTER_ADDRESS, command_byte1, 2); + ret |= lspcon_i2c_spi_write_data(fd, REGISTER_ADDRESS, command_byte2, 2); + + return ret ? FUNCTION_ERR : 0; +} + +static int lspcon_i2c_spi_read(struct flashctx *flash, uint8_t *buf, + unsigned int start, unsigned int len) +{ + unsigned int i; + int ret = 0; + if (start & 0xff) + return default_spi_read(flash, buf, start, len); + + int fd = get_fd_from_context(flash); + if (fd < 0) + return FUNCTION_ERR; + + for (i = 0; i < len; i += PAGE_SIZE) { + ret |= lspcon_i2c_spi_map_page(fd, start + i); + ret |= lspcon_i2c_spi_read_data(fd, PAGE_ADDRESS, buf + i, min(len - i, PAGE_SIZE)); + } + + return ret; +} + +static int lspcon_i2c_spi_write_page(int fd, const uint8_t *buf, unsigned int len) +{ + uint8_t write_buffer[len + 1]; + write_buffer[0] = 0; + memcpy(write_buffer + 1, buf, len); + + return lspcon_i2c_spi_write_data(fd, PAGE_ADDRESS, write_buffer, len + 1); +} + +static int lspcon_i2c_spi_write_256(struct flashctx *flash, const uint8_t *buf, + unsigned int start, unsigned int len) +{ + int ret = 0; + if (start & 0xff) + return default_spi_write_256(flash, buf, start, len); + + int fd = get_fd_from_context(flash); + if (fd < 0) + return FUNCTION_ERR; + + ret |= lspcon_i2c_spi_disable_all_protection(fd); + /* Enable hardware write and reset clt2SPI interface. */ + ret |= lspcon_i2c_spi_enable_hw_write(fd); + ret |= lspcon_i2c_clt2_spi_reset(fd); + + for (unsigned int i = 0; i < len; i += PAGE_SIZE) { + ret |= lspcon_i2c_spi_map_page(fd, start + i); + ret |= lspcon_i2c_spi_write_page(fd, buf + i, min(len - i, PAGE_SIZE)); + } + + ret |= lspcon_i2c_spi_enable_write_protection(fd); + ret |= lspcon_i2c_spi_disable_hw_write(fd); + + return ret; +} + +static int lspcon_i2c_spi_write_aai(struct flashctx *flash, const uint8_t *buf, + unsigned int start, unsigned int len) +{ + msg_perr("Error: AAI write function is not supported.\n"); + return FUNCTION_ERR; +} + +static const struct spi_master spi_master_i2c_lspcon = { + .max_data_read = 256, + .max_data_write = 256, + .command = lspcon_i2c_spi_send_command, + .multicommand = default_spi_send_multicommand, + .read = lspcon_i2c_spi_read, + .write_256 = lspcon_i2c_spi_write_256, + .write_aai = lspcon_i2c_spi_write_aai, +}; + +/* TODO: MPU still stop at this point, probably need to reset it. */ +static int lspcon_i2c_spi_shutdown(void *data) +{ + int ret = 0; + int fd = ((struct lspcon_i2c_spi_data *)data)->fd; + ret |= lspcon_i2c_spi_enable_write_protection(fd); + ret |= lspcon_i2c_spi_toggle_register_protection(fd, 0); + i2c_close(fd); + free(data); + + return ret; +} + +/* TODO: remove this out of the specific spi master implementation. */ +static int get_bus() +{ + char *bus_str = extract_programmer_param("bus"); + int ret = FUNCTION_ERR; + if (bus_str) { + char *bus_suffix; + errno = 0; + int bus = (int)strtol(bus_str, &bus_suffix, 10); + if (errno != 0 || bus_str == bus_suffix) { + msg_perr("Error: Could not convert 'bus'.\n"); + goto get_bus_done; + } + + if (bus < 0 || bus > 255) { + msg_perr("Error: Value for 'bus' is out of range(0-255).\n"); + goto get_bus_done; + } + + if (strlen(bus_suffix) > 0) { + msg_perr("Error: Garbage following 'bus' value.\n"); + goto get_bus_done; + } + + msg_pinfo("Using i2c bus %i.\n", bus); + ret = bus; + goto get_bus_done; + } else { + msg_perr("Error: Bus number not specified.\n"); + } +get_bus_done: + if (bus_str) + free(bus_str); + + return ret; +} + +static int register_lspcon_i2c_spi_master(void *ptr) +{ + struct spi_master mst = spi_master_i2c_lspcon; + mst.data = ptr; + + return register_spi_master(&mst); +} + +int lspcon_i2c_spi_init(void) +{ + int lspcon_i2c_spi_bus = get_bus(); + if (lspcon_i2c_spi_bus < 0) + return FUNCTION_ERR; + + int ret = 0; + int fd = i2c_open(lspcon_i2c_spi_bus, REGISTER_ADDRESS, 0); + if (fd < 0) + return fd; + + ret |= lspcon_i2c_spi_reset_mpu_stop(fd); + if (ret) + return ret; + + struct lspcon_i2c_spi_data data = { fd }; + void *data_ptr = calloc(1, sizeof(data)); + if (!data_ptr) { + msg_perr("Unable to allocate space for extra spi master data.\n"); + return FUNCTION_ERR; + } + + memcpy(data_ptr, &data, sizeof(data)); + ret |= register_shutdown(lspcon_i2c_spi_shutdown, data_ptr); + ret |= register_lspcon_i2c_spi_master(data_ptr); + + return ret; +} diff --git a/meson.build b/meson.build index b586d9a..7494c51 100644 --- a/meson.build +++ b/meson.build @@ -63,6 +63,7 @@ config_serprog = get_option('config_serprog') config_usbblaster_spi = get_option('config_usbblaster_spi') config_stlinkv3_spi = get_option('config_stlinkv3_spi') +config_lspcon_i2c_spi = get_option('config_lspcon_i2c_spi') config_linux_i2c_helper = get_option('config_linux_i2c_helper') cargs = [] @@ -284,6 +285,10 @@ srcs += 'stlinkv3_spi.c' cargs += '-DCONFIG_STLINKV3_SPI=1' endif +if config_lspcon_i2c_spi + srcs += 'lspcon_i2c_spi.c' + cargs += '-DCONFIG_LSPCON_I2C_SPI=1' +endif # bitbanging SPI infrastructure if config_bitbang_spi diff --git a/meson_options.txt b/meson_options.txt index ff4a786..e4b4fa9 100644 --- a/meson_options.txt +++ b/meson_options.txt @@ -35,4 +35,5 @@ option('config_serprog', type : 'boolean', value : true, description : 'serprog') option('config_usbblaster_spi', type : 'boolean', value : true, description : 'Altera USB-Blaster dongles') option('config_stlinkv3_spi', type : 'boolean', value : true, description : 'STMicroelectronics STLINK-V3') +option('config_lspcon_i2c_spi', type : 'boolean', value : true, description : 'SPI control from I2C bus') option('config_linux_i2c_helper', type: 'boolean', value : true, description : 'Linux I2C control') diff --git a/programmer.h b/programmer.h index 08500c6..d47caf3 100644 --- a/programmer.h +++ b/programmer.h @@ -130,6 +130,9 @@ #if CONFIG_STLINKV3_SPI == 1 PROGRAMMER_STLINKV3_SPI, #endif +#if CONFIG_LSPCON_I2C_SPI == 1 + PROGRAMMER_LSPCON_I2C_SPI, +#endif PROGRAMMER_INVALID /* This must always be the last entry. */ }; @@ -810,4 +813,7 @@ struct libusb_device_handle *usb_dev_get_by_vid_pid_number( struct libusb_context *usb_ctx, uint16_t vid, uint16_t pid, unsigned int num); +/* lspcon_i2c_spi.c */ +int lspcon_i2c_spi_init(void); + #endif /* !__PROGRAMMER_H__ */ -- To view, visit https://review.coreboot.org/c/flashrom/+/39687 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I039e683252cfaf1ffef8694a3e8081b1b6b944f7 Gerrit-Change-Number: 39687 Gerrit-PatchSet: 1 Gerrit-Owner: Shiyu Sun <sshiyu(a)google.com> Gerrit-MessageType: newchange

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flashrom-gerrit April 2020