Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/40470 )
Change subject: lspcon_i2c_spi.c: Clean up some unnecessary indirection
......................................................................
Patch Set 2:
> Patch Set 1: Code-Review+1
>
> Needs a rebase
To re-trigger the buildbot? Done.
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Gerrit-Change-Number: 40470
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Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/40470 )
Change subject: lspcon_i2c_spi.c: Clean up some unnecessary indirection
......................................................................
Patch Set 1: Code-Review+1
Needs a rebase
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Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/40401 )
Change subject: chipset_enable.c: Disable SPI on ICH7 if booted from LPC
......................................................................
chipset_enable.c: Disable SPI on ICH7 if booted from LPC
Commit 92d6a86 ("Refactor Intel Chipset Enables") eliminated a check
to disable SPI when ICH7 has booted from LPC, as the hardware does not
support it. Therefore, when flashrom probes the SPI bus, it times out
waiting for the hardware to react, for each and every SPI flash chip.
This results in very long delays and countless instances of the error:
Error: SCIP never cleared!
To prevent this, bring back part of the lost check. Probing for LPC and
FWH when booted from SPI does not seem to cause any problems on desktop
mainboards with ICH7, so don't disable LPC nor FWH if that is the case.
UNTESTED.
Change-Id: I5e59e66a2dd16b07f2dca410997fce38ab9c8fd1
Signed-off-by: Angel Pons <th3fanbus(a)gmail.com>
---
M chipset_enable.c
1 file changed, 8 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/01/40401/1
diff --git a/chipset_enable.c b/chipset_enable.c
index 36d0dbe..783bb94 100644
--- a/chipset_enable.c
+++ b/chipset_enable.c
@@ -757,6 +757,14 @@
if (ret_fwh == ERROR_FATAL)
return ret_fwh;
+ /*
+ * It seems that the ICH7 does not support SPI and LPC chips at the same time. When booted
+ * from LPC, the SCIP bit will never clear, which causes long delays and many error messages.
+ * To avoid this, we will not enable SPI on ICH7 when the southbridge is strapped to LPC.
+ */
+ if (ich_generation == CHIPSET_ICH7 && (boot_buses & BUS_LPC))
+ return 0;
+
/* SPIBAR is at RCRB+0x3020 for ICH[78], Tunnel Creek and Centerton, and RCRB+0x3800 for ICH9. */
uint16_t spibar_offset;
switch (ich_generation) {
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HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/40328 )
Change subject: Hide redondant 'Error: SCIP never cleared!' message
......................................................................
Hide redondant 'Error: SCIP never cleared!' message
This will hide redondant 'Error: SCIP never cleared!' messahe on ICH7.
https://paste.flashrom.org/view.php?id=3282
Note that this will take a very long time in comparison with v0.9.7-r1711 version.
current version gives:
time ./flashrom -p internal
flashrom v1.2-24-gf572b50-dirty on Linux 5.4.0-4-amd64 (x86_64)
flashrom is free software, get the source code at https://flashrom.org
Using clock_gettime for delay loops (clk_id: 1, resolution: 1ns).
Found chipset "Intel ICH7/ICH7R".
Enabling flash write... OK.
Found SST flash chip "SST49LF004A/B" (512 kB, FWH) mapped at physical address 0x00000000fff80000.
No operations were specified.
real 0m31,031s
user 0m10,079s
sys 0m20,785s
and old version v0.9.7-r171 will go faster:
time ./flashrom -p internal
flashrom v0.9.7-r1711 on Linux 5.4.0-4-amd64 (x86_64)
flashrom is free software, get the source code at http://www.flashrom.org
Calibrating delay loop... OK.
sh: 1: dmidecode: not found
dmidecode execution unsuccessful - continuing without DMI info
Found chipset "Intel ICH7/ICH7R". Enabling flash write... OK.
Found SST flash chip "SST49LF004A/B" (512 kB, FWH) at physical address 0xfff80000.
No operations were specified.
real 0m0,861s
user 0m0,844s
sys 0m0,008s
Change-Id: I0795653bd9ababccf666ed8af0c9bff22853371d
Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr>
---
M ichspi.c
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/28/40328/1
diff --git a/ichspi.c b/ichspi.c
index 12ee126..19fc29e 100644
--- a/ichspi.c
+++ b/ichspi.c
@@ -852,7 +852,7 @@
programmer_delay(10);
}
if (!timeout) {
- msg_perr("Error: SCIP never cleared!\n");
+ msg_pdbg("Error: SCIP never cleared!\n");
return 1;
}
--
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Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/39972 )
Change subject: cli_classic.c: Prevent memory leak
......................................................................
cli_classic.c: Prevent memory leak
If the `--flash-contents` switch is specified more than once, it will
result in a memory leak. Therefore, allow this option only once.
Change-Id: I530933c9a6431580fe4645396bb363939472a80a
Signed-off-by: Angel Pons <th3fanbus(a)gmail.com>
---
M cli_classic.c
1 file changed, 3 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/72/39972/1
diff --git a/cli_classic.c b/cli_classic.c
index 73cc417..967ff50 100644
--- a/cli_classic.c
+++ b/cli_classic.c
@@ -273,6 +273,9 @@
}
break;
case OPTION_FLASH_CONTENTS:
+ if (referencefile)
+ cli_classic_abort_usage("Error: --flash-contents specified more than once."
+ "Aborting.\n");
referencefile = strdup(optarg);
break;
case OPTION_FLASH_NAME:
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Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/40275 )
Change subject: flashchips: Add support for Winbond W25Q64JW
......................................................................
Patch Set 10:
> Will this CL be updated to chromium gerrit?
It's not done automatically. Please rebase your change in chromium and add the link to here in its description comment (and make it clear this is from upstream) and get review again.
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Scott Chao has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/40275 )
Change subject: flashchips: Add support for Winbond W25Q64JW
......................................................................
Patch Set 10:
Will this CL be updated to chromium gerrit?
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Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/39640 )
Change subject: Copy Verified label from coreboot
......................................................................
Patch Set 3: Verified+1
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