April 2020 - flashrom-gerrit - mail.coreboot.org

Change in flashrom[master]: Initial Realtek MST i2c_spi support
by Edward O'Callaghan (Code Review) 04 May '20

04 May '20

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/40667 ) Change subject: Initial Realtek MST i2c_spi support ...................................................................... Initial Realtek MST i2c_spi support NOT-FOR-MERGE. Good news everyone - ID/SZ and READ works now. cleanups++. Change-Id: I892e0be776fe605e69fb39c77abf3016591d7123 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M flashrom.c M meson.build M meson_options.txt M programmer.h A realtek_mst_i2c_spi.c 5 files changed, 454 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/67/40667/1 diff --git a/flashrom.c b/flashrom.c index 4224637..e58c4b7 100644 --- a/flashrom.c +++ b/flashrom.c @@ -401,6 +401,18 @@ }, #endif +#if CONFIG_REALTEK_MST_I2C_SPI == 1 + { + .name = "realtek_mst_i2c_spi", + .type = OTHER, + .devs.note = "Device files /dev/i2c-*.\n", + .init = realtek_mst_i2c_spi_init, + .map_flash_region = fallback_map, + .unmap_flash_region = fallback_unmap, + .delay = internal_delay, + }, +#endif + #if CONFIG_USBBLASTER_SPI == 1 { .name = "usbblaster_spi", diff --git a/meson.build b/meson.build index 699370a..5d8e630 100644 --- a/meson.build +++ b/meson.build @@ -64,6 +64,7 @@ config_usbblaster_spi = get_option('config_usbblaster_spi') config_stlinkv3_spi = get_option('config_stlinkv3_spi') config_lspcon_i2c_spi = get_option('config_lspcon_i2c_spi') +config_realtek_mst_i2c_spi = get_option('config_realtek_mst_i2c_spi') cargs = [] deps = [] @@ -288,6 +289,10 @@ srcs += 'lspcon_i2c_spi.c' cargs += '-DCONFIG_LSPCON_I2C_SPI=1' endif +if config_realtek_mst_i2c_spi + srcs += 'realtek_mst_i2c_spi.c' + cargs += '-DCONFIG_REALTEK_MST_I2C_SPI=1' +endif # bitbanging SPI infrastructure if config_bitbang_spi diff --git a/meson_options.txt b/meson_options.txt index a103dc6..ac48e4e 100644 --- a/meson_options.txt +++ b/meson_options.txt @@ -36,3 +36,4 @@ option('config_usbblaster_spi', type : 'boolean', value : true, description : 'Altera USB-Blaster dongles') option('config_stlinkv3_spi', type : 'boolean', value : true, description : 'STMicroelectronics STLINK-V3') option('config_lspcon_i2c_spi', type : 'boolean', value : false, description : 'Parade lspcon USB-C to HDMI protocol translator') +option('config_realtek_mst_i2c_spi', type : 'boolean', value : true, description : 'Realtek MultiStream Transport MST') diff --git a/programmer.h b/programmer.h index f6c5399..61e53da 100644 --- a/programmer.h +++ b/programmer.h @@ -133,6 +133,9 @@ #if CONFIG_LSPCON_I2C_SPI == 1 PROGRAMMER_LSPCON_I2C_SPI, #endif +#if CONFIG_REALTEK_MST_I2C_SPI == 1 + PROGRAMMER_REALTEK_MST_I2C_SPI, +#endif PROGRAMMER_INVALID /* This must always be the last entry. */ }; @@ -819,4 +822,9 @@ int lspcon_i2c_spi_init(void); #endif +/* realtek_mst_i2c_spi.c */ +#if CONFIG_REALTEK_MST_I2C_SPI == 1 +int realtek_mst_i2c_spi_init(void); +#endif + #endif /* !__PROGRAMMER_H__ */ diff --git a/realtek_mst_i2c_spi.c b/realtek_mst_i2c_spi.c new file mode 100644 index 0000000..16e5507 --- /dev/null +++ b/realtek_mst_i2c_spi.c @@ -0,0 +1,428 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2020 The Chromium OS Authors + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdlib.h> +#include <stdint.h> +#include <stdio.h> +#include <string.h> +#include <time.h> +#include <errno.h> + +#include "programmer.h" +#include "spi.h" +#include "i2c_helper.h" + + +#define MCU_I2C_SLAVE_ADDR 0x94 +#define REGISTER_ADDRESS (0x94 >> 1) +#define PAGE_SIZE 256 +#define MAX_SPI_WAIT_RETRIES 1000 + +//opcodes +#define OPCODE_READ 3 +#define OPCODE_WRITE 2 + + +struct realtek_mst_i2c_spi_data { + int fd; +}; + +static int realtek_mst_i2c_spi_write_data(int fd, uint16_t addr, void *buf, uint16_t len) +{ + i2c_buffer_t data; + if (i2c_buffer_t_fill(&data, buf, len)) + return SPI_GENERIC_ERROR; + + return i2c_write(fd, addr, &data) == len ? 0 : SPI_GENERIC_ERROR; +} + +static int realtek_mst_i2c_spi_read_data(int fd, uint16_t addr, void *buf, uint16_t len) +{ + i2c_buffer_t data; + if (i2c_buffer_t_fill(&data, buf, len)) + return SPI_GENERIC_ERROR; + + return i2c_read(fd, addr, &data) == len ? 0 : SPI_GENERIC_ERROR; +} + +static int get_fd_from_context(const struct flashctx *flash) +{ + if (!flash || !flash->mst || !flash->mst->spi.data) { + msg_perr("Unable to extract fd from flash context.\n"); + return SPI_GENERIC_ERROR; + } + const struct realtek_mst_i2c_spi_data *data = + (const struct realtek_mst_i2c_spi_data *)flash->mst->spi.data; + + return data->fd; +} + +static int realtek_mst_i2c_spi_write_register(int fd, uint8_t reg, uint8_t value) +{ + uint8_t command[] = { reg, value }; + return realtek_mst_i2c_spi_write_data(fd, REGISTER_ADDRESS, command, 2); +} + +static int realtek_mst_i2c_spi_read_register(int fd, uint8_t reg, uint8_t *value) +{ + uint8_t command[] = { reg }; + int ret = realtek_mst_i2c_spi_write_data(fd, REGISTER_ADDRESS, command, 1); + ret |= realtek_mst_i2c_spi_read_data(fd, REGISTER_ADDRESS, value, 1); + + return ret ? SPI_GENERIC_ERROR : 0; +} + +static int realtek_mst_i2c_spi_wait_command_done(int fd, unsigned int offset, int mask) +{ + uint8_t val; + int tried = 0; + int ret = 0; + do { + ret |= realtek_mst_i2c_spi_read_register(fd, offset, &val); + } while(!ret && (val & mask) && ++tried < MAX_SPI_WAIT_RETRIES); + + if (tried == MAX_SPI_WAIT_RETRIES) { + msg_perr("%s: Time out on sending command.\n", __func__); + return -MAX_SPI_WAIT_RETRIES; + } + + return (val & mask) ? SPI_GENERIC_ERROR : ret; +} + +static int realtek_mst_i2c_spi_enter_isp_mode(int fd) +{ + // 0xFF6F = 0x80; + int ret = realtek_mst_i2c_spi_write_register(fd, 0x6F, 0x80); // enter isp mode + + // set internal osc divider register to default to speed up MCU + // 0x06A0 = 0x74 + ret |= realtek_mst_i2c_spi_write_register(fd, 0xF4, 0x9F); + ret |= realtek_mst_i2c_spi_write_register(fd, 0xF5, 0x06); + ret |= realtek_mst_i2c_spi_write_register(fd, 0xF4, 0xA0); + ret |= realtek_mst_i2c_spi_write_register(fd, 0xF5, 0x74); + + return ret; +} + +static int realtek_mst_i2c_spi_reset_mpu(int fd) +{ + int ret = 0; + // 0xFFEE[1] = 1; + uint8_t val = 0; + ret |= realtek_mst_i2c_spi_read_register(fd, 0xEE, &val); + ret |= realtek_mst_i2c_spi_write_register(fd, 0xEE, (val & 0xFD) | 0x02); + return ret; +} + +#if 0 +static int realtek_mst_i2c_spi_set_defaults(int fd) +{ + // 0xFF1B = 0x02; + int ret = realtek_mst_i2c_spi_write_register(fd, 0x1B, 0x02); + ret = realtek_mst_i2c_spi_write_register(fd, 0x1C, 0x30); + ret = realtek_mst_i2c_spi_write_register(fd, 0x1D, 0x1C); + ret = realtek_mst_i2c_spi_write_register(fd, 0x1E, 0x02); + ret = realtek_mst_i2c_spi_write_register(fd, 0x1F, 0x00); + + ret = realtek_mst_i2c_spi_write_register(fd, 0x20, 0x1C); + ret = realtek_mst_i2c_spi_write_register(fd, 0x2C, 0x02); + ret = realtek_mst_i2c_spi_write_register(fd, 0x2D, 0x00); + ret = realtek_mst_i2c_spi_write_register(fd, 0x2E, 0x1C); + + ret = realtek_mst_i2c_spi_write_register(fd, 0x62, 0x06); + ret = realtek_mst_i2c_spi_write_register(fd, 0x6A, 0x03); + ret = realtek_mst_i2c_spi_write_register(fd, 0x6B, 0x0B); + ret = realtek_mst_i2c_spi_write_register(fd, 0x6C, 0x00); + + ret = realtek_mst_i2c_spi_write_register(fd, 0xED, 0x88); + ret = realtek_mst_i2c_spi_write_register(fd, 0xEE, 0x04); + + return ret; +} +#endif + +static int realtek_mst_i2c_spi_disable_protection(int fd) +{ + int ret = 0; + uint8_t val = 0; + // 0xAB[2:0] = b001 + + ret |= realtek_mst_i2c_spi_write_register(fd, 0xF4, 0x9F); + ret |= realtek_mst_i2c_spi_write_register(fd, 0xF5, 0x10); + ret |= realtek_mst_i2c_spi_write_register(fd, 0xF4, 0xAB); + + ret |= realtek_mst_i2c_spi_read_register(fd, 0xF5, &val); + + ret |= realtek_mst_i2c_spi_write_register(fd, 0xF4, 0x9F); + ret |= realtek_mst_i2c_spi_write_register(fd, 0xF5, 0x10); + ret |= realtek_mst_i2c_spi_write_register(fd, 0xF4, 0xAB); + + ret |= realtek_mst_i2c_spi_write_register(fd, 0xF5, (val & 0xF8) | 0x01); + + return ret; +} + +static int realtek_mst_i2c_spi_send_command(const struct flashctx *flash, + unsigned int writecnt, unsigned int readcnt, + const unsigned char *writearr, + unsigned char *readarr) +{ + unsigned i; + int ret = 0; + + if (writecnt > 4 || readcnt > 3 || writecnt == 0) { + //msg_perr("%s: Invalid read/write count for send command.\n", __func__); + return SPI_GENERIC_ERROR; + } + //printf("%s: writearr[0]=0x%x\n", __func__, writearr[0]); + + int fd = get_fd_from_context(flash); + if (fd < 0) + return SPI_GENERIC_ERROR; + + /* First byte of writearr should be the command value, followed by the value to write. */ + // 0xFF60 = cmd; + writecnt--; + uint8_t ctrl_reg_val = (writecnt << 3) | (readcnt << 1) | (2 << 5); + ret |= realtek_mst_i2c_spi_write_register(fd, 0x60, ctrl_reg_val); + ret |= realtek_mst_i2c_spi_write_register(fd, 0x61, writearr[0]); + + for (i = 0; i < writecnt; ++i) + ret |= realtek_mst_i2c_spi_write_register(fd, 0x64 + i, writearr[i + 1]); + ret |= realtek_mst_i2c_spi_write_register(fd, 0x60, ctrl_reg_val | 0x1); + if (ret) + return ret; + + ret = realtek_mst_i2c_spi_wait_command_done(fd, 0x60, 0x01); + if (ret) + return ret; + + for (i = 0; i < readcnt; ++i) + ret |= realtek_mst_i2c_spi_read_register(fd, 0x67 + i, &readarr[i]); + + //for (i = 0; i< readcnt; i++) + // printf("DEBUG: readarr[%d]=0x%02x\n", i, readarr[i]); + + return ret; +} + +static int realtek_mst_i2c_spi_map_page(int fd, uint8_t block_idx, uint8_t page_idx, uint8_t byte_idx) +{ + int ret = 0; + ret |= realtek_mst_i2c_spi_write_register(fd, 0x64, block_idx); + ret |= realtek_mst_i2c_spi_write_register(fd, 0x65, page_idx); + ret |= realtek_mst_i2c_spi_write_register(fd, 0x66, byte_idx); + + return ret ? SPI_GENERIC_ERROR : 0; +} + +static int realtek_mst_i2c_spi_read(struct flashctx *flash, uint8_t *buf, + unsigned int start, unsigned int len) +{ + unsigned i; + int ret = 0; + + if (start & 0xff) + return default_spi_read(flash, buf, start, len); + + int fd = get_fd_from_context(flash); + if (fd < 0) + return SPI_GENERIC_ERROR; + + start--; + ret |= realtek_mst_i2c_spi_write_register(fd, 0x60, 0x46); // ** + ret |= realtek_mst_i2c_spi_write_register(fd, 0x61, OPCODE_READ); + uint8_t block_idx = start >> 16; + uint8_t page_idx = start >> 8; + uint8_t byte_idx = start; + ret |= realtek_mst_i2c_spi_map_page(fd, block_idx, page_idx, byte_idx); + ret |= realtek_mst_i2c_spi_write_register(fd, 0x6a, 0x03); + ret |= realtek_mst_i2c_spi_write_register(fd, 0x60, 0x47); // ** + if (ret) + return ret; + + ret = realtek_mst_i2c_spi_wait_command_done(fd, 0x60, 0x01); + if (ret) + return ret; + + uint8_t dummy; + realtek_mst_i2c_spi_read_register(fd, 0x70, &dummy); + + for (i = 0; i < len; i += PAGE_SIZE) { + ret |= realtek_mst_i2c_spi_read_data(fd, REGISTER_ADDRESS, + buf + i, min(len - i, PAGE_SIZE)); + if (ret) + return ret; + } + + return ret; +} + +static int realtek_mst_i2c_spi_write_256(struct flashctx *flash, const uint8_t *buf, + unsigned int start, unsigned int len) +{ + unsigned i; + int ret = 0; + + if (start & 0xff) + return default_spi_write_256(flash, buf, start, len); + + int fd = get_fd_from_context(flash); + if (fd < 0) + return SPI_GENERIC_ERROR; + + ret = realtek_mst_i2c_spi_disable_protection(fd); + if (ret) + return ret; + + start--; + ret |= realtek_mst_i2c_spi_write_register(fd, 0x60, 0x46); // ** + ret |= realtek_mst_i2c_spi_write_register(fd, 0x61, OPCODE_WRITE); + uint8_t block_idx = start >> 16; + uint8_t page_idx = start >> 8; + uint8_t byte_idx = start; + ret |= realtek_mst_i2c_spi_map_page(fd, block_idx, page_idx, byte_idx); + ret |= realtek_mst_i2c_spi_write_register(fd, 0x6a, 0x03); + ret |= realtek_mst_i2c_spi_write_register(fd, 0x60, 0x47); // ** + if (ret) + return ret; + + ret = realtek_mst_i2c_spi_wait_command_done(fd, 0x60, 0x01); + if (ret) + return ret; + + // XXX?? + //uint8_t dummy; + //realtek_mst_i2c_spi_read_register(fd, 0x70, &dummy); + + for (i = 0; i < len; i += PAGE_SIZE) { + ret |= realtek_mst_i2c_spi_write_data(fd, REGISTER_ADDRESS, + (uint8_t *)buf + i, min(len - i, PAGE_SIZE)); + if (ret) + return ret; + } + +// ret |= realtek_mst_i2c_spi_enable_write_protection(fd); +// ret |= realtek_mst_i2c_spi_toggle_register_protection(fd, 0); + + return ret; +} + +static int realtek_mst_i2c_spi_write_aai(struct flashctx *flash, const uint8_t *buf, + unsigned int start, unsigned int len) +{ + msg_perr("%s: AAI write function is not supported.\n", __func__); + return SPI_GENERIC_ERROR; +} + +static struct spi_master spi_master_i2c_realtek_mst = { + .max_data_read = 16, + .max_data_write = 8, + .command = realtek_mst_i2c_spi_send_command, + .multicommand = default_spi_send_multicommand, + .read = realtek_mst_i2c_spi_read, + .write_256 = realtek_mst_i2c_spi_write_256, + .write_aai = realtek_mst_i2c_spi_write_aai, +}; + +static int realtek_mst_i2c_spi_shutdown(void *data) +{ + int ret = 0; + struct realtek_mst_i2c_spi_data *realtek_mst_data = + (struct realtek_mst_i2c_spi_data *)data; + int fd = realtek_mst_data->fd; + ret |= realtek_mst_i2c_spi_reset_mpu(fd); + i2c_close(fd); + free(data); + + return ret; +} + +/* TODO: remove this out of the specific SPI master implementation. */ +static int get_bus(void) +{ + char *bus_str = extract_programmer_param("bus"); + int ret = SPI_GENERIC_ERROR; + if (bus_str) { + char *bus_suffix; + errno = 0; + int bus = (int)strtol(bus_str, &bus_suffix, 10); + if (errno != 0 || bus_str == bus_suffix) { + msg_perr("%s: Could not convert 'bus'.\n", __func__); + goto get_bus_done; + } + + if (bus < 0 || bus > 255) { + msg_perr("%s: Value for 'bus' is out of range(0-255).\n", __func__); + goto get_bus_done; + } + + if (strlen(bus_suffix) > 0) { + msg_perr("%s: Garbage following 'bus' value.\n", __func__); + goto get_bus_done; + } + + msg_pinfo("Using i2c bus %i.\n", bus); + ret = bus; + goto get_bus_done; + } else { + msg_perr("%s: Bus number not specified.\n", __func__); + } +get_bus_done: + if (bus_str) + free(bus_str); + + return ret; +} + +int realtek_mst_i2c_spi_init(void) +{ + int realtek_mst_i2c_spi_bus = get_bus(); + if (realtek_mst_i2c_spi_bus < 0) + return SPI_GENERIC_ERROR; + + int ret = 0; + int fd = i2c_open(realtek_mst_i2c_spi_bus, REGISTER_ADDRESS, 0); + if (fd < 0) + return fd; + + /* XXX ensure we are in a known state before entering ISP mode */ + ret |= realtek_mst_i2c_spi_reset_mpu(fd); + if (ret) + return ret; + + ret |= realtek_mst_i2c_spi_enter_isp_mode(fd); + if (ret) + return ret; +// XXX: maybe make into a mode:defaults cli param? +// ret |= realtek_mst_i2c_spi_set_defaults(fd); +// if (ret) +// return ret; + + struct realtek_mst_i2c_spi_data *data = calloc(1, sizeof(struct realtek_mst_i2c_spi_data)); + if (!data) { + msg_perr("Unable to allocate space for extra SPI master data.\n"); + return SPI_GENERIC_ERROR; + } + + data->fd = fd; + ret |= register_shutdown(realtek_mst_i2c_spi_shutdown, data); + + spi_master_i2c_realtek_mst.data = data; + ret |= register_spi_master(&spi_master_i2c_realtek_mst); + + return ret; +} -- To view, visit https://review.coreboot.org/c/flashrom/+/40667 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I892e0be776fe605e69fb39c77abf3016591d7123 Gerrit-Change-Number: 40667 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

5 20

Change in flashrom[master]: libflashrom.c: Use correct type for sizeof
by Angel Pons (Code Review) 03 May '20

03 May '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/39973 ) Change subject: libflashrom.c: Use correct type for sizeof ...................................................................... libflashrom.c: Use correct type for sizeof As we want to allocate an array of `flashrom_board_info` structs, use that type in sizeof. This did not cause problems as `board_info` was at least as big as `flashrom_board_info`, but nothing guarantees it. Change-Id: I66e875d54c9a7cc59898b072b052282b0b5cbb2f Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M libflashrom.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/73/39973/1 diff --git a/libflashrom.c b/libflashrom.c index 0dec22e..ab7e364 100644 --- a/libflashrom.c +++ b/libflashrom.c @@ -182,7 +182,7 @@ ++boards_known_size; struct flashrom_board_info *supported_boards = - malloc(boards_known_size * sizeof(*binfo)); + malloc(boards_known_size * sizeof(struct flashrom_board_info)); if (supported_boards != NULL) { for (; i < boards_known_size; ++i) { -- To view, visit https://review.coreboot.org/c/flashrom/+/39973 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I66e875d54c9a7cc59898b072b052282b0b5cbb2f Gerrit-Change-Number: 39973 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

5 7

Change in flashrom[master]: chipset_enable.c: Spell `BIOS` in uppercase
by Angel Pons (Code Review) 03 May '20

03 May '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/40857 ) Change subject: chipset_enable.c: Spell `BIOS` in uppercase ...................................................................... chipset_enable.c: Spell `BIOS` in uppercase Change-Id: Ib66547b2b5d77658ab1925e4ad3acfe44e14843c Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M chipset_enable.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/57/40857/1 diff --git a/chipset_enable.c b/chipset_enable.c index 783bb94..632679c 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -354,7 +354,7 @@ msg_pwarn("Warning: BIOS region SMM protection is enabled!\n"); if (new != wanted) - msg_pwarn("Warning: Setting Bios Control at 0x%x from 0x%02x to 0x%02x failed.\n" + msg_pwarn("Warning: Setting BIOS Control at 0x%x from 0x%02x to 0x%02x failed.\n" "New value is 0x%02x.\n", bios_cntl, old, wanted, new); /* Return an error if we could not set the write enable only. */ -- To view, visit https://review.coreboot.org/c/flashrom/+/40857 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ib66547b2b5d77658ab1925e4ad3acfe44e14843c Gerrit-Change-Number: 40857 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

4 5

Change in flashrom[master]: Revert "flashchips: port S25FS(128S) chip from chromiumos"
by Nico Huber (Code Review) 01 May '20

01 May '20

Hello Hung-Te Lin, build bot (Jenkins), Paul Menzel, Stefan Reinauer, David Hendricks, Edward O'Callaghan, Angel Pons, Samir Ibradžić, I'd like you to do a code review. Please visit https://review.coreboot.org/c/flashrom/+/40626 to review the following change. Change subject: Revert "flashchips: port S25FS(128S) chip from chromiumos" ...................................................................... Revert "flashchips: port S25FS(128S) chip from chromiumos" This reverts commit a3519561bd0fb44153bb376322b799000657576f. Breaks support for most SPI flash chips. Doesn't look like it's been reviewed at all. It's too big and too invasive to be reviewed as a single commit. Change-Id: Id2a4593bdb654f8a26957d69d52189ce61621d93 --- M chipdrivers.h M flash.h M flashchips.c M flashchips.h M flashrom.c M spi.h M spi25.c M spi25_statusreg.c 8 files changed, 6 insertions(+), 415 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/26/40626/1 diff --git a/chipdrivers.h b/chipdrivers.h index aa24085..cb1e877 100644 --- a/chipdrivers.h +++ b/chipdrivers.h @@ -35,9 +35,6 @@ int probe_spi_res2(struct flashctx *flash); int probe_spi_res3(struct flashctx *flash); int probe_spi_at25f(struct flashctx *flash); -int probe_spi_big_spansion(struct flashctx *flash); -int s25fs_software_reset(struct flashctx *flash); -int spi_poll_wip(struct flashctx *const flash, const unsigned int poll_delay); int spi_write_enable(struct flashctx *flash); int spi_write_disable(struct flashctx *flash); int spi_block_erase_20(struct flashctx *flash, unsigned int addr, unsigned int blocklen); @@ -52,7 +49,6 @@ int spi_block_erase_c7(struct flashctx *flash, unsigned int addr, unsigned int blocklen); int spi_block_erase_d7(struct flashctx *flash, unsigned int addr, unsigned int blocklen); int spi_block_erase_d8(struct flashctx *flash, unsigned int addr, unsigned int blocklen); -int s25fs_block_erase_d8(struct flashctx *flash, unsigned int addr, unsigned int blocklen); int spi_block_erase_db(struct flashctx *flash, unsigned int addr, unsigned int blocklen); int spi_block_erase_dc(struct flashctx *flash, unsigned int addr, unsigned int blocklen); erasefunc_t *spi_get_erasefn_from_opcode(uint8_t opcode); @@ -64,12 +60,10 @@ int spi_exit_4ba(struct flashctx *flash); int spi_set_extended_address(struct flashctx *, uint8_t addr_high); + /* spi25_statusreg.c */ uint8_t spi_read_status_register(struct flashctx *flash); int spi_write_status_register(struct flashctx *flash, int status); -int s25fs_read_cr(struct flashctx *const flash, uint32_t addr); -int s25fs_write_cr(struct flashctx *const flash, uint32_t addr, uint8_t data); -int s25fs_restore_cr3nv(struct flashctx *const flash, uint8_t cfg); void spi_prettyprint_status_register_bit(uint8_t status, int bit); int spi_prettyprint_status_register_plain(struct flashctx *flash); int spi_prettyprint_status_register_default_welwip(struct flashctx *flash); diff --git a/flash.h b/flash.h index 1ee0f0f..1a9bd9f 100644 --- a/flash.h +++ b/flash.h @@ -54,8 +54,6 @@ #define PRIxPTR_WIDTH ((int)(sizeof(uintptr_t)*2)) int register_shutdown(int (*function) (void *data), void *data); -#define CHIP_RESTORE_CALLBACK int (*func) (struct flashrom_flashctx *flash, uint8_t status) -int register_chip_restore(CHIP_RESTORE_CALLBACK, struct flashrom_flashctx *flash, uint8_t status); int shutdown_free(void *data); void *programmer_map_flash_region(const char *descr, uintptr_t phys_addr, size_t len); void programmer_unmap_flash_region(void *virt_addr, size_t len); @@ -209,7 +207,6 @@ SPI_EDI = 1, } spi_cmd_set; - int (*reset) (struct flashctx *flash); int (*probe) (struct flashctx *flash); /* Delay after "enter/exit ID mode" commands in microseconds. diff --git a/flashchips.c b/flashchips.c index 974ba81..b4006df 100644 --- a/flashchips.c +++ b/flashchips.c @@ -49,7 +49,6 @@ * .eraseblocks[] = Array of { blocksize, blockcount } * .block_erase = Block erase function * } - * .reset = Reset Chip * .printlock = Chip lock status function * .unlock = Chip unlock function * .write = Chip write function @@ -15826,69 +15825,6 @@ { .vendor = "Spansion", - .name = "S25FS128S Large Sectors", - .bustype = BUS_SPI, - .manufacture_id = SPANSION_ID, - .model_id = SPANSION_S25FS128S_L, - .total_size = 16384, - .page_size = 256, - .feature_bits = FEATURE_WRSR_WREN, - .tested = TEST_UNTESTED, - .probe = probe_spi_big_spansion, - .probe_timing = TIMING_ZERO, - .block_erasers = - { - { - .eraseblocks = { {64 * 1024, 256} }, - .block_erase = s25fs_block_erase_d8, - }, { - .eraseblocks = { {16 * 1024 * 1024, 1} }, - .block_erase = spi_block_erase_60, - }, { - .eraseblocks = { {16 * 1024 * 1024, 1} }, - .block_erase = spi_block_erase_c7, - }, - }, - .unlock = spi_disable_blockprotect, - .write = spi_chip_write_256, - .read = spi_chip_read, - .voltage = {1700, 2000}, - }, - - { - .vendor = "Spansion", - .name = "S25FS128S Small Sectors", - .bustype = BUS_SPI, - .manufacture_id = SPANSION_ID, - .model_id = SPANSION_S25FS128S_S, - .total_size = 16384, - .page_size = 256, - .feature_bits = FEATURE_WRSR_WREN, - .tested = TEST_OK_PREW, - .probe = probe_spi_big_spansion, - .probe_timing = TIMING_ZERO, - .block_erasers = - { - { - .eraseblocks = { {64 * 1024, 256} }, - .block_erase = s25fs_block_erase_d8, - }, { - .eraseblocks = { {16 * 1024 * 1024, 1} }, - .block_erase = spi_block_erase_60, - }, { - .eraseblocks = { {16 * 1024 * 1024, 1} }, - .block_erase = spi_block_erase_c7, - }, - }, - .reset = s25fs_software_reset, - .unlock = spi_disable_blockprotect, - .write = spi_chip_write_256, - .read = spi_chip_read, - .voltage = {1700, 2000}, - }, - - { - .vendor = "Spansion", .name = "S25FL129P......1", /* uniform 256 kB sectors */ .bustype = BUS_SPI, .manufacture_id = SPANSION_ID, diff --git a/flashchips.h b/flashchips.h index 0c77d1d..e5ef390 100644 --- a/flashchips.h +++ b/flashchips.h @@ -642,8 +642,6 @@ #define SPANSION_S25FL032A 0x0215 /* Same as S25FL032P, but the latter supports EDI and CFI */ #define SPANSION_S25FL064A 0x0216 /* Same as S25FL064P, but the latter supports EDI and CFI */ #define SPANSION_S25FL128 0x2018 /* Same ID for various S25FL127S, S25FL128P, S25FL128S and S25FL129P (including dual-die S70FL256P) variants (EDI supported) */ -#define SPANSION_S25FS128S_L 0x20180081 /* Large sectors. */ -#define SPANSION_S25FS128S_S 0x20180181 /* Small sectors. */ #define SPANSION_S25FL256 0x0219 #define SPANSION_S25FL512 0x0220 #define SPANSION_S25FL204 0x4013 diff --git a/flashrom.c b/flashrom.c index 4224637..07ce734 100644 --- a/flashrom.c +++ b/flashrom.c @@ -500,14 +500,6 @@ {0}, /* This entry corresponds to PROGRAMMER_INVALID. */ }; -#define CHIP_RESTORE_MAXFN 4 -static int chip_restore_fn_count = 0; -static struct chip_restore_func_data { - CHIP_RESTORE_CALLBACK; - struct flashctx *flash; - uint8_t status; -} chip_restore_fn[CHIP_RESTORE_MAXFN]; - #define SHUTDOWN_MAXFN 32 static int shutdown_fn_count = 0; /** @private */ @@ -558,23 +550,6 @@ return 0; } -//int register_chip_restore(int (*function) (void *data), void *data) -int register_chip_restore(CHIP_RESTORE_CALLBACK, - struct flashctx *flash, uint8_t status) -{ - if (chip_restore_fn_count >= CHIP_RESTORE_MAXFN) { - msg_perr("Tried to register more than %i chip restore" - " functions.\n", CHIP_RESTORE_MAXFN); - return 1; - } - chip_restore_fn[chip_restore_fn_count].func = func; /* from macro */ - chip_restore_fn[chip_restore_fn_count].flash = flash; - chip_restore_fn[chip_restore_fn_count].status = status; - chip_restore_fn_count++; - - return 0; -} - int programmer_init(enum programmer prog, const char *param) { int ret; diff --git a/spi.h b/spi.h index 12063d7..3f45038 100644 --- a/spi.h +++ b/spi.h @@ -101,7 +101,7 @@ #define JEDEC_BE_C4_OUTSIZE 0x04 #define JEDEC_BE_C4_INSIZE 0x00 -/* Block Erase 0xd8 is supported by EON/Macronix/Spansion chips. */ +/* Block Erase 0xd8 is supported by EON/Macronix chips. */ #define JEDEC_BE_D8 0xd8 #define JEDEC_BE_D8_OUTSIZE 0x04 #define JEDEC_BE_D8_INSIZE 0x00 @@ -116,18 +116,6 @@ #define JEDEC_SE_OUTSIZE 0x04 #define JEDEC_SE_INSIZE 0x00 -/* RADR, WRAR, RSTEN, RST & CR3NV OPs and timers on Spansion S25FS chips */ -#define CMD_RDAR 0x65 -#define CMD_WRAR 0x71 -#define CMD_WRAR_LEN 5 -#define CMD_RSTEN 0x66 -#define CMD_RST 0x99 -#define CR3NV_ADDR 0x000004 -#define CR3NV_20H_NV (1 << 3) -#define T_W 145 * 1000 /* NV register write time */ -#define T_RPH 35 /* Reset pulse hold time */ -#define T_SE 145 * 1000 /* Sector Erase Time */ - /* Page Erase 0xDB */ #define JEDEC_PE 0xDB #define JEDEC_PE_OUTSIZE 0x04 @@ -141,7 +129,6 @@ /* Status Register Bits */ #define SPI_SR_WIP (0x01 << 0) #define SPI_SR_WEL (0x01 << 1) -#define SPI_SR_ERA_ERR (0x01 << 5) #define SPI_SR_AAI (0x01 << 6) /* Write Status Enable */ diff --git a/spi25.c b/spi25.c index c774f99..2a1d492 100644 --- a/spi25.c +++ b/spi25.c @@ -25,7 +25,6 @@ #include "flashchips.h" #include "chipdrivers.h" #include "programmer.h" -#include "hwaccess.h" #include "spi.h" static int spi_rdid(struct flashctx *flash, unsigned char *readarr, int bytes) @@ -285,155 +284,13 @@ return 0; } -/* Used for probing 'big' Spansion/Cypress S25FS chips */ -int probe_spi_big_spansion(struct flashctx *flash) +static int spi_poll_wip(struct flashctx *const flash, const unsigned int poll_delay) { - static const unsigned char cmd = JEDEC_RDID; - int ret; - unsigned char dev_id[6]; /* We care only about 6 first bytes */ - - ret = spi_send_command(flash, sizeof(cmd), sizeof(dev_id), &cmd, dev_id); - - if (!ret) { - unsigned long i; - - for (i = 0; i < sizeof(dev_id); i++) - msg_gdbg(" 0x%02x", dev_id[i]); - msg_gdbg(".\n"); - - if (dev_id[0] == flash->chip->manufacture_id) { - union { - uint8_t array[4]; - uint32_t whole; - } model_id; - - /* - * The structure of the RDID output is as follows: - * - * offset value meaning - * 00h 01h Manufacturer ID for Spansion - * 01h 20h 128 Mb capacity - * 01h 02h 256 Mb capacity - * 02h 18h 128 Mb capacity - * 02h 19h 256 Mb capacity - * 03h 4Dh Full size of the RDID output (ignored) - * 04h 00h FS: 256-kB physical sectors - * 04h 01h FS: 64-kB physical sectors - * 04h 00h FL: 256-kB physical sectors - * 04h 01h FL: Mix of 64-kB and 4KB overlayed sectors - * 05h 80h FL family - * 05h 81h FS family - * - * Need to use bytes 1, 2, 4, and 5 to properly identify one of eight - * possible chips: - * - * 2 types * 2 possible sizes * 2 possible sector layouts - * - */ - memcpy(model_id.array, dev_id + 1, 2); - memcpy(model_id.array + 2, dev_id + 4, 2); - if (be_to_cpu32(model_id.whole) == flash->chip->model_id) - return 1; - } - } - - return 0; -} - -/* Used for Spansion/Cypress S25F chips */ -static int s25f_legacy_software_reset(struct flashctx *flash) -{ - int result; - struct spi_command cmds[] = { - { - .writecnt = 1, - .writearr = (const unsigned char[]){ CMD_RSTEN }, - .readcnt = 0, - .readarr = NULL, - }, { - .writecnt = 1, - .writearr = (const unsigned char[]){ 0xf0 }, - .readcnt = 0, - .readarr = NULL, - }, { - .writecnt = 0, - .writearr = NULL, - .readcnt = 0, - .readarr = NULL, - }}; - - result = spi_send_multicommand(flash, cmds); - if (result) { - msg_cerr("%s failed during command execution\n", __func__); - return result; - } - /* Reset takes 35us according to data-sheet, double that for safety */ - programmer_delay(T_RPH * 2); - - return 0; -} - -/* Only for Spansion S25FS chips, where legacy reset is disabled by default */ -int s25fs_software_reset(struct flashctx *flash) -{ - int result; - struct spi_command cmds[] = { - { - .writecnt = 1, - .writearr = (const unsigned char[]){ CMD_RSTEN }, - .readcnt = 0, - .readarr = NULL, - }, { - .writecnt = 1, - .writearr = (const unsigned char[]){ CMD_RST }, - .readcnt = 0, - .readarr = NULL, - }, { - .writecnt = 0, - .writearr = NULL, - .readcnt = 0, - .readarr = NULL, - }}; - - msg_cdbg("Force resetting SPI chip.\n"); - result = spi_send_multicommand(flash, cmds); - if (result) { - msg_cerr("%s failed during command execution\n", __func__); - return result; - } - - programmer_delay(T_RPH * 2); - - return 0; -} - -int spi_poll_wip(struct flashctx *const flash, const unsigned int poll_delay) -{ - uint8_t status_reg = spi_read_status_register(flash); - + /* FIXME: We can't tell if spi_read_status_register() failed. */ /* FIXME: We don't time out. */ - while (status_reg & SPI_SR_WIP) { - /* - * The WIP bit on S25F chips remains set to 1 if erase or - * programming errors occur, so we must check for those - * errors here. If an error is encountered, do a software - * reset to clear WIP and other volatile bits, otherwise - * the chip will be unresponsive to further commands. - */ - if (status_reg & SPI_SR_ERA_ERR) { - msg_cerr("Erase error occurred\n"); - s25f_legacy_software_reset(flash); - return -1; - } - if (status_reg & (1 << 6)) { - msg_cerr("Programming error occurred\n"); - s25f_legacy_software_reset(flash); - return -1; - } + while (spi_read_status_register(flash) & SPI_SR_WIP) programmer_delay(poll_delay); - status_reg = spi_read_status_register(flash); - } - + /* FIXME: Check the status register for errors. */ return 0; } @@ -629,73 +486,6 @@ return spi_write_cmd(flash, 0xd8, false, addr, NULL, 0, 100 * 1000); } -/* Used on Spansion/Cypress S25FS chips */ -int s25fs_block_erase_d8(struct flashctx *flash, - unsigned int addr, unsigned int blocklen) -{ - unsigned char cfg; - int result; - static int cr3nv_checked = 0; - - struct spi_command erase_cmds[] = { - { - .writecnt = JEDEC_WREN_OUTSIZE, - .writearr = (const unsigned char[]){ JEDEC_WREN }, - .readcnt = 0, - .readarr = NULL, - }, { - .writecnt = JEDEC_BE_D8_OUTSIZE, - .writearr = (const unsigned char[]){ - JEDEC_BE_D8, - (addr >> 16) & 0xff, - (addr >> 8) & 0xff, - (addr & 0xff) - }, - .readcnt = 0, - .readarr = NULL, - }, { - .writecnt = 0, - .writearr = NULL, - .readcnt = 0, - .readarr = NULL, - }}; - - /* Check if hybrid sector architecture is in use and, if so, - * switch to uniform sectors. */ - if (!cr3nv_checked) { - cfg = s25fs_read_cr(flash, CR3NV_ADDR); - if (!(cfg & CR3NV_20H_NV)) { - s25fs_write_cr(flash, CR3NV_ADDR, cfg | CR3NV_20H_NV); - s25fs_software_reset(flash); - - cfg = s25fs_read_cr(flash, CR3NV_ADDR); - if (!(cfg & CR3NV_20H_NV)) { - msg_cerr("%s: Unable to enable uniform " - "block sizes.\n", __func__); - return 1; - } - - msg_cdbg("\n%s: CR3NV updated (0x%02x -> 0x%02x)\n", - __func__, cfg, - s25fs_read_cr(flash, CR3NV_ADDR)); - /* Restore CR3V when flashrom exits */ - register_chip_restore(s25fs_restore_cr3nv, flash, cfg); - } - - cr3nv_checked = 1; - } - - result = spi_send_multicommand(flash, erase_cmds); - if (result) { - msg_cerr("%s failed during command execution at address 0x%x\n", - __func__, addr); - return result; - } - - programmer_delay(T_SE); - return spi_poll_wip(flash, 1000 * 10); -} - /* Block size is usually * 4k for PMC */ diff --git a/spi25_statusreg.c b/spi25_statusreg.c index aa574d5..8cd5a28 100644 --- a/spi25_statusreg.c +++ b/spi25_statusreg.c @@ -108,89 +108,6 @@ return readarr[0]; } -static int spi_restore_status(struct flashctx *flash, uint8_t status) -{ - msg_cdbg("restoring chip status (0x%02x)\n", status); - return spi_write_status_register(flash, status); -} - -/* 'Read Any Register' used on Spansion/Cypress S25FS chips */ -int s25fs_read_cr(struct flashctx *const flash, uint32_t addr) -{ - int result; - uint8_t cfg; - /* By default, 8 dummy cycles are necessary for variable-latency - commands such as RDAR (see CR2NV[3:0]). */ - unsigned char read_cr_cmd[] = { - CMD_RDAR, - (addr >> 16) & 0xff, - (addr >> 8) & 0xff, - (addr & 0xff), - 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, - }; - - result = spi_send_command(flash, sizeof(read_cr_cmd), 1, read_cr_cmd, &cfg); - if (result) { - msg_cerr("%s failed during command execution at address 0x%x\n", - __func__, addr); - return -1; - } - - return cfg; -} - -/* 'Write Any Register' used on Spansion/Cypress S25FS chips */ -int s25fs_write_cr(struct flashctx *const flash, - uint32_t addr, uint8_t data) -{ - int result; - struct spi_command cmds[] = { - { - .writecnt = JEDEC_WREN_OUTSIZE, - .writearr = (const unsigned char[]){ JEDEC_WREN }, - .readcnt = 0, - .readarr = NULL, - }, { - .writecnt = CMD_WRAR_LEN, - .writearr = (const unsigned char[]){ - CMD_WRAR, - (addr >> 16) & 0xff, - (addr >> 8) & 0xff, - (addr & 0xff), - data - }, - .readcnt = 0, - .readarr = NULL, - }, { - .writecnt = 0, - .writearr = NULL, - .readcnt = 0, - .readarr = NULL, - }}; - - result = spi_send_multicommand(flash, cmds); - if (result) { - msg_cerr("%s failed during command execution at address 0x%x\n", - __func__, addr); - return -1; - } - - programmer_delay(T_W); - return spi_poll_wip(flash, 1000 * 10); -} - -/* Used on Spansion/Cypress S25FS chips */ -int s25fs_restore_cr3nv(struct flashctx *const flash, uint8_t cfg) -{ - int ret = 0; - - msg_cdbg("Restoring CR3NV value to 0x%02x\n", cfg); - ret |= s25fs_write_cr(flash, CR3NV_ADDR, cfg); - ret |= s25fs_software_reset(flash); - return ret; -} - /* A generic block protection disable. * Tests if a protection is enabled with the block protection mask (bp_mask) and returns success otherwise. * Tests if the register bits are locked with the lock_mask (lock_mask). @@ -222,9 +139,6 @@ return 0; } - /* restore status register content upon exit */ - register_chip_restore(spi_restore_status, flash, status); - msg_cdbg("Some block protection in effect, disabling... "); if ((status & lock_mask) != 0) { msg_cdbg("\n\tNeed to disable the register lock first... "); -- To view, visit https://review.coreboot.org/c/flashrom/+/40626 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Id2a4593bdb654f8a26957d69d52189ce61621d93 Gerrit-Change-Number: 40626 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Samir Ibradžić <sibradzic(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newchange

4 12

Change in flashrom[master]: Switch all log prefixed with 'Error:' to '__func__:'
by Shiyu Sun (Code Review) 01 May '20

01 May '20

Shiyu Sun has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/40901 ) Change subject: Switch all log prefixed with 'Error:' to '__func__:' ...................................................................... Switch all log prefixed with 'Error:' to '__func__:' Showing Error is not very informative and switch to function name to make it easy for debug. Change-Id: If3205d8e453cfcd37f725b4fd135fe1221c913c0 Signed-off-by: Shiyu Sun <sshiyu(a)chromium.org> --- M atavia.c M chipset_enable.c M cli_output.c M dediprog.c M digilent_spi.c M dummyflasher.c M flashrom.c M ft2232_spi.c M ichspi.c M it87spi.c M layout.c M libflashrom.c M lspcon_i2c_spi.c M mcp6x_spi.c M mstarddc_spi.c M pcidev.c M pickit2_spi.c M pony_spi.c M rayer_spi.c M sb600spi.c M serprog.c M spi25_statusreg.c 22 files changed, 215 insertions(+), 136 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/01/40901/1 diff --git a/atavia.c b/atavia.c index b407a30..c9dfb4d 100644 --- a/atavia.c +++ b/atavia.c @@ -131,7 +131,8 @@ char *endptr; atavia_offset = (void *)strtoul(arg, &endptr, 0); if (*endptr) { - msg_perr("Error: Invalid offset specified: \"%s\".\n", arg); + msg_perr("%s: Invalid offset specified: \"%s\".\n", + __func__, arg); free(arg); return ERROR_FATAL; } diff --git a/chipset_enable.c b/chipset_enable.c index 783bb94..8ebf2c5 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -403,7 +403,7 @@ case CHIPSET_BAYTRAIL: { uint32_t ilb_base = pci_read_long(dev, 0x50) & 0xfffffe00; /* bits 31:9 */ if (ilb_base == 0) { - msg_perr("Error: Invalid ILB_BASE_ADDRESS\n"); + msg_perr("%s: Invalid ILB_BASE_ADDRESS\n", __func__); return ERROR_FATAL; } ilb = rphysmap("BYT IBASE", ilb_base, 512); @@ -427,21 +427,24 @@ char *idsel = extract_programmer_param("fwh_idsel"); if (idsel && strlen(idsel)) { if (!implemented) { - msg_perr("Error: fwh_idsel= specified, but (yet) unsupported on this chipset.\n"); + msg_perr("%s: fwh_idsel= specified, but (yet) unsupported on this chipset.\n", + __func__); goto idsel_garbage_out; } errno = 0; /* Base 16, nothing else makes sense. */ uint64_t fwh_idsel = (uint64_t)strtoull(idsel, NULL, 16); if (errno) { - msg_perr("Error: fwh_idsel= specified, but value could not be converted.\n"); + msg_perr("%s: fwh_idsel= specified, but value could not be converted.\n", + __func__); goto idsel_garbage_out; } uint64_t fwh_mask = 0xffffffff; if (fwh_sel2 > 0) fwh_mask |= (0xffffULL << 32); if (fwh_idsel & ~fwh_mask) { - msg_perr("Error: fwh_idsel= specified, but value had unused bits set.\n"); + msg_perr("%s: fwh_idsel= specified, but value had unused bits set.\n", + __func__); goto idsel_garbage_out; } uint64_t fwh_idsel_old; @@ -460,7 +463,7 @@ fwh_idsel_old, fwh_idsel); /* FIXME: Decode settings are not changed. */ } else if (idsel) { - msg_perr("Error: fwh_idsel= specified, but no value given.\n"); + msg_perr("%s: fwh_idsel= specified, but no value given.\n", __func__); idsel_garbage_out: free(idsel); return ERROR_FATAL; diff --git a/cli_output.c b/cli_output.c index e12446d..d21216f 100644 --- a/cli_output.c +++ b/cli_output.c @@ -49,7 +49,8 @@ return 1; } if ((logfile = fopen(filename, "w")) == NULL) { - msg_gerr("Error: opening log file \"%s\" failed: %s\n", filename, strerror(errno)); + msg_gerr("%s: opening log file \"%s\" failed: %s\n", + __func__, filename, strerror(errno)); return 1; } return 0; diff --git a/dediprog.c b/dediprog.c index 175e099..1ea3681 100644 --- a/dediprog.c +++ b/dediprog.c @@ -1075,7 +1075,8 @@ } } if (!spispeeds[i].name) { - msg_perr("Error: Invalid spispeed value: '%s'.\n", spispeed); + msg_perr("%s: Invalid spispeed value: '%s'.\n", + __func__, spispeed); free(spispeed); return 1; } @@ -1095,18 +1096,20 @@ if (id_str) { char prefix0, prefix1; if (sscanf(id_str, "%c%c%d", &prefix0, &prefix1, &id) != 3) { - msg_perr("Error: Could not parse dediprog 'id'.\n"); + msg_perr("%s: Could not parse dediprog 'id'.\n", + __func__); msg_perr("Expected a string like SF012345 or DP012345.\n"); free(id_str); return 1; } if (id < 0 || id >= 0x1000000) { - msg_perr("Error: id %s is out of range!\n", id_str); + msg_perr("%s: id %s is out of range!\n", + __func__, id_str); free(id_str); return 1; } if (!(prefix0 == 'S' && prefix1 == 'F') && !(prefix0 == 'D' && prefix1 == 'P')) { - msg_perr("Error: %s is an invalid id!\n", id_str); + msg_perr("%s: %s is an invalid id!\n", __func__, id_str); free(id_str); return 1; } @@ -1118,22 +1121,25 @@ if (device) { char *dev_suffix; if (id != -1) { - msg_perr("Error: Cannot use 'id' and 'device'.\n"); + msg_perr("%s: Cannot use 'id' and 'device'.\n", + __func__); } errno = 0; usedevice = strtol(device, &dev_suffix, 10); if (errno != 0 || device == dev_suffix) { - msg_perr("Error: Could not convert 'device'.\n"); + msg_perr("%s: Could not convert 'device'.\n", __func__); free(device); return 1; } if (usedevice < 0 || usedevice > INT_MAX) { - msg_perr("Error: Value for 'device' is out of range.\n"); + msg_perr("%s: Value for 'device' is out of range.\n", + __func__); free(device); return 1; } if (strlen(dev_suffix) > 0) { - msg_perr("Error: Garbage following 'device' value.\n"); + msg_perr("%s: Garbage following 'device' value.\n", + __func__); free(device); return 1; } @@ -1147,17 +1153,20 @@ errno = 0; target = strtol(target_str, &target_suffix, 10); if (errno != 0 || target_str == target_suffix) { - msg_perr("Error: Could not convert 'target'.\n"); + msg_perr("%s: Could not convert 'target'.\n", + __func__); free(target_str); return 1; } if (target < 1 || target > 2) { - msg_perr("Error: Value for 'target' is out of range.\n"); + msg_perr("%s: Value for 'target' is out of range.\n", + __func__); free(target_str); return 1; } if (strlen(target_suffix) > 0) { - msg_perr("Error: Garbage following 'target' value.\n"); + msg_perr("%s: Garbage following 'target' value.\n", + __func__); free(target_str); return 1; } diff --git a/digilent_spi.c b/digilent_spi.c index 13a876e..8bae9f7 100644 --- a/digilent_spi.c +++ b/digilent_spi.c @@ -414,7 +414,7 @@ } } if (!spispeeds[i].name) { - msg_perr("Error: Invalid spispeed value: '%s'.\n", p); + msg_perr("%s: Invalid spispeed value: '%s'.\n", __func__, p); free(p); goto close_handle; } diff --git a/dummyflasher.c b/dummyflasher.c index b9f6126..49f0356 100644 --- a/dummyflasher.c +++ b/dummyflasher.c @@ -364,8 +364,9 @@ emu_status = strtoul(status, &endptr, 0); free(status); if (errno != 0 || status == endptr) { - msg_perr("Error: initial status register specified, " - "but the value could not be converted.\n"); + msg_perr("%s: initial status register specified, " + "but the value could not be converted.\n", + __func__); return 1; } msg_pdbg("Initial status register is set to 0x%02x.\n", diff --git a/flashrom.c b/flashrom.c index 4224637..b2d553b 100644 --- a/flashrom.c +++ b/flashrom.c @@ -852,7 +852,7 @@ int ret = 0; if (start + len > flash->chip->total_size * 1024) { - msg_gerr("Error: %s called with start 0x%x + len 0x%x >" + msg_gerr("%s: called with start 0x%x + len 0x%x >" " total_size 0x%x\n", __func__, start, len, flash->chip->total_size * 1024); ret = -1; @@ -1309,34 +1309,36 @@ const char *filename) { #ifdef __LIBPAYLOAD__ - msg_gerr("Error: No file I/O support in libpayload\n"); + msg_gerr("%s: No file I/O support in libpayload\n", __func__); return 1; #else int ret = 0; FILE *image; if ((image = fopen(filename, "rb")) == NULL) { - msg_gerr("Error: opening file \"%s\" failed: %s\n", filename, strerror(errno)); + msg_gerr("%s: opening file \"%s\" failed: %s\n", + __func__, filename, strerror(errno)); return 1; } struct stat image_stat; if (fstat(fileno(image), &image_stat) != 0) { - msg_gerr("Error: getting metadata of file \"%s\" failed: %s\n", filename, strerror(errno)); + msg_gerr("%s: getting metadata of file \"%s\" failed: %s\n", + __func__, filename, strerror(errno)); ret = 1; goto out; } if (image_stat.st_size != (intmax_t)size) { - msg_gerr("Error: Image size (%jd B) doesn't match the flash chip's size (%lu B)!\n", - (intmax_t)image_stat.st_size, size); + msg_gerr("%s: Image size (%jd B) doesn't match the flash chip's size (%lu B)!\n", + __func__, (intmax_t)image_stat.st_size, size); ret = 1; goto out; } unsigned long numbytes = fread(buf, 1, size, image); if (numbytes != size) { - msg_gerr("Error: Failed to read complete file. Got %ld bytes, " - "wanted %ld!\n", numbytes, size); + msg_gerr("%s: Failed to read complete file. Got %ld bytes, " + "wanted %ld!\n", __func__, numbytes, size); ret = 1; } out: @@ -1348,7 +1350,7 @@ int write_buf_to_file(const unsigned char *buf, unsigned long size, const char *filename) { #ifdef __LIBPAYLOAD__ - msg_gerr("Error: No file I/O support in libpayload\n"); + msg_gerr("%s: No file I/O support in libpayload\n", __func__); return 1; #else FILE *image; @@ -1359,38 +1361,44 @@ return 1; } if ((image = fopen(filename, "wb")) == NULL) { - msg_gerr("Error: opening file \"%s\" failed: %s\n", filename, strerror(errno)); + msg_gerr("%s: opening file \"%s\" failed: %s\n", + __func__, filename, strerror(errno)); return 1; } unsigned long numbytes = fwrite(buf, 1, size, image); if (numbytes != size) { - msg_gerr("Error: file %s could not be written completely.\n", filename); + msg_gerr("%s: file %s could not be written completely.\n", + __func__, filename); ret = 1; goto out; } if (fflush(image)) { - msg_gerr("Error: flushing file \"%s\" failed: %s\n", filename, strerror(errno)); + msg_gerr("%s: flushing file \"%s\" failed: %s\n", + __func__, filename, strerror(errno)); ret = 1; } // Try to fsync() only regular files and if that function is available at all (e.g. not on MinGW). #if defined(_POSIX_FSYNC) && (_POSIX_FSYNC != -1) struct stat image_stat; if (fstat(fileno(image), &image_stat) != 0) { - msg_gerr("Error: getting metadata of file \"%s\" failed: %s\n", filename, strerror(errno)); + msg_gerr("%s: getting metadata of file \"%s\" failed: %s\n", + __func__, filename, strerror(errno)); ret = 1; goto out; } if (S_ISREG(image_stat.st_mode)) { if (fsync(fileno(image))) { - msg_gerr("Error: fsyncing file \"%s\" failed: %s\n", filename, strerror(errno)); + msg_gerr("%s: fsyncing file \"%s\" failed: %s\n", + __func__, filename, strerror(errno)); ret = 1; } } #endif out: if (fclose(image)) { - msg_gerr("Error: closing file \"%s\" failed: %s\n", filename, strerror(errno)); + msg_gerr("%s: closing file \"%s\" failed: %s\n", + __func__, filename, strerror(errno)); ret = 1; } return ret; diff --git a/ft2232_spi.c b/ft2232_spi.c index 9f4c7f0..6f07c05 100644 --- a/ft2232_spi.c +++ b/ft2232_spi.c @@ -283,7 +283,7 @@ * and 0x40 to be driven low to enable output buffers */ pindir = 0xcb; } else { - msg_perr("Error: Invalid device type specified.\n"); + msg_perr("%s: Invalid device type specified.\n", __func__); free(arg); return -1; } @@ -316,7 +316,8 @@ break; } if (channel_count < 0 || strlen(arg) != 1) { - msg_perr("Error: Invalid channel/port/interface specified: \"%s\".\n", arg); + msg_perr("%s: Invalid channel/port/interface specified: \"%s\".\n", + __func__, arg); free(arg); return -2; } @@ -329,8 +330,9 @@ char *endptr; temp = strtoul(arg, &endptr, 10); if (*endptr || temp < 2 || temp > 131072 || temp & 0x1) { - msg_perr("Error: Invalid SPI frequency divisor specified: \"%s\".\n" - "Valid are even values between 2 and 131072.\n", arg); + msg_perr("%s: Invalid SPI frequency divisor specified: \"%s\".\n" + "Valid are even values between 2 and 131072.\n", + __func__, arg); free(arg); return -2; } @@ -345,9 +347,10 @@ for (unsigned int i = 0; i <= ngpios; i++) { int temp = arg[i] - '0'; if (ngpios == 0 || (ngpios != i && (temp < 0 || temp > 3))) { - msg_perr("Error: Invalid GPIOLs specified: \"%s\".\n" + msg_perr("%s: Invalid GPIOLs specified: \"%s\".\n" "Valid values are numbers between 0 and 3. " - "Multiple GPIOLs can be specified.\n", arg); + "Multiple GPIOLs can be specified.\n", + __func__, arg); free(arg); return -2; } else { diff --git a/ichspi.c b/ichspi.c index 12ee126..c993129 100644 --- a/ichspi.c +++ b/ichspi.c @@ -852,7 +852,7 @@ programmer_delay(10); } if (!timeout) { - msg_perr("Error: SCIP never cleared!\n"); + msg_perr("%s: SCIP never cleared!\n", __func__); return 1; } @@ -969,7 +969,7 @@ programmer_delay(10); } if (!timeout) { - msg_perr("Error: SCIP never cleared!\n"); + msg_perr("%s: SCIP never cleared!\n", __func__); return 1; } diff --git a/it87spi.c b/it87spi.c index f5955fe..98389bc 100644 --- a/it87spi.c +++ b/it87spi.c @@ -203,9 +203,10 @@ * should only be done if no port between 0x100 and * 0xff8 works due to routing issues. */ - msg_perr("Error: it87spiport specified, but no valid " + msg_perr("%s: it87spiport specified, but no valid " "port specified.\nPort must be a multiple of " - "0x8 and lie between 0x100 and 0xff8.\n"); + "0x8 and lie between 0x100 and 0xff8.\n", + __func__); exit_conf_mode_ite(port); free(param); return 1; diff --git a/layout.c b/layout.c index d80b01f..b39c76f 100644 --- a/layout.c +++ b/layout.c @@ -76,7 +76,8 @@ tstr1 = strtok(tempstr, ":"); tstr2 = strtok(NULL, ":"); if (!tstr1 || !tstr2) { - msg_gerr("Error parsing layout file. Offending string: \"%s\"\n", tempstr); + msg_gerr("%s: error parsing layout file. Offending string: \"%s\"\n", + __func__, tempstr); goto _close_ret; } layout->entries[layout->num_entries].start = strtol(tstr1, (char **)NULL, 16); @@ -84,7 +85,8 @@ layout->entries[layout->num_entries].included = 0; layout->entries[layout->num_entries].name = strdup(tempname); if (!layout->entries[layout->num_entries].name) { - msg_gerr("Error adding layout entry: %s\n", strerror(errno)); + msg_gerr("%s: error adding layout entry: %s\n", + __func__, strerror(errno)); goto _close_ret; } layout->num_entries++; @@ -226,8 +228,8 @@ ret = 1; } if (layout->entries[i].start > layout->entries[i].end) { - msg_gerr("Error: Size of the address range of region \"%s\" is not positive.\n", - layout->entries[i].name); + msg_gerr("%s: Size of the address range of region \"%s\" is not positive.\n", + __func__, layout->entries[i].name); ret = 1; } } diff --git a/libflashrom.c b/libflashrom.c index 0dec22e..cde2629 100644 --- a/libflashrom.c +++ b/libflashrom.c @@ -281,7 +281,7 @@ break; } if (prog >= PROGRAMMER_INVALID) { - msg_ginfo("Error: Unknown programmer \"%s\". Valid choices are:\n", prog_name); + msg_ginfo("%s: Unknown programmer \"%s\". Valid choices are:\n", __func__, prog_name); list_programmers_linebreak(0, 80, 0); return 1; } @@ -531,7 +531,7 @@ l->entries[l->num_entries].name = strndup((const char *)fmap->areas[i].name, FMAP_STRLEN); if (!l->entries[l->num_entries].name) { - msg_gerr("Error adding layout entry: %s\n", strerror(errno)); + msg_gerr("%s: error adding layout entry: %s\n", __func__, strerror(errno)); return 1; } msg_gdbg("fmap %08x - %08x named %s\n", diff --git a/lspcon_i2c_spi.c b/lspcon_i2c_spi.c index 8de2c14..0e01607 100644 --- a/lspcon_i2c_spi.c +++ b/lspcon_i2c_spi.c @@ -154,7 +154,7 @@ } while (!ret && (val & mask) && ++tried < MAX_SPI_WAIT_RETRIES); if (tried == MAX_SPI_WAIT_RETRIES) { - msg_perr("Error: Time out on sending command.\n"); + msg_perr("%s: Time out on sending command.\n", __func__); return -MAX_SPI_WAIT_RETRIES; } @@ -179,7 +179,7 @@ } while (!ret && (val & SWSPICTL_ACCESS_TRIGGER) && ++tried < MAX_SPI_WAIT_RETRIES); if (tried == MAX_SPI_WAIT_RETRIES) { - msg_perr("Error: Time out on waiting ROM free.\n"); + msg_perr("%s: Time out on waiting ROM free.\n", __func__); return -MAX_SPI_WAIT_RETRIES; } @@ -258,7 +258,8 @@ { unsigned int i; if (writecnt > 16 || readcnt > 16 || writecnt == 0) { - msg_perr("Error: Invalid read/write count for send command.\n"); + msg_perr("%s: Invalid read/write count for send command.\n", + __func__); return SPI_GENERIC_ERROR; } @@ -402,7 +403,8 @@ static int lspcon_i2c_spi_write_aai(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len) { - msg_perr("Error: AAI write function is not supported.\n"); + msg_perr("%s: AAI write function is not supported.\n", + __func__); return SPI_GENERIC_ERROR; } @@ -441,17 +443,19 @@ errno = 0; int bus = (int)strtol(bus_str, &bus_suffix, 10); if (errno != 0 || bus_str == bus_suffix) { - msg_perr("Error: Could not convert 'bus'.\n"); + msg_perr("%s: Could not convert 'bus'.\n", __func__); goto get_bus_done; } if (bus < 0 || bus > 255) { - msg_perr("Error: Value for 'bus' is out of range(0-255).\n"); + msg_perr("%s: Value for 'bus' is out of range(0-255).\n", + __func__); goto get_bus_done; } if (strlen(bus_suffix) > 0) { - msg_perr("Error: Garbage following 'bus' value.\n"); + msg_perr("%s: Garbage following 'bus' value.\n", + __func__); goto get_bus_done; } @@ -459,7 +463,7 @@ ret = bus; goto get_bus_done; } else { - msg_perr("Error: Bus number not specified.\n"); + msg_perr("%s: Bus number not specified.\n", __func__); } get_bus_done: if (bus_str) diff --git a/mcp6x_spi.c b/mcp6x_spi.c index b53d07b..c9ac1b5 100644 --- a/mcp6x_spi.c +++ b/mcp6x_spi.c @@ -130,7 +130,8 @@ /* Accessing a NULL pointer BAR is evil. Don't do it. */ if (!mcp6x_spibaraddr && want_spi) { - msg_perr("Error: Chipset is strapped for SPI, but MCP SPI BAR is invalid.\n"); + msg_perr("%s: Chipset is strapped for SPI, but MCP SPI BAR is invalid.\n", + __func__); return 1; } else if (!mcp6x_spibaraddr && !want_spi) { msg_pdbg("MCP SPI is not used.\n"); diff --git a/mstarddc_spi.c b/mstarddc_spi.c index db11157..49fdd95 100644 --- a/mstarddc_spi.c +++ b/mstarddc_spi.c @@ -81,15 +81,17 @@ i2c_address++; } if (i2c_address == NULL || strlen(i2c_address) == 0) { - msg_perr("Error: no address specified.\n" - "Use flashrom -p mstarddc_spi:dev=/dev/device:address.\n"); + msg_perr("%s: no address specified.\n" + "Use flashrom -p mstarddc_spi:dev=/dev/device:address.\n", + __func__); ret = -1; goto out; } mstarddc_addr = strtol(i2c_address, NULL, 16); // FIXME: error handling } else { - msg_perr("Error: no device specified.\n" - "Use flashrom -p mstarddc_spi:dev=/dev/device:address.\n"); + msg_perr("%s: no device specified.\n" + "Use flashrom -p mstarddc_spi:dev=/dev/device:address.\n", + __func__); ret = -1; goto out; } diff --git a/pcidev.c b/pcidev.c index e13b78c..2c3cdfa 100644 --- a/pcidev.c +++ b/pcidev.c @@ -198,7 +198,7 @@ pcidev_bdf = extract_programmer_param("pci"); if (pcidev_bdf != NULL) { if ((msg = pci_filter_parse_slot(&filter, pcidev_bdf))) { - msg_perr("Error: %s\n", msg); + msg_perr("%s: %s\n", __func__, msg); return NULL; } } @@ -237,11 +237,12 @@ /* Only continue if exactly one supported PCI dev has been found. */ if (found == 0) { - msg_perr("Error: No supported PCI device found.\n"); + msg_perr("%s: No supported PCI device found.\n", __func__); return NULL; } else if (found > 1) { - msg_perr("Error: Multiple supported PCI devices found. Use 'flashrom -p xxxx:pci=bb:dd.f'\n" - "to explicitly select the card with the given BDF (PCI bus, device, function).\n"); + msg_perr("%s: Multiple supported PCI devices found. Use 'flashrom -p xxxx:pci=bb:dd.f'\n" + "to explicitly select the card with the given BDF (PCI bus, device, function).\n", + __func__); return NULL; } diff --git a/pickit2_spi.c b/pickit2_spi.c index 2936ee8..1b5d869 100644 --- a/pickit2_spi.c +++ b/pickit2_spi.c @@ -409,7 +409,7 @@ } } if (spispeeds[i].name == NULL) { - msg_perr("Error: Invalid 'spispeed' value.\n"); + msg_perr("%s: Invalid 'spispeed' value.\n", __func__); free(spispeed); return 1; } diff --git a/pony_spi.c b/pony_spi.c index ed9d326..d113a63 100644 --- a/pony_spi.c +++ b/pony_spi.c @@ -137,8 +137,9 @@ free(arg); if (!have_device) { - msg_perr("Error: No valid device specified.\n" - "Use flashrom -p pony_spi:dev=/dev/device[,type=name]\n"); + msg_perr("%s: No valid device specified.\n" + "Use flashrom -p pony_spi:dev=/dev/device[,type=name]\n", + __func__); return 1; } @@ -150,11 +151,11 @@ } else if (arg && !strcasecmp( arg, "ajawe")) { type = TYPE_AJAWE; } else if (arg && !strlen(arg)) { - msg_perr("Error: Missing argument for programmer type.\n"); + msg_perr("%s: Missing argument for programmer type.\n", __func__); free(arg); return 1; } else if (arg){ - msg_perr("Error: Invalid programmer type specified.\n"); + msg_perr("%s: Invalid programmer type specified.\n", __func__); free(arg); return 1; } diff --git a/rayer_spi.c b/rayer_spi.c index 8e869e6..801ac9b 100644 --- a/rayer_spi.c +++ b/rayer_spi.c @@ -184,9 +184,10 @@ * should only be done if no port between 0x100 and * 0xfffc works due to routing issues. */ - msg_perr("Error: iobase= specified, but the I/O base " + msg_perr("%s: iobase= specified, but the I/O base " "given was invalid.\nIt must be a multiple of " - "0x4 and lie between 0x100 and 0xfffc.\n"); + "0x4 and lie between 0x100 and 0xfffc.\n", + __func__); free(arg); return 1; } else { @@ -211,7 +212,8 @@ } } if (prog->type == NULL) { - msg_perr("Error: Invalid device type specified.\n"); + msg_perr("%s: Invalid device type specified.\n" + , __func__); free(arg); return 1; } diff --git a/sb600spi.c b/sb600spi.c index a649253..41c808a 100644 --- a/sb600spi.c +++ b/sb600spi.c @@ -432,7 +432,8 @@ (i == ARRAY_SIZE(spispeeds)) || (amd_gen < CHIPSET_YANGTZE && spispeed_idx > 3) || (amd_gen < CHIPSET_SB89XX && spispeed_idx == 0)) { - msg_perr("Error: Invalid spispeed value: '%s'.\n", spispeed); + msg_perr("%s: Invalid spispeed value: '%s'.\n", + __func__, spispeed); free(spispeed); return 1; } @@ -450,7 +451,8 @@ } if ((strcasecmp(spireadmode, "reserved") == 0) || (i == ARRAY_SIZE(spireadmodes))) { - msg_perr("Error: Invalid spireadmode value: '%s'.\n", spireadmode); + msg_perr("%s: Invalid spireadmode value: '%s'.\n", + __func__, spireadmode); free(spireadmode); return 1; } diff --git a/serprog.c b/serprog.c index 37a9db4..1c269a3 100644 --- a/serprog.c +++ b/serprog.c @@ -91,7 +91,8 @@ msg_pdbg(MSGHEADER "IP %s port %d\n", ip, port); sock = socket(PF_INET, SOCK_STREAM, IPPROTO_TCP); if (sock < 0) { - msg_perr("Error: serprog cannot open socket: %s\n", strerror(errno)); + msg_perr("%s: serprog cannot open socket: %s\n", + __func__, strerror(errno)); return -1; } hostPtr = gethostbyname(ip); @@ -99,7 +100,7 @@ hostPtr = gethostbyaddr(ip, strlen(ip), AF_INET); if (NULL == hostPtr) { close(sock); - msg_perr("Error: cannot resolve %s\n", ip); + msg_perr("%s: cannot resolve %s\n", __func__, ip); return -1; } } @@ -108,14 +109,16 @@ (void)memcpy(&sp.si.sin_addr, hostPtr->h_addr_list[0], hostPtr->h_length); if (connect(sock, &sp.s, sizeof(sp.si)) < 0) { close(sock); - msg_perr("Error: serprog cannot connect: %s\n", strerror(errno)); + msg_perr("%s: serprog cannot connect: %s\n", + __func__,strerror(errno)); return -1; } /* We are latency limited, and sometimes do write-write-read * * (write-n) - so enable TCP_NODELAY. */ if (setsockopt(sock, IPPROTO_TCP, TCP_NODELAY, &flag, sizeof(int))) { close(sock); - msg_perr("Error: serprog cannot set socket options: %s\n", strerror(errno)); + msg_perr("%s: serprog cannot set socket options: %s\n", + __func__, strerror(errno)); return -1; } return sock; @@ -185,7 +188,8 @@ } } err_out: - msg_perr("Error: cannot synchronize protocol - check communications and reset device?\n"); + msg_perr("%s: cannot synchronize protocol - check communications and reset device?\n", + __func__); return 1; } @@ -214,26 +218,31 @@ if (sp_automatic_cmdcheck(command)) return 1; if (serialport_write(&command, 1) != 0) { - msg_perr("Error: cannot write op code: %s\n", strerror(errno)); + msg_perr("%s: cannot write op code: %s\n", + __func__, strerror(errno)); return 1; } if (serialport_write(params, parmlen) != 0) { - msg_perr("Error: cannot write parameters: %s\n", strerror(errno)); + msg_perr("%s: cannot write parameters: %s\n", + __func__, strerror(errno)); return 1; } if (serialport_read(&c, 1) != 0) { - msg_perr("Error: cannot read from device: %s\n", strerror(errno)); + msg_perr("%s: cannot read from device: %s\n", + __func__, strerror(errno)); return 1; } if (c == S_NAK) return 1; if (c != S_ACK) { - msg_perr("Error: invalid response 0x%02X from device (to command 0x%02X)\n", c, command); + msg_perr("%s: invalid response 0x%02X from device (to command 0x%02X)\n", + __func__, c, command); return 1; } if (retlen) { if (serialport_read(retparms, retlen) != 0) { - msg_perr("Error: cannot read return parameters: %s\n", strerror(errno)); + msg_perr("%s: cannot read return parameters: %s\n", + __func__, strerror(errno)); return 1; } } @@ -246,15 +255,18 @@ do { unsigned char c; if (serialport_read(&c, 1) != 0) { - msg_perr("Error: cannot read from device (flushing stream)"); + msg_perr("%s: cannot read from device (flushing stream)\n", + __func__); return 1; } if (c == S_NAK) { - msg_perr("Error: NAK to a stream buffer operation\n"); + msg_perr("%s: NAK to a stream buffer operation\n", + __func__); return 1; } if (c != S_ACK) { - msg_perr("Error: Invalid reply 0x%02X from device\n", c); + msg_perr("%s: Invalid reply 0x%02X from device\n", + __func__, c); return 1; } } while (--sp_streamed_transmit_ops); @@ -271,7 +283,7 @@ sp = malloc(1 + parmlen); if (!sp) { - msg_perr("Error: cannot malloc command buffer\n"); + msg_perr("%s: cannot malloc command buffer\n", __func__); return 1; } sp[0] = cmd; @@ -284,7 +296,7 @@ } } if (serialport_write(sp, 1 + parmlen) != 0) { - msg_perr("Error: cannot write command\n"); + msg_perr("%s: cannot write command\n", __func__); free(sp); return 1; } @@ -368,8 +380,9 @@ #if !IS_WINDOWS if (device && !strlen(device)) { - msg_perr("Error: No device specified.\n" - "Use flashrom -p serprog:dev=/dev/device[:baud]\n"); + msg_perr("%s: No device specified.\n" + "Use flashrom -p serprog:dev=/dev/device[:baud]\n", + __func__); free(device); return 1; } @@ -377,8 +390,9 @@ device = extract_programmer_param("ip"); if (have_device && device) { - msg_perr("Error: Both host and device specified.\n" - "Please use either dev= or ip= but not both.\n"); + msg_perr("%s: Both host and device specified.\n" + "Please use either dev= or ip= but not both.\n", + __func__); free(device); return 1; } @@ -390,8 +404,9 @@ port++; } if (!port || !strlen(port)) { - msg_perr("Error: No port specified.\n" - "Use flashrom -p serprog:ip=ipaddr:port\n"); + msg_perr("%s: No port specified.\n" + "Use flashrom -p serprog:ip=ipaddr:port\n", + __func__); free(device); return 1; } @@ -405,8 +420,9 @@ } } if (device && !strlen(device)) { - msg_perr("Error: No host specified.\n" - "Use flashrom -p serprog:ip=ipaddr:port\n"); + msg_perr("%s: No host specified.\n" + "Use flashrom -p serprog:ip=ipaddr:port\n", + __func__); free(device); return 1; } @@ -415,12 +431,14 @@ if (!have_device) { #if IS_WINDOWS - msg_perr("Error: No device specified.\n" - "Use flashrom -p serprog:dev=comN[:baud]\n"); + msg_perr("%s: No device specified.\n" + "Use flashrom -p serprog:dev=comN[:baud]\n", + __func__); #else - msg_perr("Error: Neither host nor device specified.\n" + msg_perr("%s: Neither host nor device specified.\n" "Use flashrom -p serprog:dev=/dev/device:baud or " - "flashrom -p serprog:ip=ipaddr:port\n"); + "flashrom -p serprog:ip=ipaddr:port\n", + __func__); #endif return 1; } @@ -438,19 +456,21 @@ msg_pdbg(MSGHEADER "Synchronized\n"); if (sp_docommand(S_CMD_Q_IFACE, 0, NULL, 2, &iface)) { - msg_perr("Error: NAK to query interface version\n"); + msg_perr("%s: NAK to query interface version\n", __func__); return 1; } if (iface != 1) { - msg_perr("Error: Unknown interface version: %d\n", iface); + msg_perr("%s: Unknown interface version: %d\n", + __func__, iface); return 1; } msg_pdbg(MSGHEADER "Interface version ok.\n"); if (sp_docommand(S_CMD_Q_CMDMAP, 0, NULL, 32, sp_cmdmap)) { - msg_perr("Error: query command map not supported\n"); + msg_perr("%s: query command map not supported\n", + __func__); return 1; } @@ -476,8 +496,9 @@ uint8_t bt = BUS_SPI; char *spispeed; if (sp_check_commandavail(S_CMD_O_SPIOP) == 0) { - msg_perr("Error: SPI operation not supported while the " - "bustype is SPI\n"); + msg_perr("%s: SPI operation not supported while the " + "bustype is SPI\n", + __func__); return 1; } if (sp_docommand(S_CMD_S_BUSTYPE, 1, &bt, 0, NULL)) @@ -515,7 +536,8 @@ errno = 0; f_spi_req = strtol(spispeed, &f_spi_suffix, 0); if (errno != 0 || spispeed == f_spi_suffix) { - msg_perr("Error: Could not convert 'spispeed'.\n"); + msg_perr("%s: Could not convert 'spispeed'.\n", + __func__); free(spispeed); return 1; } @@ -525,12 +547,14 @@ else if (!strcasecmp(f_spi_suffix, "k")) f_spi_req *= 1000; else { - msg_perr("Error: Garbage following 'spispeed' value.\n"); + msg_perr("%s: Garbage following 'spispeed' value.\n", + __func__); free(spispeed); return 1; } } else if (strlen(f_spi_suffix) > 1) { - msg_perr("Error: Garbage following 'spispeed' value.\n"); + msg_perr("%s: Garbage following 'spispeed' value.\n", + __func__); free(spispeed); return 1; } @@ -560,32 +584,37 @@ if (serprog_buses_supported & BUS_NONSPI) { if (sp_check_commandavail(S_CMD_O_INIT) == 0) { - msg_perr("Error: Initialize operation buffer " - "not supported\n"); + msg_perr("%s: Initialize operation buffer " + "not supported\n", + __func__); return 1; } if (sp_check_commandavail(S_CMD_O_DELAY) == 0) { - msg_perr("Error: Write to opbuf: " - "delay not supported\n"); + msg_perr("%s: Write to opbuf: " + "delay not supported\n", + __func__); return 1; } /* S_CMD_O_EXEC availability checked later. */ if (sp_check_commandavail(S_CMD_R_BYTE) == 0) { - msg_perr("Error: Single byte read not supported\n"); + msg_perr("%s: Single byte read not supported\n", + __func__); return 1; } /* This could be translated to single byte reads (if missing), * but now we don't support that. */ if (sp_check_commandavail(S_CMD_R_NBYTES) == 0) { - msg_perr("Error: Read n bytes not supported\n"); + msg_perr("%s: Read n bytes not supported\n", + __func__); return 1; } if (sp_check_commandavail(S_CMD_O_WRITEB) == 0) { - msg_perr("Error: Write to opbuf: " - "write byte not supported\n"); + msg_perr("%s: Write to opbuf: " + "write byte not supported\n", + __func__); return 1; } @@ -603,8 +632,9 @@ sp_max_write_n); sp_write_n_buf = malloc(sp_max_write_n); if (!sp_write_n_buf) { - msg_perr("Error: cannot allocate memory for " - "Write-n buffer\n"); + msg_perr("%s: cannot allocate memory for " + "Write-n buffer\n", + __func__); return 1; } sp_write_n_bytes = 0; @@ -641,13 +671,15 @@ if (sp_check_commandavail(S_CMD_O_INIT)) { /* This would be inconsistent. */ if (sp_check_commandavail(S_CMD_O_EXEC) == 0) { - msg_perr("Error: Execute operation buffer not " - "supported\n"); + msg_perr("%s: Execute operation buffer not " + "supported\n", + __func__); return 1; } if (sp_docommand(S_CMD_O_INIT, 0, NULL, 0, NULL)) { - msg_perr("Error: NAK to initialize operation buffer\n"); + msg_perr("%s: NAK to initialize operation buffer\n", + __func__); return 1; } @@ -662,7 +694,8 @@ if (sp_check_commandavail(S_CMD_S_PIN_STATE)) { uint8_t en = 1; if (sp_docommand(S_CMD_S_PIN_STATE, 1, &en, 0, NULL) != 0) { - msg_perr("Error: could not enable output buffers\n"); + msg_perr("%s: could not enable output buffers\n", + __func__); return 1; } else msg_pdbg(MSGHEADER "Output drivers enabled\n"); @@ -709,11 +742,12 @@ header[5] = (sp_write_n_addr >> 8) & 0xFF; header[6] = (sp_write_n_addr >> 16) & 0xFF; if (serialport_write(header, 7) != 0) { - msg_perr(MSGHEADER "Error: cannot write write-n command\n"); + msg_perr(MSGHEADER "%s: cannot write write-n command\n", + __func__); return 1; } if (serialport_write(sp_write_n_buf, sp_write_n_bytes) != 0) { - msg_perr(MSGHEADER "Error: cannot write write-n data"); + msg_perr(MSGHEADER "%s: cannot write write-n data", __func__); return 1; } sp_streamed_transmit_bytes += 7 + sp_write_n_bytes; @@ -728,12 +762,13 @@ { if ((sp_max_write_n) && (sp_write_n_bytes)) { if (sp_pass_writen() != 0) { - msg_perr("Error: could not transfer write buffer\n"); + msg_perr("%s: could not transfer write buffer\n", + __func__); return 1; } } if (sp_stream_buffer_op(S_CMD_O_EXEC, 0, NULL) != 0) { - msg_perr("Error: could not execute command buffer\n"); + msg_perr("%s: could not execute command buffer\n", __func__); return 1; } msg_pspew(MSGHEADER "Executed operation buffer of %d bytes\n", sp_opbuf_usage); @@ -852,7 +887,7 @@ if (sp_flush_stream() != 0) return 1; if (serialport_read(buf, len) != 0) { - msg_perr(MSGHEADER "Error: cannot read read-n data"); + msg_perr(MSGHEADER "%s: cannot read read-n data", __func__); return 1; } return 0; @@ -904,14 +939,16 @@ msg_pspew("%s, writecnt=%i, readcnt=%i\n", __func__, writecnt, readcnt); if ((sp_opbuf_usage) || (sp_max_write_n && sp_write_n_bytes)) { if (sp_execute_opbuf() != 0) { - msg_perr("Error: could not execute command buffer before sending SPI commands.\n"); + msg_perr("%s: could not execute command buffer before sending SPI commands.\n", + __func__); return 1; } } parmbuf = malloc(writecnt + 6); if (!parmbuf) { - msg_perr("Error: could not allocate SPI send param buffer.\n"); + msg_perr("%s: could not allocate SPI send param buffer.\n", + __func__); return 1; } parmbuf[0] = (writecnt >> 0) & 0xFF; diff --git a/spi25_statusreg.c b/spi25_statusreg.c index aa574d5..91df8b2 100644 --- a/spi25_statusreg.c +++ b/spi25_statusreg.c @@ -65,7 +65,7 @@ programmer_delay(100 * 1000); while (spi_read_status_register(flash) & SPI_SR_WIP) { if (++i > 490) { - msg_cerr("Error: WIP bit after WRSR never cleared\n"); + msg_cerr("%s: WIP bit after WRSR never cleared\n", __func__); return TIMEOUT_ERROR; } programmer_delay(10 * 1000); -- To view, visit https://review.coreboot.org/c/flashrom/+/40901 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: If3205d8e453cfcd37f725b4fd135fe1221c913c0 Gerrit-Change-Number: 40901 Gerrit-PatchSet: 1 Gerrit-Owner: Shiyu Sun <sshiyu(a)google.com> Gerrit-MessageType: newchange

3 11

Change in flashrom[master]: const'ify flashctx to align signatures with cros flashrom
by Edward O'Callaghan (Code Review) 30 Apr '20

30 Apr '20

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/40324 ) Change subject: const'ify flashctx to align signatures with cros flashrom ...................................................................... const'ify flashctx to align signatures with cros flashrom The ChromiumOS flashrom fork has since const'ify flashctx in a few places. This aligns the function signatures to match with downstream to ease forward porting patches out of downstream back into mainline flashrom. This patch is minimum viable alignment and so feedback is welcome. Change-Id: Iff6dbda13cb0d941481c0d204b9c30895630fbd1 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M bitbang_spi.c M buspirate_spi.c M ch341a_spi.c M chipdrivers.h M dediprog.c M digilent_spi.c M dummyflasher.c M flash.h M ft2232_spi.c M ichspi.c M it85spi.c M it87spi.c M jlink_spi.c M linux_spi.c M lspcon_i2c_spi.c M mstarddc_spi.c M pickit2_spi.c M programmer.h M raiden_debug_spi.c M sb600spi.c M serprog.c M spi.c M spi25_statusreg.c M stlinkv3_spi.c M usbblaster_spi.c M wbsio_spi.c 26 files changed, 52 insertions(+), 52 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/24/40324/1 diff --git a/bitbang_spi.c b/bitbang_spi.c index 7c183c3..ac50e67 100644 --- a/bitbang_spi.c +++ b/bitbang_spi.c @@ -64,7 +64,7 @@ return master->get_miso(); } -static int bitbang_spi_send_command(struct flashctx *flash, +static int bitbang_spi_send_command(const struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); @@ -145,7 +145,7 @@ } } -static int bitbang_spi_send_command(struct flashctx *flash, +static int bitbang_spi_send_command(const struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) diff --git a/buspirate_spi.c b/buspirate_spi.c index 826bd84..fdfc0e4 100644 --- a/buspirate_spi.c +++ b/buspirate_spi.c @@ -128,9 +128,9 @@ return ret; } -static int buspirate_spi_send_command_v1(struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, +static int buspirate_spi_send_command_v1(const struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); -static int buspirate_spi_send_command_v2(struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, +static int buspirate_spi_send_command_v2(const struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); static struct spi_master spi_master_buspirate = { @@ -572,7 +572,7 @@ return 0; } -static int buspirate_spi_send_command_v1(struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, +static int buspirate_spi_send_command_v1(const struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { unsigned int i = 0; @@ -625,7 +625,7 @@ return ret; } -static int buspirate_spi_send_command_v2(struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, +static int buspirate_spi_send_command_v2(const struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { int i = 0, ret = 0; diff --git a/ch341a_spi.c b/ch341a_spi.c index d3af32f..17c37eb 100644 --- a/ch341a_spi.c +++ b/ch341a_spi.c @@ -335,7 +335,7 @@ stored_delay_us += usecs; } -static int ch341a_spi_spi_send_command(struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) +static int ch341a_spi_spi_send_command(const struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { if (handle == NULL) return -1; diff --git a/chipdrivers.h b/chipdrivers.h index cb1e877..3c7d146 100644 --- a/chipdrivers.h +++ b/chipdrivers.h @@ -62,8 +62,8 @@ /* spi25_statusreg.c */ -uint8_t spi_read_status_register(struct flashctx *flash); -int spi_write_status_register(struct flashctx *flash, int status); +uint8_t spi_read_status_register(const struct flashctx *flash); +int spi_write_status_register(const struct flashctx *flash, int status); void spi_prettyprint_status_register_bit(uint8_t status, int bit); int spi_prettyprint_status_register_plain(struct flashctx *flash); int spi_prettyprint_status_register_default_welwip(struct flashctx *flash); diff --git a/dediprog.c b/dediprog.c index 175e099..1f7c3d0 100644 --- a/dediprog.c +++ b/dediprog.c @@ -714,7 +714,7 @@ return dediprog_spi_write(flash, buf, start, len, WRITE_MODE_2B_AAI); } -static int dediprog_spi_send_command(struct flashctx *flash, +static int dediprog_spi_send_command(const struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, diff --git a/digilent_spi.c b/digilent_spi.c index 13a876e..0f7a9da 100644 --- a/digilent_spi.c +++ b/digilent_spi.c @@ -257,7 +257,7 @@ return 0; } -static int digilent_spi_send_command(struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, +static int digilent_spi_send_command(const struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { int ret; diff --git a/dummyflasher.c b/dummyflasher.c index b9f6126..e1a1d80 100644 --- a/dummyflasher.c +++ b/dummyflasher.c @@ -93,7 +93,7 @@ static unsigned int spi_write_256_chunksize = 256; -static int dummy_spi_send_command(struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, +static int dummy_spi_send_command(const struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); static int dummy_spi_write_256(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len); @@ -818,7 +818,7 @@ } #endif -static int dummy_spi_send_command(struct flashctx *flash, unsigned int writecnt, +static int dummy_spi_send_command(const struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) diff --git a/flash.h b/flash.h index 1a9bd9f..2f0143b 100644 --- a/flash.h +++ b/flash.h @@ -415,8 +415,8 @@ unsigned char *readarr; }; #define NULL_SPI_CMD { 0, 0, NULL, NULL, } -int spi_send_command(struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); -int spi_send_multicommand(struct flashctx *flash, struct spi_command *cmds); +int spi_send_command(const struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); +int spi_send_multicommand(const struct flashctx *flash, struct spi_command *cmds); enum chipbustype get_buses_supported(void); #endif /* !__FLASH_H__ */ diff --git a/ft2232_spi.c b/ft2232_spi.c index 520eb6e..c416d0f 100644 --- a/ft2232_spi.c +++ b/ft2232_spi.c @@ -155,7 +155,7 @@ return 0; } -static int ft2232_spi_send_command(struct flashctx *flash, +static int ft2232_spi_send_command(const struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); @@ -459,7 +459,7 @@ } /* Returns 0 upon success, a negative number upon errors. */ -static int ft2232_spi_send_command(struct flashctx *flash, +static int ft2232_spi_send_command(const struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) diff --git a/ichspi.c b/ichspi.c index 12ee126..c780d52 100644 --- a/ichspi.c +++ b/ichspi.c @@ -1103,7 +1103,7 @@ } } -static int ich_spi_send_command(struct flashctx *flash, unsigned int writecnt, +static int ich_spi_send_command(const struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) @@ -1506,7 +1506,7 @@ return 0; } -static int ich_spi_send_multicommand(struct flashctx *flash, +static int ich_spi_send_multicommand(const struct flashctx *flash, struct spi_command *cmds) { int ret = 0; diff --git a/it85spi.c b/it85spi.c index 5ce9193..b998790 100644 --- a/it85spi.c +++ b/it85spi.c @@ -270,7 +270,7 @@ return 0; } -static int it85xx_spi_send_command(struct flashctx *flash, +static int it85xx_spi_send_command(const struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); @@ -322,7 +322,7 @@ * 3. read date from LPC/FWH address 0xffff_fdxxh (drive CE# low and get * data from MISO) */ -static int it85xx_spi_send_command(struct flashctx *flash, +static int it85xx_spi_send_command(const struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) diff --git a/it87spi.c b/it87spi.c index f5955fe..8224db0 100644 --- a/it87spi.c +++ b/it87spi.c @@ -98,7 +98,7 @@ return; } -static int it8716f_spi_send_command(struct flashctx *flash, +static int it8716f_spi_send_command(const struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); @@ -275,7 +275,7 @@ * commands with the address in inverse wire order. That's why the register * ordering in case 4 and 5 may seem strange. */ -static int it8716f_spi_send_command(struct flashctx *flash, +static int it8716f_spi_send_command(const struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) diff --git a/jlink_spi.c b/jlink_spi.c index 8a69b41..36611bf 100644 --- a/jlink_spi.c +++ b/jlink_spi.c @@ -101,7 +101,7 @@ return true; } -static int jlink_spi_send_command(struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, +static int jlink_spi_send_command(const struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { uint32_t length; diff --git a/linux_spi.c b/linux_spi.c index aa73c18..1ef8f2b 100644 --- a/linux_spi.c +++ b/linux_spi.c @@ -49,7 +49,7 @@ static size_t max_kernel_buf_size; static int linux_spi_shutdown(void *data); -static int linux_spi_send_command(struct flashctx *flash, unsigned int writecnt, +static int linux_spi_send_command(const struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *txbuf, unsigned char *rxbuf); @@ -183,7 +183,7 @@ return 0; } -static int linux_spi_send_command(struct flashctx *flash, unsigned int writecnt, +static int linux_spi_send_command(const struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *txbuf, unsigned char *rxbuf) diff --git a/lspcon_i2c_spi.c b/lspcon_i2c_spi.c index 4c85426..3402111 100644 --- a/lspcon_i2c_spi.c +++ b/lspcon_i2c_spi.c @@ -251,7 +251,7 @@ return ret; } -static int lspcon_i2c_spi_send_command(struct flashctx *flash, +static int lspcon_i2c_spi_send_command(const struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) diff --git a/mstarddc_spi.c b/mstarddc_spi.c index db11157..48d6204 100644 --- a/mstarddc_spi.c +++ b/mstarddc_spi.c @@ -153,7 +153,7 @@ } /* Returns 0 upon success, a negative number upon errors. */ -static int mstarddc_spi_send_command(struct flashctx *flash, +static int mstarddc_spi_send_command(const struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, diff --git a/pickit2_spi.c b/pickit2_spi.c index 2936ee8..0bc17af 100644 --- a/pickit2_spi.c +++ b/pickit2_spi.c @@ -195,7 +195,7 @@ return 0; } -static int pickit2_spi_send_command(struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, +static int pickit2_spi_send_command(const struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { diff --git a/programmer.h b/programmer.h index f6c5399..49a9d29 100644 --- a/programmer.h +++ b/programmer.h @@ -612,9 +612,9 @@ uint32_t features; unsigned int max_data_read; // (Ideally,) maximum data read size in one go (excluding opcode+address). unsigned int max_data_write; // (Ideally,) maximum data write size in one go (excluding opcode+address). - int (*command)(struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, + int (*command)(const struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); - int (*multicommand)(struct flashctx *flash, struct spi_command *cmds); + int (*multicommand)(const struct flashctx *flash, struct spi_command *cmds); /* Optimized functions for this master */ int (*read)(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len); @@ -623,9 +623,9 @@ const void *data; }; -int default_spi_send_command(struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, +int default_spi_send_command(const struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); -int default_spi_send_multicommand(struct flashctx *flash, struct spi_command *cmds); +int default_spi_send_multicommand(const struct flashctx *flash, struct spi_command *cmds); int default_spi_read(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len); int default_spi_write_256(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len); int default_spi_write_aai(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len); diff --git a/raiden_debug_spi.c b/raiden_debug_spi.c index 173e355..2bdb94b 100644 --- a/raiden_debug_spi.c +++ b/raiden_debug_spi.c @@ -284,7 +284,7 @@ return response_packet.status_code; } -static int send_command(struct flashctx *flash, +static int send_command(const struct flashctx *flash, unsigned int write_count, unsigned int read_count, const unsigned char *write_buffer, diff --git a/sb600spi.c b/sb600spi.c index a649253..5892d57 100644 --- a/sb600spi.c +++ b/sb600spi.c @@ -56,9 +56,9 @@ #define FIFO_SIZE_OLD 8 #define FIFO_SIZE_YANGTZE 71 -static int sb600_spi_send_command(struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, +static int sb600_spi_send_command(const struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); -static int spi100_spi_send_command(struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, +static int spi100_spi_send_command(const struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); static struct spi_master spi_master_sb600 = { @@ -190,7 +190,7 @@ } /* Check the number of bytes to be transmitted and extract opcode. */ -static int check_readwritecnt(struct flashctx *flash, unsigned int writecnt, unsigned int readcnt) +static int check_readwritecnt(const struct flashctx *flash, unsigned int writecnt, unsigned int readcnt) { unsigned int maxwritecnt = flash->mst->spi.max_data_write + 3; if (writecnt > maxwritecnt) { @@ -217,7 +217,7 @@ msg_pspew("done\n"); } -static int sb600_spi_send_command(struct flashctx *flash, unsigned int writecnt, +static int sb600_spi_send_command(const struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) @@ -303,7 +303,7 @@ return 0; } -static int spi100_spi_send_command(struct flashctx *flash, unsigned int writecnt, +static int spi100_spi_send_command(const struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) diff --git a/serprog.c b/serprog.c index 37a9db4..1befce1 100644 --- a/serprog.c +++ b/serprog.c @@ -295,7 +295,7 @@ return 0; } -static int serprog_spi_send_command(struct flashctx *flash, +static int serprog_spi_send_command(const struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); @@ -894,7 +894,7 @@ sp_prev_was_write = 0; } -static int serprog_spi_send_command(struct flashctx *flash, +static int serprog_spi_send_command(const struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) diff --git a/spi.c b/spi.c index 489baf3..aed2a92 100644 --- a/spi.c +++ b/spi.c @@ -26,7 +26,7 @@ #include "programmer.h" #include "spi.h" -int spi_send_command(struct flashctx *flash, unsigned int writecnt, +int spi_send_command(const struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { @@ -34,12 +34,12 @@ readarr); } -int spi_send_multicommand(struct flashctx *flash, struct spi_command *cmds) +int spi_send_multicommand(const struct flashctx *flash, struct spi_command *cmds) { return flash->mst->spi.multicommand(flash, cmds); } -int default_spi_send_command(struct flashctx *flash, unsigned int writecnt, +int default_spi_send_command(const struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) @@ -60,7 +60,7 @@ return spi_send_multicommand(flash, cmd); } -int default_spi_send_multicommand(struct flashctx *flash, +int default_spi_send_multicommand(const struct flashctx *flash, struct spi_command *cmds) { int result = 0; diff --git a/spi25_statusreg.c b/spi25_statusreg.c index 8cd5a28..4b9b2a9 100644 --- a/spi25_statusreg.c +++ b/spi25_statusreg.c @@ -22,7 +22,7 @@ #include "spi.h" /* === Generic functions === */ -static int spi_write_status_register_flag(struct flashctx *flash, int status, const unsigned char enable_opcode) +static int spi_write_status_register_flag(const struct flashctx *flash, int status, const unsigned char enable_opcode) { int result; int i = 0; @@ -73,7 +73,7 @@ return 0; } -int spi_write_status_register(struct flashctx *flash, int status) +int spi_write_status_register(const struct flashctx *flash, int status) { int feature_bits = flash->chip->feature_bits; int ret = 1; @@ -90,7 +90,7 @@ return ret; } -uint8_t spi_read_status_register(struct flashctx *flash) +uint8_t spi_read_status_register(const struct flashctx *flash) { static const unsigned char cmd[JEDEC_RDSR_OUTSIZE] = { JEDEC_RDSR }; /* FIXME: No workarounds for driver/hardware bugs in generic code. */ diff --git a/stlinkv3_spi.c b/stlinkv3_spi.c index 7338911..39a0c9b 100644 --- a/stlinkv3_spi.c +++ b/stlinkv3_spi.c @@ -323,7 +323,7 @@ return 0; } -static int stlinkv3_spi_transmit(struct flashctx *flash, +static int stlinkv3_spi_transmit(const struct flashctx *flash, unsigned int write_cnt, unsigned int read_cnt, const unsigned char *write_arr, diff --git a/usbblaster_spi.c b/usbblaster_spi.c index e2a0a4f..46de86c 100644 --- a/usbblaster_spi.c +++ b/usbblaster_spi.c @@ -179,7 +179,7 @@ } /* Returns 0 upon success, a negative number upon errors. */ -static int usbblaster_spi_send_command(struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, +static int usbblaster_spi_send_command(const struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { uint8_t cmd; diff --git a/wbsio_spi.c b/wbsio_spi.c index f4f6af9..1674825 100644 --- a/wbsio_spi.c +++ b/wbsio_spi.c @@ -57,7 +57,7 @@ return flashport; } -static int wbsio_spi_send_command(struct flashctx *flash, unsigned int writecnt, +static int wbsio_spi_send_command(const struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); @@ -110,7 +110,7 @@ * Would one more byte of RAM in the chip (to get all 24 bits) really make * such a big difference? */ -static int wbsio_spi_send_command(struct flashctx *flash, unsigned int writecnt, +static int wbsio_spi_send_command(const struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) -- To view, visit https://review.coreboot.org/c/flashrom/+/40324 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Iff6dbda13cb0d941481c0d204b9c30895630fbd1 Gerrit-Change-Number: 40324 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

2 5

Change in flashrom[master]: lspcon_i2c_spi.c: Switch logs with 'Error:' to '__func__:'
by Shiyu Sun (Code Review) 30 Apr '20

30 Apr '20

Shiyu Sun has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/40903 ) Change subject: lspcon_i2c_spi.c: Switch logs with 'Error:' to '__func__:' ...................................................................... lspcon_i2c_spi.c: Switch logs with 'Error:' to '__func__:' Showing Error is not very informative and switch to function name to make it easy for debug. BUG=b:154285774 BRANCH=none TEST=build success Change-Id: If3205d8e453cfcd37f725b4fd135fe1221c913c0 Signed-off-by: Shiyu Sun <sshiyu(a)chromium.org> Change-Id: I34d326a9b40a95334995db2c6de80cfb7d133b03 --- M lspcon_i2c_spi.c 1 file changed, 12 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/03/40903/1 diff --git a/lspcon_i2c_spi.c b/lspcon_i2c_spi.c index 8de2c14..0e01607 100644 --- a/lspcon_i2c_spi.c +++ b/lspcon_i2c_spi.c @@ -154,7 +154,7 @@ } while (!ret && (val & mask) && ++tried < MAX_SPI_WAIT_RETRIES); if (tried == MAX_SPI_WAIT_RETRIES) { - msg_perr("Error: Time out on sending command.\n"); + msg_perr("%s: Time out on sending command.\n", __func__); return -MAX_SPI_WAIT_RETRIES; } @@ -179,7 +179,7 @@ } while (!ret && (val & SWSPICTL_ACCESS_TRIGGER) && ++tried < MAX_SPI_WAIT_RETRIES); if (tried == MAX_SPI_WAIT_RETRIES) { - msg_perr("Error: Time out on waiting ROM free.\n"); + msg_perr("%s: Time out on waiting ROM free.\n", __func__); return -MAX_SPI_WAIT_RETRIES; } @@ -258,7 +258,8 @@ { unsigned int i; if (writecnt > 16 || readcnt > 16 || writecnt == 0) { - msg_perr("Error: Invalid read/write count for send command.\n"); + msg_perr("%s: Invalid read/write count for send command.\n", + __func__); return SPI_GENERIC_ERROR; } @@ -402,7 +403,8 @@ static int lspcon_i2c_spi_write_aai(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len) { - msg_perr("Error: AAI write function is not supported.\n"); + msg_perr("%s: AAI write function is not supported.\n", + __func__); return SPI_GENERIC_ERROR; } @@ -441,17 +443,19 @@ errno = 0; int bus = (int)strtol(bus_str, &bus_suffix, 10); if (errno != 0 || bus_str == bus_suffix) { - msg_perr("Error: Could not convert 'bus'.\n"); + msg_perr("%s: Could not convert 'bus'.\n", __func__); goto get_bus_done; } if (bus < 0 || bus > 255) { - msg_perr("Error: Value for 'bus' is out of range(0-255).\n"); + msg_perr("%s: Value for 'bus' is out of range(0-255).\n", + __func__); goto get_bus_done; } if (strlen(bus_suffix) > 0) { - msg_perr("Error: Garbage following 'bus' value.\n"); + msg_perr("%s: Garbage following 'bus' value.\n", + __func__); goto get_bus_done; } @@ -459,7 +463,7 @@ ret = bus; goto get_bus_done; } else { - msg_perr("Error: Bus number not specified.\n"); + msg_perr("%s: Bus number not specified.\n", __func__); } get_bus_done: if (bus_str) -- To view, visit https://review.coreboot.org/c/flashrom/+/40903 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I34d326a9b40a95334995db2c6de80cfb7d133b03 Gerrit-Change-Number: 40903 Gerrit-PatchSet: 1 Gerrit-Owner: Shiyu Sun <sshiyu(a)google.com> Gerrit-MessageType: newchange

1 1

Change in flashrom[master]: ft2232_spi.c: Pack WREN and op in one ftdi_write_data() call to save ...
by Simon Buhrow (Code Review) 28 Apr '20

28 Apr '20

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/40477 to look at the new patch set (#7). Change subject: ft2232_spi.c: Pack WREN and op in one ftdi_write_data() call to save programming time ...................................................................... ft2232_spi.c: Pack WREN and op in one ftdi_write_data() call to save programming time Every ftdi_write_data() call is quite time consuming as the ftdi-chips seems to take always 2-3ms to respond. This leads to what the comment already says: Minimize USB transfers by packing as many commands as possible together. So I packed the WREN command together with the following operation which can be program or erase operation. This saves about 1 minute when programming a 128MBit Flash with my config! See timings WREN in extra ftdi_write_data() call: https://ibb.co/0c1J25d WREN packed with op: https://ibb.co/7G1hLkj I´m using ftdi-2232H chip. That´s why I put it at this place. If anyone has a good overview about all programmers: This could be implemented in spi_write_cmd() in case that it is compatible to all programmers or this principle could be transfered to other programmers which act in a similar way. Signed-off-by: Simon Buhrow <simon.buhrow(a)posteo.de> Change-Id: Ie4a07499ec5ef0af23818593f45dc427285a9e8a --- M ft2232_spi.c 1 file changed, 18 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/77/40477/7 -- To view, visit https://review.coreboot.org/c/flashrom/+/40477 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ie4a07499ec5ef0af23818593f45dc427285a9e8a Gerrit-Change-Number: 40477 Gerrit-PatchSet: 7 Gerrit-Owner: Simon Buhrow Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

1 0

Change in flashrom[master]: flashchips: port S25FS(128S) chip from chromiumos
by Samir Ibradžić (Code Review) 28 Apr '20

28 Apr '20

Samir Ibradžić has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/39822 ) Change subject: flashchips: port S25FS(128S) chip from chromiumos ...................................................................... flashchips: port S25FS(128S) chip from chromiumos This may seem too big just to support yet another flash chip, but in reality it brings support for whole new family of S25FS Spansion/Cypress flash chips. These chips require handling of some special status registers for erasing or writing, with very specific timing checks in place. For example, WIP status bit will remain being set to 1 if erase or programming errors occur, and in that case chip 'software reset' has to be performed otherwise the chip will remain unresponsive to all further commands. Also, special CR3NV register (Configuration Register 3 Nonvolatile) status bits needs to be read and set by using RDAR (ReaD Any Register) and WRAR (WRite Any Register) OP commands, and these states are needed to determine whether which type of reset feature is enabled at the time (legacy or SF25FS type) in the first place, determine whether Uniform or Hybrid sector architecture is used at the time, or programming buffer address wrap point (256 or 512 bytes). Furthermore, S25FS chip status register has to be restored to its original state (hence that ugly CHIP_RESTORE_CALLBACK) following erasing or writing, failing to do so may result in host being unable to access data on the chip at all. Finally, although this brings support for the whole family of chips, I only have one such chip to do actual testing, S25FS128S (Small Sectors), which I fully tested on ch341a and FT4232H programmers, with confirmed working probe, read, erase and write. The full summary of changes are here: flashchips: add new flashchip sctructure property: .reset add chip definitions: S25FS128S Large Sectors S25FS128S Small Sectors flash: add macro (chip_restore_func_data call-back): CHIP_RESTORE_CALLBACK flashrom: add struct: chip_restore_func_data add call-back function: register_chip_restore spi: add OP codes: CMD_RDAR, CMD_WRAR, CMD_WRAR_LEN, CMD_RSTEN, CMD_RST add register bit function definitions: CR3NV_ADDR, CR3NV_20H_NV add timers: T_W, T_RPH, T_SE spi25: refactor (based on chromiumos implementation) function: spi_poll_wip port these functions from chromiumos: probe_spi_big_spansion s25fs_software_reset s25f_legacy_software_reset s25fs_block_erase_d8 spi25_statusreg: port these functions from chromiumos: spi_restore_status s25fs_read_cr s25fs_write_cr s25fs_restore_cr3nv Change-Id: If659290874a4b9db6e71256bdef382d31b288e72 Signed-off-by: Samir Ibradzic <sibradzic(a)gmail.com> --- M chipdrivers.h M flash.h M flashchips.c M flashchips.h M flashrom.c M spi.h M spi25.c M spi25_statusreg.c 8 files changed, 415 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/22/39822/1 diff --git a/chipdrivers.h b/chipdrivers.h index cb1e877..aa24085 100644 --- a/chipdrivers.h +++ b/chipdrivers.h @@ -35,6 +35,9 @@ int probe_spi_res2(struct flashctx *flash); int probe_spi_res3(struct flashctx *flash); int probe_spi_at25f(struct flashctx *flash); +int probe_spi_big_spansion(struct flashctx *flash); +int s25fs_software_reset(struct flashctx *flash); +int spi_poll_wip(struct flashctx *const flash, const unsigned int poll_delay); int spi_write_enable(struct flashctx *flash); int spi_write_disable(struct flashctx *flash); int spi_block_erase_20(struct flashctx *flash, unsigned int addr, unsigned int blocklen); @@ -49,6 +52,7 @@ int spi_block_erase_c7(struct flashctx *flash, unsigned int addr, unsigned int blocklen); int spi_block_erase_d7(struct flashctx *flash, unsigned int addr, unsigned int blocklen); int spi_block_erase_d8(struct flashctx *flash, unsigned int addr, unsigned int blocklen); +int s25fs_block_erase_d8(struct flashctx *flash, unsigned int addr, unsigned int blocklen); int spi_block_erase_db(struct flashctx *flash, unsigned int addr, unsigned int blocklen); int spi_block_erase_dc(struct flashctx *flash, unsigned int addr, unsigned int blocklen); erasefunc_t *spi_get_erasefn_from_opcode(uint8_t opcode); @@ -60,10 +64,12 @@ int spi_exit_4ba(struct flashctx *flash); int spi_set_extended_address(struct flashctx *, uint8_t addr_high); - /* spi25_statusreg.c */ uint8_t spi_read_status_register(struct flashctx *flash); int spi_write_status_register(struct flashctx *flash, int status); +int s25fs_read_cr(struct flashctx *const flash, uint32_t addr); +int s25fs_write_cr(struct flashctx *const flash, uint32_t addr, uint8_t data); +int s25fs_restore_cr3nv(struct flashctx *const flash, uint8_t cfg); void spi_prettyprint_status_register_bit(uint8_t status, int bit); int spi_prettyprint_status_register_plain(struct flashctx *flash); int spi_prettyprint_status_register_default_welwip(struct flashctx *flash); diff --git a/flash.h b/flash.h index 1a9bd9f..1ee0f0f 100644 --- a/flash.h +++ b/flash.h @@ -54,6 +54,8 @@ #define PRIxPTR_WIDTH ((int)(sizeof(uintptr_t)*2)) int register_shutdown(int (*function) (void *data), void *data); +#define CHIP_RESTORE_CALLBACK int (*func) (struct flashrom_flashctx *flash, uint8_t status) +int register_chip_restore(CHIP_RESTORE_CALLBACK, struct flashrom_flashctx *flash, uint8_t status); int shutdown_free(void *data); void *programmer_map_flash_region(const char *descr, uintptr_t phys_addr, size_t len); void programmer_unmap_flash_region(void *virt_addr, size_t len); @@ -207,6 +209,7 @@ SPI_EDI = 1, } spi_cmd_set; + int (*reset) (struct flashctx *flash); int (*probe) (struct flashctx *flash); /* Delay after "enter/exit ID mode" commands in microseconds. diff --git a/flashchips.c b/flashchips.c index 942cbc2..8881804 100644 --- a/flashchips.c +++ b/flashchips.c @@ -49,6 +49,7 @@ * .eraseblocks[] = Array of { blocksize, blockcount } * .block_erase = Block erase function * } + * .reset = Reset Chip * .printlock = Chip lock status function * .unlock = Chip unlock function * .write = Chip write function @@ -15787,6 +15788,69 @@ { .vendor = "Spansion", + .name = "S25FS128S Large Sectors", + .bustype = BUS_SPI, + .manufacture_id = SPANSION_ID, + .model_id = SPANSION_S25FS128S_L, + .total_size = 16384, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_UNTESTED, + .probe = probe_spi_big_spansion, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {64 * 1024, 256} }, + .block_erase = s25fs_block_erase_d8, + }, { + .eraseblocks = { {16 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {16 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + }, + }, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {1700, 2000}, + }, + + { + .vendor = "Spansion", + .name = "S25FS128S Small Sectors", + .bustype = BUS_SPI, + .manufacture_id = SPANSION_ID, + .model_id = SPANSION_S25FS128S_S, + .total_size = 16384, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_OK_PREW, + .probe = probe_spi_big_spansion, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {64 * 1024, 256} }, + .block_erase = s25fs_block_erase_d8, + }, { + .eraseblocks = { {16 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {16 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + }, + }, + .reset = s25fs_software_reset, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {1700, 2000}, + }, + + { + .vendor = "Spansion", .name = "S25FL129P......1", /* uniform 256 kB sectors */ .bustype = BUS_SPI, .manufacture_id = SPANSION_ID, diff --git a/flashchips.h b/flashchips.h index 36990e2..fb2ec53 100644 --- a/flashchips.h +++ b/flashchips.h @@ -641,6 +641,8 @@ #define SPANSION_S25FL032A 0x0215 /* Same as S25FL032P, but the latter supports EDI and CFI */ #define SPANSION_S25FL064A 0x0216 /* Same as S25FL064P, but the latter supports EDI and CFI */ #define SPANSION_S25FL128 0x2018 /* Same ID for various S25FL127S, S25FL128P, S25FL128S and S25FL129P (including dual-die S70FL256P) variants (EDI supported) */ +#define SPANSION_S25FS128S_L 0x20180081 /* Large sectors. */ +#define SPANSION_S25FS128S_S 0x20180181 /* Small sectors. */ #define SPANSION_S25FL256 0x0219 #define SPANSION_S25FL512 0x0220 #define SPANSION_S25FL204 0x4013 diff --git a/flashrom.c b/flashrom.c index e541b68..178c7b6 100644 --- a/flashrom.c +++ b/flashrom.c @@ -488,6 +488,14 @@ {0}, /* This entry corresponds to PROGRAMMER_INVALID. */ }; +#define CHIP_RESTORE_MAXFN 4 +static int chip_restore_fn_count = 0; +static struct chip_restore_func_data { + CHIP_RESTORE_CALLBACK; + struct flashctx *flash; + uint8_t status; +} chip_restore_fn[CHIP_RESTORE_MAXFN]; + #define SHUTDOWN_MAXFN 32 static int shutdown_fn_count = 0; /** @private */ @@ -538,6 +546,23 @@ return 0; } +//int register_chip_restore(int (*function) (void *data), void *data) +int register_chip_restore(CHIP_RESTORE_CALLBACK, + struct flashctx *flash, uint8_t status) +{ + if (chip_restore_fn_count >= CHIP_RESTORE_MAXFN) { + msg_perr("Tried to register more than %i chip restore" + " functions.\n", CHIP_RESTORE_MAXFN); + return 1; + } + chip_restore_fn[chip_restore_fn_count].func = func; /* from macro */ + chip_restore_fn[chip_restore_fn_count].flash = flash; + chip_restore_fn[chip_restore_fn_count].status = status; + chip_restore_fn_count++; + + return 0; +} + int programmer_init(enum programmer prog, const char *param) { int ret; diff --git a/spi.h b/spi.h index 3f45038..12063d7 100644 --- a/spi.h +++ b/spi.h @@ -101,7 +101,7 @@ #define JEDEC_BE_C4_OUTSIZE 0x04 #define JEDEC_BE_C4_INSIZE 0x00 -/* Block Erase 0xd8 is supported by EON/Macronix chips. */ +/* Block Erase 0xd8 is supported by EON/Macronix/Spansion chips. */ #define JEDEC_BE_D8 0xd8 #define JEDEC_BE_D8_OUTSIZE 0x04 #define JEDEC_BE_D8_INSIZE 0x00 @@ -116,6 +116,18 @@ #define JEDEC_SE_OUTSIZE 0x04 #define JEDEC_SE_INSIZE 0x00 +/* RADR, WRAR, RSTEN, RST & CR3NV OPs and timers on Spansion S25FS chips */ +#define CMD_RDAR 0x65 +#define CMD_WRAR 0x71 +#define CMD_WRAR_LEN 5 +#define CMD_RSTEN 0x66 +#define CMD_RST 0x99 +#define CR3NV_ADDR 0x000004 +#define CR3NV_20H_NV (1 << 3) +#define T_W 145 * 1000 /* NV register write time */ +#define T_RPH 35 /* Reset pulse hold time */ +#define T_SE 145 * 1000 /* Sector Erase Time */ + /* Page Erase 0xDB */ #define JEDEC_PE 0xDB #define JEDEC_PE_OUTSIZE 0x04 @@ -129,6 +141,7 @@ /* Status Register Bits */ #define SPI_SR_WIP (0x01 << 0) #define SPI_SR_WEL (0x01 << 1) +#define SPI_SR_ERA_ERR (0x01 << 5) #define SPI_SR_AAI (0x01 << 6) /* Write Status Enable */ diff --git a/spi25.c b/spi25.c index 2a1d492..41fa3e2 100644 --- a/spi25.c +++ b/spi25.c @@ -25,6 +25,7 @@ #include "flashchips.h" #include "chipdrivers.h" #include "programmer.h" +#include "hwaccess.h" #include "spi.h" static int spi_rdid(struct flashctx *flash, unsigned char *readarr, int bytes) @@ -284,13 +285,155 @@ return 0; } -static int spi_poll_wip(struct flashctx *const flash, const unsigned int poll_delay) +/* Used for probing 'big' Spansion/Cypress S25FS chips */ +int probe_spi_big_spansion(struct flashctx *flash) { - /* FIXME: We can't tell if spi_read_status_register() failed. */ + static const unsigned char cmd = JEDEC_RDID; + int ret; + unsigned char dev_id[6]; /* We care only about 6 first bytes */ + + ret = spi_send_command(flash, sizeof(cmd), sizeof(dev_id), &cmd, dev_id); + + if (!ret) { + unsigned long i; + + for (i = 0; i < sizeof(dev_id); i++) + msg_gdbg(" 0x%02x", dev_id[i]); + msg_gdbg(".\n"); + + if (dev_id[0] == flash->chip->manufacture_id) { + union { + uint8_t array[4]; + uint32_t whole; + } model_id; + + /* + * The structure of the RDID output is as follows: + * + * offset value meaning + * 00h 01h Manufacturer ID for Spansion + * 01h 20h 128 Mb capacity + * 01h 02h 256 Mb capacity + * 02h 18h 128 Mb capacity + * 02h 19h 256 Mb capacity + * 03h 4Dh Full size of the RDID output (ignored) + * 04h 00h FS: 256-kB physical sectors + * 04h 01h FS: 64-kB physical sectors + * 04h 00h FL: 256-kB physical sectors + * 04h 01h FL: Mix of 64-kB and 4KB overlayed sectors + * 05h 80h FL family + * 05h 81h FS family + * + * Need to use bytes 1, 2, 4, and 5 to properly identify one of eight + * possible chips: + * + * 2 types * 2 possible sizes * 2 possible sector layouts + * + */ + memcpy(model_id.array, dev_id + 1, 2); + memcpy(model_id.array + 2, dev_id + 4, 2); + if (be_to_cpu32(model_id.whole) == flash->chip->model_id) + return 1; + } + } + + return 0; +} + +/* Used for Spansion/Cypress S25F chips */ +static int s25f_legacy_software_reset(struct flashctx *flash) +{ + int result; + struct spi_command cmds[] = { + { + .writecnt = 1, + .writearr = (const unsigned char[]){ CMD_RSTEN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 1, + .writearr = (const unsigned char[]){ 0xf0 }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; + + result = spi_send_multicommand(flash, cmds); + if (result) { + msg_cerr("%s failed during command execution\n", __func__); + return result; + } + /* Reset takes 35us according to data-sheet, double that for safety */ + programmer_delay(T_RPH * 2); + + return 0; +} + +/* Only for Spansion S25F chips, where legacy reset is disabled by default */ +int s25fs_software_reset(struct flashctx *flash) +{ + int result; + struct spi_command cmds[] = { + { + .writecnt = 1, + .writearr = (const unsigned char[]){ CMD_RSTEN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 1, + .writearr = (const unsigned char[]){ CMD_RST }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; + + msg_cdbg("Force resetting SPI chip.\n"); + result = spi_send_multicommand(flash, cmds); + if (result) { + msg_cerr("%s failed during command execution\n", __func__); + return result; + } + + programmer_delay(T_RPH * 2); + + return 0; +} + +int spi_poll_wip(struct flashctx *const flash, const unsigned int poll_delay) +{ + uint8_t status_reg = spi_read_status_register(flash); + /* FIXME: We don't time out. */ - while (spi_read_status_register(flash) & SPI_SR_WIP) + while (status_reg & SPI_SR_WIP) { + /* + * The WIP bit on S25F chips remains set to 1 if erase or + * programming errors occur, so we must check for those + * errors here. If an error is encountered, do a software + * reset to clear WIP and other volatile bits, otherwise + * the chip will be unresponsive to further commands. + */ + if (status_reg & SPI_SR_ERA_ERR) { + msg_cerr("Erase error occurred\n"); + s25f_legacy_software_reset(flash); + return -1; + } + if (status_reg & (1 << 6)) { + msg_cerr("Programming error occurred\n"); + s25f_legacy_software_reset(flash); + return -1; + } programmer_delay(poll_delay); - /* FIXME: Check the status register for errors. */ + status_reg = spi_read_status_register(flash); + } + return 0; } @@ -486,6 +629,73 @@ return spi_write_cmd(flash, 0xd8, false, addr, NULL, 0, 100 * 1000); } +/* Used on Spansion/Cypress S25FS chips */ +int s25fs_block_erase_d8(struct flashctx *flash, + unsigned int addr, unsigned int blocklen) +{ + unsigned char cfg; + int result; + static int cr3nv_checked = 0; + + struct spi_command erase_cmds[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_BE_D8_OUTSIZE, + .writearr = (const unsigned char[]){ + JEDEC_BE_D8, + (addr >> 16) & 0xff, + (addr >> 8) & 0xff, + (addr & 0xff) + }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; + + /* Check if hybrid sector architecture is in use and, if so, + * switch to uniform sectors. */ + if (!cr3nv_checked) { + cfg = s25fs_read_cr(flash, CR3NV_ADDR); + if (!(cfg & CR3NV_20H_NV)) { + s25fs_write_cr(flash, CR3NV_ADDR, cfg | CR3NV_20H_NV); + s25fs_software_reset(flash); + + cfg = s25fs_read_cr(flash, CR3NV_ADDR); + if (!(cfg & CR3NV_20H_NV)) { + msg_cerr("%s: Unable to enable uniform " + "block sizes.\n", __func__); + return 1; + } + + msg_cdbg("\n%s: CR3NV updated (0x%02x -> 0x%02x)\n", + __func__, cfg, + s25fs_read_cr(flash, CR3NV_ADDR)); + /* Restore CR3V when flashrom exits */ + register_chip_restore(s25fs_restore_cr3nv, flash, cfg); + } + + cr3nv_checked = 1; + } + + result = spi_send_multicommand(flash, erase_cmds); + if (result) { + msg_cerr("%s failed during command execution at address 0x%x\n", + __func__, addr); + return result; + } + + programmer_delay(T_SE); + return spi_poll_wip(flash, 1000 * 10); +} + /* Block size is usually * 4k for PMC */ diff --git a/spi25_statusreg.c b/spi25_statusreg.c index 8cd5a28..aa574d5 100644 --- a/spi25_statusreg.c +++ b/spi25_statusreg.c @@ -108,6 +108,89 @@ return readarr[0]; } +static int spi_restore_status(struct flashctx *flash, uint8_t status) +{ + msg_cdbg("restoring chip status (0x%02x)\n", status); + return spi_write_status_register(flash, status); +} + +/* 'Read Any Register' used on Spansion/Cypress S25FS chips */ +int s25fs_read_cr(struct flashctx *const flash, uint32_t addr) +{ + int result; + uint8_t cfg; + /* By default, 8 dummy cycles are necessary for variable-latency + commands such as RDAR (see CR2NV[3:0]). */ + unsigned char read_cr_cmd[] = { + CMD_RDAR, + (addr >> 16) & 0xff, + (addr >> 8) & 0xff, + (addr & 0xff), + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + }; + + result = spi_send_command(flash, sizeof(read_cr_cmd), 1, read_cr_cmd, &cfg); + if (result) { + msg_cerr("%s failed during command execution at address 0x%x\n", + __func__, addr); + return -1; + } + + return cfg; +} + +/* 'Write Any Register' used on Spansion/Cypress S25FS chips */ +int s25fs_write_cr(struct flashctx *const flash, + uint32_t addr, uint8_t data) +{ + int result; + struct spi_command cmds[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = CMD_WRAR_LEN, + .writearr = (const unsigned char[]){ + CMD_WRAR, + (addr >> 16) & 0xff, + (addr >> 8) & 0xff, + (addr & 0xff), + data + }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; + + result = spi_send_multicommand(flash, cmds); + if (result) { + msg_cerr("%s failed during command execution at address 0x%x\n", + __func__, addr); + return -1; + } + + programmer_delay(T_W); + return spi_poll_wip(flash, 1000 * 10); +} + +/* Used on Spansion/Cypress S25FS chips */ +int s25fs_restore_cr3nv(struct flashctx *const flash, uint8_t cfg) +{ + int ret = 0; + + msg_cdbg("Restoring CR3NV value to 0x%02x\n", cfg); + ret |= s25fs_write_cr(flash, CR3NV_ADDR, cfg); + ret |= s25fs_software_reset(flash); + return ret; +} + /* A generic block protection disable. * Tests if a protection is enabled with the block protection mask (bp_mask) and returns success otherwise. * Tests if the register bits are locked with the lock_mask (lock_mask). @@ -139,6 +222,9 @@ return 0; } + /* restore status register content upon exit */ + register_chip_restore(spi_restore_status, flash, status); + msg_cdbg("Some block protection in effect, disabling... "); if ((status & lock_mask) != 0) { msg_cdbg("\n\tNeed to disable the register lock first... "); -- To view, visit https://review.coreboot.org/c/flashrom/+/39822 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: If659290874a4b9db6e71256bdef382d31b288e72 Gerrit-Change-Number: 39822 Gerrit-PatchSet: 1 Gerrit-Owner: Samir Ibradžić <sibradzic(a)gmail.com> Gerrit-MessageType: newchange

5 13

Change in flashrom[master]: ft2232_spi.c - Pack WREN and op in one ftdi_write_data() call to save...
by Simon Buhrow (Code Review) 27 Apr '20

27 Apr '20

Simon Buhrow has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/40477 ) Change subject: ft2232_spi.c - Pack WREN and op in one ftdi_write_data() call to save programming time ...................................................................... Patch Set 6: (1 comment) > Patch Set 3: > > (1 comment) https://review.coreboot.org/c/flashrom/+/40477/2/ft2232_spi.c File ft2232_spi.c: https://review.coreboot.org/c/flashrom/+/40477/2/ft2232_spi.c@549 PS2, Line 549: return 0; > Well, in the usual use case with maximum buf size equal to normal page program operations, I agree. […] Done in patchset 6: Set buf to fix size to fix realloc issue. -- To view, visit https://review.coreboot.org/c/flashrom/+/40477 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ie4a07499ec5ef0af23818593f45dc427285a9e8a Gerrit-Change-Number: 40477 Gerrit-PatchSet: 6 Gerrit-Owner: Simon Buhrow Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 27 Apr 2020 08:29:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Simon Buhrow Comment-In-Reply-To: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: comment

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flashrom-gerrit April 2020