October 2018 - flashrom-gerrit

Change in flashrom[master]: ati: add fiji family
by Luc Verhaegen (Code Review) 22 Oct '18

22 Oct '18

Luc Verhaegen has uploaded this change for review. ( https://review.coreboot.org/29218 Change subject: ati: add fiji family ...................................................................... ati: add fiji family Change-Id: I7ab1a18597067301959c77cc555bda23d48c2862 Signed-off-by: Luc Verhaegen <libv(a)skynet.be> --- M ati_spi.c 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/18/29218/1 diff --git a/ati_spi.c b/ati_spi.c index cd48020..9988ce7 100644 --- a/ati_spi.c +++ b/ati_spi.c @@ -773,7 +773,7 @@ }; /* - * Used by Iceland, Tonga + * Used by Iceland, Tonga, Fiji */ static const struct ati_spi_pci_private iceland_spi_pci_private = { .io_bar = CI_MMIO_BAR, @@ -899,6 +899,7 @@ {0x1002, 0x692F, NT, &iceland_spi_pci_private}, {0x1002, 0x6938, NT, &iceland_spi_pci_private}, {0x1002, 0x6939, NT, &iceland_spi_pci_private}, + {0x1002, 0x7300, NT, &iceland_spi_pci_private}, {0x1002, 0x9400, NT, &r600_spi_pci_private}, {0x1002, 0x9401, NT, &r600_spi_pci_private}, {0x1002, 0x9402, NT, &r600_spi_pci_private}, -- To view, visit https://review.coreboot.org/29218 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I7ab1a18597067301959c77cc555bda23d48c2862 Gerrit-Change-Number: 29218 Gerrit-PatchSet: 1 Gerrit-Owner: Luc Verhaegen <libv(a)skynet.be>

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Change in flashrom[master]: ati: add iceland family
by Luc Verhaegen (Code Review) 22 Oct '18

22 Oct '18

Luc Verhaegen has uploaded this change for review. ( https://review.coreboot.org/29216 Change subject: ati: add iceland family ...................................................................... ati: add iceland family Change-Id: I6f02d0db4408fcad5cde19c4f4c27484fad3598f Signed-off-by: Luc Verhaegen <libv(a)skynet.be> --- M ati_spi.c 1 file changed, 20 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/16/29216/1 diff --git a/ati_spi.c b/ati_spi.c index f327da1..4cfa1b1 100644 --- a/ati_spi.c +++ b/ati_spi.c @@ -36,6 +36,7 @@ ATI_SPI_TYPE_SOUTHERN_ISLAND, ATI_SPI_TYPE_BONAIRE, /* First of sea island type spi interface */ ATI_SPI_TYPE_HAWAII, + ATI_SPI_TYPE_ICELAND, }; struct ati_spi_pci_private { @@ -586,8 +587,10 @@ mmio_mask(CI_GPIOPAD_A, 0x40000000, 0x40000000); } - /* disable open drain pads */ - smc_mask(CI_GENERAL_PWRMGT, 0, 0x0800); + if ((private->type != ATI_SPI_TYPE_BONAIRE) && + (private->type != ATI_SPI_TYPE_HAWAII)) + /* disable open drain pads */ + smc_mask(CI_GENERAL_PWRMGT, 0, 0x0800); programmer_delay(1000); @@ -769,6 +772,18 @@ .master = &ci_spi_master, }; +/* + * Used by Iceland + */ +static const struct ati_spi_pci_private iceland_spi_pci_private = { + .io_bar = CI_MMIO_BAR, + .type = ATI_SPI_TYPE_ICELAND, + .save = ci_spi_save, + .restore = ci_spi_restore, + .enable = ci_spi_enable, + .master = &ci_spi_master, +}; + const struct flashrom_pci_match ati_spi_pci_devices[] = { {0x1002, 0x6640, NT, &bonaire_spi_pci_private}, {0x1002, 0x6641, NT, &bonaire_spi_pci_private}, @@ -875,6 +890,9 @@ {0x1002, 0x68F9, NT, &evergreen_spi_pci_private}, {0x1002, 0x68FA, NT, &evergreen_spi_pci_private}, {0x1002, 0x68FE, NT, &evergreen_spi_pci_private}, + {0x1002, 0x6900, NT, &iceland_spi_pci_private}, + {0x1002, 0x6901, NT, &iceland_spi_pci_private}, + {0x1002, 0x6907, NT, &iceland_spi_pci_private}, {0x1002, 0x9400, NT, &r600_spi_pci_private}, {0x1002, 0x9401, NT, &r600_spi_pci_private}, {0x1002, 0x9402, NT, &r600_spi_pci_private}, -- To view, visit https://review.coreboot.org/29216 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I6f02d0db4408fcad5cde19c4f4c27484fad3598f Gerrit-Change-Number: 29216 Gerrit-PatchSet: 1 Gerrit-Owner: Luc Verhaegen <libv(a)skynet.be>

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Change in flashrom[master]: ati: add tonga family
by Luc Verhaegen (Code Review) 22 Oct '18

22 Oct '18

Luc Verhaegen has uploaded this change for review. ( https://review.coreboot.org/29217 Change subject: ati: add tonga family ...................................................................... ati: add tonga family Change-Id: If5585f760687e761bb39dc5de869cdc2ba8db5db Signed-off-by: Luc Verhaegen <libv(a)skynet.be> --- M ati_spi.c 1 file changed, 7 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/17/29217/1 diff --git a/ati_spi.c b/ati_spi.c index 4cfa1b1..cd48020 100644 --- a/ati_spi.c +++ b/ati_spi.c @@ -773,7 +773,7 @@ }; /* - * Used by Iceland + * Used by Iceland, Tonga */ static const struct ati_spi_pci_private iceland_spi_pci_private = { .io_bar = CI_MMIO_BAR, @@ -893,6 +893,12 @@ {0x1002, 0x6900, NT, &iceland_spi_pci_private}, {0x1002, 0x6901, NT, &iceland_spi_pci_private}, {0x1002, 0x6907, NT, &iceland_spi_pci_private}, + {0x1002, 0x6921, NT, &iceland_spi_pci_private}, + {0x1002, 0x6929, NT, &iceland_spi_pci_private}, + {0x1002, 0x692B, NT, &iceland_spi_pci_private}, + {0x1002, 0x692F, NT, &iceland_spi_pci_private}, + {0x1002, 0x6938, NT, &iceland_spi_pci_private}, + {0x1002, 0x6939, NT, &iceland_spi_pci_private}, {0x1002, 0x9400, NT, &r600_spi_pci_private}, {0x1002, 0x9401, NT, &r600_spi_pci_private}, {0x1002, 0x9402, NT, &r600_spi_pci_private}, -- To view, visit https://review.coreboot.org/29217 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: If5585f760687e761bb39dc5de869cdc2ba8db5db Gerrit-Change-Number: 29217 Gerrit-PatchSet: 1 Gerrit-Owner: Luc Verhaegen <libv(a)skynet.be>

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Change in flashrom[master]: ati: add further bonaire ids
by Luc Verhaegen (Code Review) 22 Oct '18

22 Oct '18

Luc Verhaegen has uploaded this change for review. ( https://review.coreboot.org/29214 Change subject: ati: add further bonaire ids ...................................................................... ati: add further bonaire ids Change-Id: I5a8a948429677fd909e6db9b81e67d47b2e9d385 Signed-off-by: Luc Verhaegen <libv(a)skynet.be> --- M ati_spi.c 1 file changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/14/29214/1 diff --git a/ati_spi.c b/ati_spi.c index e9e049e..790ee2f 100644 --- a/ati_spi.c +++ b/ati_spi.c @@ -757,6 +757,16 @@ }; const struct flashrom_pci_match ati_spi_pci_devices[] = { + {0x1002, 0x6640, NT, &bonaire_spi_pci_private}, + {0x1002, 0x6641, NT, &bonaire_spi_pci_private}, + {0x1002, 0x6646, NT, &bonaire_spi_pci_private}, + {0x1002, 0x6647, NT, &bonaire_spi_pci_private}, + {0x1002, 0x6649, NT, &bonaire_spi_pci_private}, + {0x1002, 0x6650, NT, &bonaire_spi_pci_private}, + {0x1002, 0x6651, NT, &bonaire_spi_pci_private}, + {0x1002, 0x6658, NT, &bonaire_spi_pci_private}, + {0x1002, 0x665C, NT, &bonaire_spi_pci_private}, + {0x1002, 0x665D, NT, &bonaire_spi_pci_private}, {0x1002, 0x665F, OK, &bonaire_spi_pci_private}, {0x1002, 0x6704, NT, &northern_island_spi_pci_private}, {0x1002, 0x6707, NT, &northern_island_spi_pci_private}, -- To view, visit https://review.coreboot.org/29214 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I5a8a948429677fd909e6db9b81e67d47b2e9d385 Gerrit-Change-Number: 29214 Gerrit-PatchSet: 1 Gerrit-Owner: Luc Verhaegen <libv(a)skynet.be>

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Change in flashrom[master]: ati: add hawaii family
by Luc Verhaegen (Code Review) 22 Oct '18

22 Oct '18

Luc Verhaegen has uploaded this change for review. ( https://review.coreboot.org/29215 Change subject: ati: add hawaii family ...................................................................... ati: add hawaii family Change-Id: Idaf243422aa1b940b2da51551f4f20ec81eb4ac0 Signed-off-by: Luc Verhaegen <libv(a)skynet.be> --- M ati_spi.c 1 file changed, 24 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/15/29215/1 diff --git a/ati_spi.c b/ati_spi.c index 790ee2f..f327da1 100644 --- a/ati_spi.c +++ b/ati_spi.c @@ -34,7 +34,8 @@ ATI_SPI_TYPE_EVERGREEN, ATI_SPI_TYPE_NORTHERN_ISLAND, ATI_SPI_TYPE_SOUTHERN_ISLAND, - ATI_SPI_TYPE_BONAIRE, + ATI_SPI_TYPE_BONAIRE, /* First of sea island type spi interface */ + ATI_SPI_TYPE_HAWAII, }; struct ati_spi_pci_private { @@ -756,6 +757,18 @@ .master = &ci_spi_master, }; +/* + * Used by Hawaii + */ +static const struct ati_spi_pci_private hawaii_spi_pci_private = { + .io_bar = CI_MMIO_BAR, + .type = ATI_SPI_TYPE_HAWAII, + .save = ci_spi_save, + .restore = ci_spi_restore, + .enable = ci_spi_enable, + .master = &ci_spi_master, +}; + const struct flashrom_pci_match ati_spi_pci_devices[] = { {0x1002, 0x6640, NT, &bonaire_spi_pci_private}, {0x1002, 0x6641, NT, &bonaire_spi_pci_private}, @@ -806,6 +819,16 @@ {0x1002, 0x6778, NT, &northern_island_spi_pci_private}, {0x1002, 0x6779, NT, &northern_island_spi_pci_private}, {0x1002, 0x677B, NT, &northern_island_spi_pci_private}, + {0x1002, 0x67A0, NT, &hawaii_spi_pci_private}, + {0x1002, 0x67A1, NT, &hawaii_spi_pci_private}, + {0x1002, 0x67A2, NT, &hawaii_spi_pci_private}, + {0x1002, 0x67A8, NT, &hawaii_spi_pci_private}, + {0x1002, 0x67A9, NT, &hawaii_spi_pci_private}, + {0x1002, 0x67AA, NT, &hawaii_spi_pci_private}, + {0x1002, 0x67B0, NT, &hawaii_spi_pci_private}, + {0x1002, 0x67B1, NT, &hawaii_spi_pci_private}, + {0x1002, 0x67B9, NT, &hawaii_spi_pci_private}, + {0x1002, 0x67BE, NT, &hawaii_spi_pci_private}, {0x1002, 0x6840, NT, &southern_island_spi_pci_private}, {0x1002, 0x6841, NT, &southern_island_spi_pci_private}, {0x1002, 0x6842, NT, &southern_island_spi_pci_private}, -- To view, visit https://review.coreboot.org/29215 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Idaf243422aa1b940b2da51551f4f20ec81eb4ac0 Gerrit-Change-Number: 29215 Gerrit-PatchSet: 1 Gerrit-Owner: Luc Verhaegen <libv(a)skynet.be>

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Change in flashrom[master]: ati: implement sea-island save/restore
by Luc Verhaegen (Code Review) 22 Oct '18

22 Oct '18

Luc Verhaegen has uploaded this change for review. ( https://review.coreboot.org/29211 Change subject: ati: implement sea-island save/restore ...................................................................... ati: implement sea-island save/restore The Sea Island SPI engine is pretty much the R600 SPI, it is just "hidden" behind indexed registers. Change-Id: I2f67b3ae9b6558d42e44522eeb68d28d62a0c139 Signed-off-by: Luc Verhaegen <libv(a)skynet.be> --- M ati_spi.c 1 file changed, 57 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/11/29211/1 diff --git a/ati_spi.c b/ati_spi.c index d01b0df..4155cf3 100644 --- a/ati_spi.c +++ b/ati_spi.c @@ -423,10 +423,47 @@ */ #define CI_MMIO_BAR 5 +#define CI_SMC1_INDEX 0x0208 +#define CI_SMC1_DATA 0x020C + +#define CI_GPIOPAD_MASK 0x0608 +#define CI_GPIOPAD_A 0x060C +#define CI_GPIOPAD_EN 0x0610 + +#define CI_DRM_ID_STRAPS 0x5564 + +#define CI_GENERAL_PWRMGT 0xC0200000 + +#define CI_ROM_CNTL 0xC0600000 +#define CI_PAGE_MIRROR_CNTL 0xC0600004 + #define CI_SPI_TRANSFER_SIZE 0x100 +static uint32_t +_ci_smc_read(struct flashrom_pci_device *device, off_t address) +{ + mmio_write(CI_SMC1_INDEX, address); + return mmio_read(CI_SMC1_DATA); +} +#define smc_read(reg) _ci_smc_read(device, (reg)) + +static void +_ci_smc_write(struct flashrom_pci_device *device, off_t address, uint32_t value) +{ + mmio_write(CI_SMC1_INDEX, address); + mmio_write(CI_SMC1_DATA, value); +} +#define smc_write(reg, val) _ci_smc_write(device, (reg), (val)) + struct ci_spi_data { - uint32_t empty; + uint32_t reg_gpiopad_mask; + uint32_t reg_gpiopad_a; + uint32_t reg_gpiopad_en; + + uint32_t reg_general_pwrmgt; + + uint32_t reg_rom_cntl; + uint32_t reg_page_mirror_cntl; }; /* @@ -447,6 +484,15 @@ data = calloc(1, sizeof(struct ci_spi_data)); + data->reg_general_pwrmgt = smc_read(CI_GENERAL_PWRMGT); + + data->reg_rom_cntl = smc_read(CI_ROM_CNTL); + data->reg_page_mirror_cntl = smc_read(CI_PAGE_MIRROR_CNTL); + + data->reg_gpiopad_mask = mmio_read(CI_GPIOPAD_MASK); + data->reg_gpiopad_a = mmio_read(CI_GPIOPAD_A); + data->reg_gpiopad_en = mmio_read(CI_GPIOPAD_EN); + device->private_data = data; return 0; @@ -468,6 +514,16 @@ return -1; } + smc_write(CI_ROM_CNTL, data->reg_rom_cntl); + + mmio_write(CI_GPIOPAD_A, data->reg_gpiopad_a); + mmio_write(CI_GPIOPAD_EN, data->reg_gpiopad_en); + mmio_write(CI_GPIOPAD_MASK, data->reg_gpiopad_mask); + + smc_write(CI_GENERAL_PWRMGT, data->reg_general_pwrmgt); + + smc_write(CI_PAGE_MIRROR_CNTL, data->reg_page_mirror_cntl); + free(data); device->private_data = NULL; -- To view, visit https://review.coreboot.org/29211 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I2f67b3ae9b6558d42e44522eeb68d28d62a0c139 Gerrit-Change-Number: 29211 Gerrit-PatchSet: 1 Gerrit-Owner: Luc Verhaegen <libv(a)skynet.be>

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Change in flashrom[master]: ati: implement sea-island spi_enable
by Luc Verhaegen (Code Review) 22 Oct '18

22 Oct '18

Luc Verhaegen has uploaded this change for review. ( https://review.coreboot.org/29212 Change subject: ati: implement sea-island spi_enable ...................................................................... ati: implement sea-island spi_enable Change-Id: I18a5ee484004f5a299b056640a92150fd9932a60 Signed-off-by: Luc Verhaegen <libv(a)skynet.be> --- M ati_spi.c 1 file changed, 73 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/12/29212/1 diff --git a/ati_spi.c b/ati_spi.c index 4155cf3..dc0ed2d 100644 --- a/ati_spi.c +++ b/ati_spi.c @@ -436,6 +436,9 @@ #define CI_ROM_CNTL 0xC0600000 #define CI_PAGE_MIRROR_CNTL 0xC0600004 +#define CI_ROM_SW_STATUS 0xC0600020 + +#define CI_ROM_SW_STATUS_LOOP_COUNT 1000 #define CI_SPI_TRANSFER_SIZE 0x100 @@ -455,6 +458,15 @@ } #define smc_write(reg, val) _ci_smc_write(device, (reg), (val)) +static void +_ci_smc_mask(struct flashrom_pci_device *device, off_t address, + uint32_t value, uint32_t mask) +{ + mmio_write(CI_SMC1_INDEX, address); + mmio_mask(CI_SMC1_DATA, value, mask); +} +#define smc_mask(reg, val, mask) _ci_smc_mask(device, (reg), (val), (mask)) + struct ci_spi_data { uint32_t reg_gpiopad_mask; uint32_t reg_gpiopad_a; @@ -536,8 +548,69 @@ static int ci_spi_enable(struct flashrom_pci_device *device) { + const struct ati_spi_pci_private *private = device->private; + int i; + msg_pdbg("%s();\n", __func__); + /* set sck divider to 1 */ + smc_mask(CI_ROM_CNTL, 0x10000000, 0xF0000000); + /* software enable clock gating */ + if (private->type == ATI_SPI_TYPE_BONAIRE) { + uint32_t drm = mmio_read(CI_DRM_ID_STRAPS); + + if (drm & 0xF0000000) + smc_mask(CI_ROM_CNTL, 0, 0x0000002); + else + smc_mask(CI_ROM_CNTL, 0x0000002, 0x0000002); + } else + smc_mask(CI_ROM_CNTL, 0x00000002, 0x00000002); + + /* set gpio7,8,9 low */ + mmio_mask(CI_GPIOPAD_A, 0, 0x0700); + /* gpio7 is input, gpio8/9 are output */ + mmio_mask(CI_GPIOPAD_EN, 0x0600, 0x0700); + /* only allow software control on gpio7,8,9 */ + mmio_mask(CI_GPIOPAD_MASK, 0x0700, 0x0700); + + if (private->type != ATI_SPI_TYPE_BONAIRE) { + mmio_mask(CI_GPIOPAD_MASK, 0x40000000, 0x40000000); + mmio_mask(CI_GPIOPAD_EN, 0x40000000, 0x40000000); + mmio_mask(CI_GPIOPAD_A, 0x40000000, 0x40000000); + } + + /* disable open drain pads */ + smc_mask(CI_GENERAL_PWRMGT, 0, 0x0800); + + programmer_delay(1000); + + mmio_mask(CI_GPIOPAD_MASK, 0, 0x700); + mmio_mask(CI_GPIOPAD_EN, 0, 0x700); + mmio_mask(CI_GPIOPAD_A, 0, 0x700); + + /* this feels like a remnant of generations past */ + mmio_mask(CI_GPIOPAD_MASK, 0, 0x80000); + mmio_mask(CI_GPIOPAD_EN, 0, 0x80000); + mmio_mask(CI_GPIOPAD_A, 0, 0x80000); + + /* page mirror usage */ + smc_mask(CI_PAGE_MIRROR_CNTL, 0x04000000, 0x0C000000); + + if (smc_read(CI_ROM_SW_STATUS)) { + for (i = 0; i < CI_ROM_SW_STATUS_LOOP_COUNT; i++) { + smc_write(CI_ROM_SW_STATUS, 0); + programmer_delay(1000); + if (!smc_read(CI_ROM_SW_STATUS)) + break; + } + + if (i == CI_ROM_SW_STATUS_LOOP_COUNT) { + msg_perr("%s: failed to clear CI_ROM_SW_STATUS\n", + __func__); + return -1; + } + } + return 0; } -- To view, visit https://review.coreboot.org/29212 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I18a5ee484004f5a299b056640a92150fd9932a60 Gerrit-Change-Number: 29212 Gerrit-PatchSet: 1 Gerrit-Owner: Luc Verhaegen <libv(a)skynet.be>

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Change in flashrom[master]: ati: implement sea-island spi_command
by Luc Verhaegen (Code Review) 22 Oct '18

22 Oct '18

Luc Verhaegen has uploaded this change for review. ( https://review.coreboot.org/29213 Change subject: ati: implement sea-island spi_command ...................................................................... ati: implement sea-island spi_command Bonaire is special in that its data registers 0xd8 through 0xE4 are shifted up by 0x10. Change-Id: Iab69973af56beb5818411932db1d8a3e6519b468 Signed-off-by: Luc Verhaegen <libv(a)skynet.be> --- M ati_spi.c 1 file changed, 94 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/13/29213/1 diff --git a/ati_spi.c b/ati_spi.c index dc0ed2d..e9e049e 100644 --- a/ati_spi.c +++ b/ati_spi.c @@ -436,7 +436,13 @@ #define CI_ROM_CNTL 0xC0600000 #define CI_PAGE_MIRROR_CNTL 0xC0600004 +#define CI_ROM_SW_CNTL 0xC060001C #define CI_ROM_SW_STATUS 0xC0600020 +#define CI_ROM_SW_COMMAND 0xC0600024 +#define CI_ROM_SW_DATA_0x00 0xC0600028 +/* ... */ +#define CI_ROM_SW_DATA_0xFC 0xC0600124 +#define CI_ROM_SW_DATA(off) (CI_ROM_SW_DATA_0x00 + (off)) #define CI_ROM_SW_STATUS_LOOP_COUNT 1000 @@ -625,6 +631,9 @@ const struct spi_master spi_master = flash->mst->spi; struct flashrom_pci_device *device = (struct flashrom_pci_device *) spi_master.data; + const struct ati_spi_pci_private *private = device->private; + uint32_t command, control; + int i, command_size; msg_pdbg("%s(%p(%p), %d, %d, %p (0x%02X), %p);\n", __func__, flash, device, writecnt, readcnt, writearr, writearr[0], readarr); @@ -634,6 +643,91 @@ return -1; } + command = writearr[0]; + if (writecnt > 1) + command |= writearr[1] << 24; + if (writecnt > 2) + command |= writearr[2] << 16; + if (writecnt > 3) + command |= writearr[3] << 8; + + if (writecnt < 4) + command_size = writecnt; + else + command_size = 4; + + smc_write(CI_ROM_SW_COMMAND, command); + + /* + * For some reason, we have an endianness difference between reading + * and writing. Also, ati hw only does 32bit register write accesses. + * If you write 8bits, the upper bytes will be nulled. Reading is fine. + * Furthermore, due to flashrom infrastructure, we need to skip the + * command in the writearr. + */ + for (i = 4; i < writecnt; i += 4) { + uint32_t value = 0; + int remainder = writecnt - i; + + if (remainder > 4) + remainder = 4; + + if (remainder > 0) + value |= writearr[i + 0] << 24; + if (remainder > 1) + value |= writearr[i + 1] << 16; + if (remainder > 2) + value |= writearr[i + 2] << 8; + if (remainder > 3) + value |= writearr[i + 3] << 0; + + /* Bonaire has a gap between 0xD8 and 0xE8 */ + if ((private->type == ATI_SPI_TYPE_BONAIRE) && (i >= 0xdc)) + smc_write(CI_ROM_SW_DATA(i + 0x0C), value); + else + smc_write(CI_ROM_SW_DATA(i - 4), value); + } + + control = (command_size - 1) << 0x10; + if (readcnt) + control |= 0x40000 | readcnt; + else if (writecnt > 4) + control |= writecnt - 4; + smc_write(CI_ROM_SW_CNTL, control); + + for (i = 0; i < CI_ROM_SW_STATUS_LOOP_COUNT; i++) { + if (smc_read(CI_ROM_SW_STATUS)) + break; + programmer_delay(1000); + } + + if (i == CI_ROM_SW_STATUS_LOOP_COUNT) { + msg_perr("%s: still waiting for CI_ROM_SW_STATUS\n", + __func__); + return -1; + } + smc_write(CI_ROM_SW_STATUS, 0); + + for (i = 0; i < readcnt; i += 4) { + uint32_t value; + int remainder = readcnt - i; + + /* Bonaire has a gap between 0xD8 and 0xE8 */ + if ((private->type == ATI_SPI_TYPE_BONAIRE) && (i >= 0xd8)) + value = smc_read(CI_ROM_SW_DATA(i + 0x10)); + else + value = smc_read(CI_ROM_SW_DATA(i)); + + if (remainder > 0) + readarr[i] = value; + if (remainder > 1) + readarr[i + 1] = value >> 8; + if (remainder > 2) + readarr[i + 2] = value >> 16; + if (remainder > 3) + readarr[i + 3] = value >> 24; + } + return 0; } -- To view, visit https://review.coreboot.org/29213 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Iab69973af56beb5818411932db1d8a3e6519b468 Gerrit-Change-Number: 29213 Gerrit-PatchSet: 1 Gerrit-Owner: Luc Verhaegen <libv(a)skynet.be>

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Change in flashrom[master]: ati: add boilerplate sea island spi support
by Luc Verhaegen (Code Review) 22 Oct '18

22 Oct '18

Luc Verhaegen has uploaded this change for review. ( https://review.coreboot.org/29210 Change subject: ati: add boilerplate sea island spi support ...................................................................... ati: add boilerplate sea island spi support Change-Id: I28c3fb8d15a7bc4fc044e04d04646011fb107e70 Signed-off-by: Luc Verhaegen <libv(a)skynet.be> --- M ati_spi.c 1 file changed, 117 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/10/29210/1 diff --git a/ati_spi.c b/ati_spi.c index 7c0f073..d01b0df 100644 --- a/ati_spi.c +++ b/ati_spi.c @@ -34,6 +34,7 @@ ATI_SPI_TYPE_EVERGREEN, ATI_SPI_TYPE_NORTHERN_ISLAND, ATI_SPI_TYPE_SOUTHERN_ISLAND, + ATI_SPI_TYPE_BONAIRE, }; struct ati_spi_pci_private { @@ -417,7 +418,123 @@ .master = &r600_spi_master, }; +/* + * Sea Island support. + */ +#define CI_MMIO_BAR 5 + +#define CI_SPI_TRANSFER_SIZE 0x100 + +struct ci_spi_data { + uint32_t empty; +}; + +/* + * Save for later restore. + */ +static int +ci_spi_save(struct flashrom_pci_device *device) +{ + struct ci_spi_data *data; + + msg_pdbg("%s();\n", __func__); + + if (device->private_data) { + msg_perr("%s: device->private_data is already assigned.\n", + __func__); + return -1; + } + + data = calloc(1, sizeof(struct ci_spi_data)); + + device->private_data = data; + + return 0; +} + +/* + * Restore saved registers, in the order of enable writes. + */ +static int +ci_spi_restore(struct flashrom_pci_device *device) +{ + struct ci_spi_data *data = device->private_data; + + msg_pdbg("%s();\n", __func__); + + if (!data) { + msg_perr("%s: device->private_data is not assigned.\n", + __func__); + return -1; + } + + free(data); + device->private_data = NULL; + + return 0; +} + +/* + * Enable SPI Access. + */ +static int +ci_spi_enable(struct flashrom_pci_device *device) +{ + msg_pdbg("%s();\n", __func__); + + return 0; +} + +/* + * + */ +static int +ci_spi_command(struct flashctx *flash, + unsigned int writecnt, unsigned int readcnt, + const unsigned char *writearr, unsigned char *readarr) +{ + const struct spi_master spi_master = flash->mst->spi; + struct flashrom_pci_device *device = + (struct flashrom_pci_device *) spi_master.data; + + msg_pdbg("%s(%p(%p), %d, %d, %p (0x%02X), %p);\n", __func__, flash, + device, writecnt, readcnt, writearr, writearr[0], readarr); + + if (!device) { + msg_perr("%s: no device specified!\n", __func__); + return -1; + } + + return 0; +} + +static struct spi_master ci_spi_master = { + .type = SPI_CONTROLLER_ATI, + .features = 0, + .max_data_read = CI_SPI_TRANSFER_SIZE, + .max_data_write = CI_SPI_TRANSFER_SIZE + 1, + .command = ci_spi_command, + .multicommand = default_spi_send_multicommand, + .read = default_spi_read, + .write_256 = default_spi_write_256, + .write_aai = default_spi_write_aai, + .data = NULL, /* make this our flashrom_pci_device... */ +}; + +/* + * Used by Bonaire + */ +static const struct ati_spi_pci_private bonaire_spi_pci_private = { + .io_bar = CI_MMIO_BAR, + .type = ATI_SPI_TYPE_BONAIRE, + .save = ci_spi_save, + .restore = ci_spi_restore, + .enable = ci_spi_enable, + .master = &ci_spi_master, +}; + const struct flashrom_pci_match ati_spi_pci_devices[] = { + {0x1002, 0x665F, OK, &bonaire_spi_pci_private}, {0x1002, 0x6704, NT, &northern_island_spi_pci_private}, {0x1002, 0x6707, NT, &northern_island_spi_pci_private}, {0x1002, 0x6718, NT, &northern_island_spi_pci_private}, -- To view, visit https://review.coreboot.org/29210 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I28c3fb8d15a7bc4fc044e04d04646011fb107e70 Gerrit-Change-Number: 29210 Gerrit-PatchSet: 1 Gerrit-Owner: Luc Verhaegen <libv(a)skynet.be>

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Change in flashrom[master]: add newer pci infrastructure
by Luc Verhaegen (Code Review) 22 Oct '18

22 Oct '18

Hello Paul Menzel, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/29078 to look at the new patch set (#2). Change subject: add newer pci infrastructure ...................................................................... add newer pci infrastructure This code does not negatively affect existing pci support and existing pci devices, it introduces parallel infrastructure which: - allows users to define a private which could be device specific. This avoids doing multiple lookups, which massively helps the ati spi driver which will support hundreds of devices. - uses linux sysfs pci infrastructure for enable/disable and mapping resources. This circumvents the security restrictions surrounding /dev/mem, but means that support for other operating systems still needs to be cobbled together. - looks up device names through libpci, keeping us from maintaining a separate names list. Change-Id: I59af37cba5cb78014e0714c654db2501151f605e Signed-off-by: Luc Verhaegen <libv(a)skynet.be> --- M pcidev.c M programmer.h 2 files changed, 165 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/78/29078/2 -- To view, visit https://review.coreboot.org/29078 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I59af37cba5cb78014e0714c654db2501151f605e Gerrit-Change-Number: 29078 Gerrit-PatchSet: 2 Gerrit-Owner: Luc Verhaegen <libv(a)skynet.be> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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flashrom-gerrit October 2018