October 2018 - flashrom-gerrit

Change in flashrom[master]: ati: add evergreen family
by Luc Verhaegen (Code Review) 13 Oct '18

13 Oct '18

Luc Verhaegen has uploaded this change for review. ( https://review.coreboot.org/29094 Change subject: ati: add evergreen family ...................................................................... ati: add evergreen family Change-Id: Id195810c8e7338f399db4198077eb256c3c4a136 Signed-off-by: Luc Verhaegen <libv(a)skynet.be> --- M ati_spi.c 1 file changed, 57 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/94/29094/1 diff --git a/ati_spi.c b/ati_spi.c index 56246eb..98b780a 100644 --- a/ati_spi.c +++ b/ati_spi.c @@ -33,6 +33,7 @@ #define ATI_SPI_TYPE_R600 1 #define ATI_SPI_TYPE_RV730 2 +#define ATI_SPI_TYPE_EVERGREEN 3 int type; int (*save) (struct flashrom_pci_device *device); @@ -201,7 +202,8 @@ mmio_mask(R600_MEDIUM_VID_LOWER_GPIO_CNTL, 0, 0x0400); mmio_mask(R600_LOW_VID_LOWER_GPIO_CNTL, 0, 0x0400); - mmio_mask(R600_LOWER_GPIO_ENABLE, 0x0400, 0x0400); + if (private->type != ATI_SPI_TYPE_EVERGREEN) + mmio_mask(R600_LOWER_GPIO_ENABLE, 0x0400, 0x0400); programmer_delay(1000); @@ -352,7 +354,61 @@ .master = &r600_spi_master, }; +/* + * Used by Cypress, Juniper, Redwood and Cedar. + */ +static const struct ati_spi_pci_private evergreen_spi_pci_private = { + .io_bar = 2, + .type = ATI_SPI_TYPE_EVERGREEN, + .save = r600_spi_save, + .restore = r600_spi_restore, + .enable = r600_spi_enable, + .master = &r600_spi_master, +}; + const struct flashrom_pci_match ati_spi_pci_devices[] = { + {0x1002, 0x6880, NT, &evergreen_spi_pci_private}, + {0x1002, 0x6888, NT, &evergreen_spi_pci_private}, + {0x1002, 0x6889, NT, &evergreen_spi_pci_private}, + {0x1002, 0x688A, NT, &evergreen_spi_pci_private}, + {0x1002, 0x688C, NT, &evergreen_spi_pci_private}, + {0x1002, 0x688D, NT, &evergreen_spi_pci_private}, + {0x1002, 0x6898, NT, &evergreen_spi_pci_private}, + {0x1002, 0x6899, NT, &evergreen_spi_pci_private}, + {0x1002, 0x689B, NT, &evergreen_spi_pci_private}, + {0x1002, 0x689C, NT, &evergreen_spi_pci_private}, + {0x1002, 0x689D, NT, &evergreen_spi_pci_private}, + {0x1002, 0x689E, NT, &evergreen_spi_pci_private}, + {0x1002, 0x68A0, NT, &evergreen_spi_pci_private}, + {0x1002, 0x68A1, NT, &evergreen_spi_pci_private}, + {0x1002, 0x68A8, NT, &evergreen_spi_pci_private}, + {0x1002, 0x68A9, NT, &evergreen_spi_pci_private}, + {0x1002, 0x68B8, NT, &evergreen_spi_pci_private}, + {0x1002, 0x68B9, NT, &evergreen_spi_pci_private}, + {0x1002, 0x68BA, NT, &evergreen_spi_pci_private}, + {0x1002, 0x68BE, NT, &evergreen_spi_pci_private}, + {0x1002, 0x68BF, NT, &evergreen_spi_pci_private}, + {0x1002, 0x68C0, NT, &evergreen_spi_pci_private}, + {0x1002, 0x68C1, NT, &evergreen_spi_pci_private}, + {0x1002, 0x68C7, NT, &evergreen_spi_pci_private}, + {0x1002, 0x68C8, NT, &evergreen_spi_pci_private}, + {0x1002, 0x68C9, NT, &evergreen_spi_pci_private}, + {0x1002, 0x68D8, NT, &evergreen_spi_pci_private}, + {0x1002, 0x68D9, NT, &evergreen_spi_pci_private}, + {0x1002, 0x68DA, NT, &evergreen_spi_pci_private}, + {0x1002, 0x68DE, NT, &evergreen_spi_pci_private}, + {0x1002, 0x68E0, NT, &evergreen_spi_pci_private}, + {0x1002, 0x68E1, NT, &evergreen_spi_pci_private}, + {0x1002, 0x68E4, NT, &evergreen_spi_pci_private}, + {0x1002, 0x68E5, NT, &evergreen_spi_pci_private}, + {0x1002, 0x68E8, NT, &evergreen_spi_pci_private}, + {0x1002, 0x68E9, NT, &evergreen_spi_pci_private}, + {0x1002, 0x68F1, NT, &evergreen_spi_pci_private}, + {0x1002, 0x68F2, NT, &evergreen_spi_pci_private}, + {0x1002, 0x68F8, NT, &evergreen_spi_pci_private}, + {0x1002, 0x68F9, NT, &evergreen_spi_pci_private}, + {0x1002, 0x68FA, NT, &evergreen_spi_pci_private}, + {0x1002, 0x68FE, NT, &evergreen_spi_pci_private}, {0x1002, 0x9400, NT, &r600_spi_pci_private}, {0x1002, 0x9401, NT, &r600_spi_pci_private}, {0x1002, 0x9402, NT, &r600_spi_pci_private}, -- To view, visit https://review.coreboot.org/29094 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Id195810c8e7338f399db4198077eb256c3c4a136 Gerrit-Change-Number: 29094 Gerrit-PatchSet: 1 Gerrit-Owner: Luc Verhaegen <libv(a)skynet.be>

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Change in flashrom[master]: ati: add rv730/rv740 support
by Luc Verhaegen (Code Review) 13 Oct '18

13 Oct '18

Luc Verhaegen has uploaded this change for review. ( https://review.coreboot.org/29093 Change subject: ati: add rv730/rv740 support ...................................................................... ati: add rv730/rv740 support For some reason, the pcie clk divider also gets set... TODO: verify on real hw whether this actually is needed. Change-Id: I0b6abc817c7ba0f12adc94c07bf81de118adffe5 Signed-off-by: Luc Verhaegen <libv(a)skynet.be> --- M ati_spi.c 1 file changed, 39 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/93/29093/1 diff --git a/ati_spi.c b/ati_spi.c index 87fe2d1..56246eb 100644 --- a/ati_spi.c +++ b/ati_spi.c @@ -31,6 +31,10 @@ struct ati_spi_pci_private { int io_bar; +#define ATI_SPI_TYPE_R600 1 +#define ATI_SPI_TYPE_RV730 2 + int type; + int (*save) (struct flashrom_pci_device *device); int (*restore) (struct flashrom_pci_device *device); int (*enable) (struct flashrom_pci_device *device); @@ -170,12 +174,17 @@ static int r600_spi_enable(struct flashrom_pci_device *device) { + const struct ati_spi_pci_private *private = device->private; int i; msg_pdbg("%s();\n", __func__); - /* software enable clock gating and set sck divider to 1 */ - mmio_mask(R600_ROM_CNTL, 0x10000002, 0xF0000002); + if (private->type == ATI_SPI_TYPE_RV730) + /* As below, but also set the (unused?) pcie clk divider */ + mmio_mask(R600_ROM_CNTL, 0x19000002, 0xFF000002); + else + /* software enable clock gating and set sck divider to 1 */ + mmio_mask(R600_ROM_CNTL, 0x10000002, 0xF0000002); /* set gpio7,8,9 low */ mmio_mask(R600_GPIOPAD_A, 0, 0x0700); @@ -324,6 +333,19 @@ */ static const struct ati_spi_pci_private r600_spi_pci_private = { .io_bar = 2, + .type = ATI_SPI_TYPE_R600, + .save = r600_spi_save, + .restore = r600_spi_restore, + .enable = r600_spi_enable, + .master = &r600_spi_master, +}; + +/* + * Used by RV730/RV740. + */ +static const struct ati_spi_pci_private rv730_spi_pci_private = { + .io_bar = 2, + .type = ATI_SPI_TYPE_RV730, .save = r600_spi_save, .restore = r600_spi_restore, .enable = r600_spi_enable, @@ -356,6 +378,21 @@ {0x1002, 0x9460, NT, &r600_spi_pci_private}, {0x1002, 0x9462, NT, &r600_spi_pci_private}, {0x1002, 0x946A, NT, &r600_spi_pci_private}, + {0x1002, 0x9480, NT, &rv730_spi_pci_private}, + {0x1002, 0x9488, NT, &rv730_spi_pci_private}, + {0x1002, 0x9489, NT, &rv730_spi_pci_private}, + {0x1002, 0x9490, NT, &rv730_spi_pci_private}, + {0x1002, 0x9491, NT, &rv730_spi_pci_private}, + {0x1002, 0x9495, NT, &rv730_spi_pci_private}, + {0x1002, 0x9498, NT, &rv730_spi_pci_private}, + {0x1002, 0x949C, NT, &rv730_spi_pci_private}, + {0x1002, 0x949E, NT, &rv730_spi_pci_private}, + {0x1002, 0x949F, NT, &rv730_spi_pci_private}, + {0x1002, 0x94A0, NT, &rv730_spi_pci_private}, + {0x1002, 0x94A1, NT, &rv730_spi_pci_private}, + {0x1002, 0x94A3, NT, &rv730_spi_pci_private}, + {0x1002, 0x94B3, NT, &rv730_spi_pci_private}, + {0x1002, 0x94B4, NT, &rv730_spi_pci_private}, {0x1002, 0x94C1, NT, &r600_spi_pci_private}, {0x1002, 0x94C3, NT, &r600_spi_pci_private}, {0x1002, 0x94C4, NT, &r600_spi_pci_private}, -- To view, visit https://review.coreboot.org/29093 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I0b6abc817c7ba0f12adc94c07bf81de118adffe5 Gerrit-Change-Number: 29093 Gerrit-PatchSet: 1 Gerrit-Owner: Luc Verhaegen <libv(a)skynet.be>

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Change in flashrom[master]: ati: add rv710/rv770/rv790 ids
by Luc Verhaegen (Code Review) 13 Oct '18

13 Oct '18

Luc Verhaegen has uploaded this change for review. ( https://review.coreboot.org/29092 Change subject: ati: add rv710/rv770/rv790 ids ...................................................................... ati: add rv710/rv770/rv790 ids These fully match rx6xx. Change-Id: Ia3bad57e00a29741b67fb1e8141c1c9cce887331 Signed-off-by: Luc Verhaegen <libv(a)skynet.be> --- M ati_spi.c 1 file changed, 28 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/92/29092/1 diff --git a/ati_spi.c b/ati_spi.c index cc6fc55..87fe2d1 100644 --- a/ati_spi.c +++ b/ati_spi.c @@ -318,6 +318,10 @@ .data = NULL, /* make this our flashrom_pci_device... */ }; +/* + * Used by all Rx6xx and RV710/RV770/RV710. RV730/RV740 use a slightly + * different enable. + */ static const struct ati_spi_pci_private r600_spi_pci_private = { .io_bar = 2, .save = r600_spi_save, @@ -335,6 +339,23 @@ {0x1002, 0x940A, NT, &r600_spi_pci_private}, {0x1002, 0x940B, NT, &r600_spi_pci_private}, {0x1002, 0x940F, NT, &r600_spi_pci_private}, + {0x1002, 0x9440, NT, &r600_spi_pci_private}, + {0x1002, 0x9441, NT, &r600_spi_pci_private}, + {0x1002, 0x9442, NT, &r600_spi_pci_private}, + {0x1002, 0x9443, NT, &r600_spi_pci_private}, + {0x1002, 0x9444, NT, &r600_spi_pci_private}, + {0x1002, 0x9446, NT, &r600_spi_pci_private}, + {0x1002, 0x944A, NT, &r600_spi_pci_private}, + {0x1002, 0x944B, NT, &r600_spi_pci_private}, + {0x1002, 0x944C, NT, &r600_spi_pci_private}, + {0x1002, 0x944e, NT, &r600_spi_pci_private}, + {0x1002, 0x9450, NT, &r600_spi_pci_private}, + {0x1002, 0x9452, NT, &r600_spi_pci_private}, + {0x1002, 0x9456, NT, &r600_spi_pci_private}, + {0x1002, 0x945A, NT, &r600_spi_pci_private}, + {0x1002, 0x9460, NT, &r600_spi_pci_private}, + {0x1002, 0x9462, NT, &r600_spi_pci_private}, + {0x1002, 0x946A, NT, &r600_spi_pci_private}, {0x1002, 0x94C1, NT, &r600_spi_pci_private}, {0x1002, 0x94C3, NT, &r600_spi_pci_private}, {0x1002, 0x94C4, NT, &r600_spi_pci_private}, @@ -358,6 +379,13 @@ {0x1002, 0x9513, NT, &r600_spi_pci_private}, {0x1002, 0x9515, NT, &r600_spi_pci_private}, {0x1002, 0x9519, NT, &r600_spi_pci_private}, + {0x1002, 0x9540, NT, &r600_spi_pci_private}, + {0x1002, 0x954F, NT, &r600_spi_pci_private}, + {0x1002, 0x9552, NT, &r600_spi_pci_private}, + {0x1002, 0x9553, NT, &r600_spi_pci_private}, + {0x1002, 0x9555, NT, &r600_spi_pci_private}, + {0x1002, 0x9557, NT, &r600_spi_pci_private}, + {0x1002, 0x955F, NT, &r600_spi_pci_private}, {0x1002, 0x9580, NT, &r600_spi_pci_private}, {0x1002, 0x9581, NT, &r600_spi_pci_private}, {0x1002, 0x9583, NT, &r600_spi_pci_private}, -- To view, visit https://review.coreboot.org/29092 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ia3bad57e00a29741b67fb1e8141c1c9cce887331 Gerrit-Change-Number: 29092 Gerrit-PatchSet: 1 Gerrit-Owner: Luc Verhaegen <libv(a)skynet.be>

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Change in flashrom[master]: ati: add all rx6xx ids
by Luc Verhaegen (Code Review) 13 Oct '18

13 Oct '18

Luc Verhaegen has uploaded this change for review. ( https://review.coreboot.org/29091 Change subject: ati: add all rx6xx ids ...................................................................... ati: add all rx6xx ids Change-Id: Ia1db93efcc4e10e6f651564ca194a146c668d68b Signed-off-by: Luc Verhaegen <libv(a)skynet.be> --- M ati_spi.c 1 file changed, 59 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/91/29091/1 diff --git a/ati_spi.c b/ati_spi.c index 8f09618..cc6fc55 100644 --- a/ati_spi.c +++ b/ati_spi.c @@ -327,7 +327,65 @@ }; const struct flashrom_pci_match ati_spi_pci_devices[] = { - {0x1002, 0x958d, NT, &r600_spi_pci_private}, + {0x1002, 0x9400, NT, &r600_spi_pci_private}, + {0x1002, 0x9401, NT, &r600_spi_pci_private}, + {0x1002, 0x9402, NT, &r600_spi_pci_private}, + {0x1002, 0x9403, NT, &r600_spi_pci_private}, + {0x1002, 0x9405, NT, &r600_spi_pci_private}, + {0x1002, 0x940A, NT, &r600_spi_pci_private}, + {0x1002, 0x940B, NT, &r600_spi_pci_private}, + {0x1002, 0x940F, NT, &r600_spi_pci_private}, + {0x1002, 0x94C1, NT, &r600_spi_pci_private}, + {0x1002, 0x94C3, NT, &r600_spi_pci_private}, + {0x1002, 0x94C4, NT, &r600_spi_pci_private}, + {0x1002, 0x94C5, NT, &r600_spi_pci_private}, + {0x1002, 0x94C6, NT, &r600_spi_pci_private}, + {0x1002, 0x94C7, NT, &r600_spi_pci_private}, + {0x1002, 0x94C8, NT, &r600_spi_pci_private}, + {0x1002, 0x94C9, NT, &r600_spi_pci_private}, + {0x1002, 0x94CB, NT, &r600_spi_pci_private}, + {0x1002, 0x94CC, NT, &r600_spi_pci_private}, + {0x1002, 0x9500, NT, &r600_spi_pci_private}, + {0x1002, 0x9501, NT, &r600_spi_pci_private}, + {0x1002, 0x9504, NT, &r600_spi_pci_private}, + {0x1002, 0x9505, NT, &r600_spi_pci_private}, + {0x1002, 0x9506, NT, &r600_spi_pci_private}, + {0x1002, 0x9507, NT, &r600_spi_pci_private}, + {0x1002, 0x9508, NT, &r600_spi_pci_private}, + {0x1002, 0x9509, NT, &r600_spi_pci_private}, + {0x1002, 0x950F, NT, &r600_spi_pci_private}, + {0x1002, 0x9511, OK, &r600_spi_pci_private}, + {0x1002, 0x9513, NT, &r600_spi_pci_private}, + {0x1002, 0x9515, NT, &r600_spi_pci_private}, + {0x1002, 0x9519, NT, &r600_spi_pci_private}, + {0x1002, 0x9580, NT, &r600_spi_pci_private}, + {0x1002, 0x9581, NT, &r600_spi_pci_private}, + {0x1002, 0x9583, NT, &r600_spi_pci_private}, + {0x1002, 0x9586, NT, &r600_spi_pci_private}, + {0x1002, 0x9587, NT, &r600_spi_pci_private}, + {0x1002, 0x9588, NT, &r600_spi_pci_private}, + {0x1002, 0x9589, NT, &r600_spi_pci_private}, + {0x1002, 0x958A, NT, &r600_spi_pci_private}, + {0x1002, 0x958B, NT, &r600_spi_pci_private}, + {0x1002, 0x958C, NT, &r600_spi_pci_private}, + {0x1002, 0x958D, OK, &r600_spi_pci_private}, + {0x1002, 0x958E, NT, &r600_spi_pci_private}, + {0x1002, 0x9591, NT, &r600_spi_pci_private}, + {0x1002, 0x9593, NT, &r600_spi_pci_private}, + {0x1002, 0x9595, NT, &r600_spi_pci_private}, + {0x1002, 0x9596, NT, &r600_spi_pci_private}, + {0x1002, 0x9597, NT, &r600_spi_pci_private}, + {0x1002, 0x9598, NT, &r600_spi_pci_private}, + {0x1002, 0x9599, NT, &r600_spi_pci_private}, + {0x1002, 0x95C0, NT, &r600_spi_pci_private}, + {0x1002, 0x95C2, NT, &r600_spi_pci_private}, + {0x1002, 0x95C4, NT, &r600_spi_pci_private}, + {0x1002, 0x95C5, NT, &r600_spi_pci_private}, + {0x1002, 0x95C6, NT, &r600_spi_pci_private}, + {0x1002, 0x95C9, NT, &r600_spi_pci_private}, + {0x1002, 0x95CC, NT, &r600_spi_pci_private}, + {0x1002, 0x95CD, NT, &r600_spi_pci_private}, + {0x1002, 0x95CF, NT, &r600_spi_pci_private}, {}, }; -- To view, visit https://review.coreboot.org/29091 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ia1db93efcc4e10e6f651564ca194a146c668d68b Gerrit-Change-Number: 29091 Gerrit-PatchSet: 1 Gerrit-Owner: Luc Verhaegen <libv(a)skynet.be>

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Change in flashrom[master]: ati: add r600_spi_command and r600_spi_master
by Luc Verhaegen (Code Review) 13 Oct '18

13 Oct '18

Luc Verhaegen has uploaded this change for review. ( https://review.coreboot.org/29090 Change subject: ati: add r600_spi_command and r600_spi_master ...................................................................... ati: add r600_spi_command and r600_spi_master Change-Id: I3d0bc682898f8eadadfe1f6db0d1383eb7639054 Signed-off-by: Luc Verhaegen <libv(a)skynet.be> --- M ati_spi.c M programmer.h 2 files changed, 117 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/90/29090/1 diff --git a/ati_spi.c b/ati_spi.c index 7d1e909..8f09618 100644 --- a/ati_spi.c +++ b/ati_spi.c @@ -24,6 +24,7 @@ /* improve readability */ #define mmio_read(reg) flashrom_pci_mmio_long_read(device, (reg)) +#define mmio_read_byte(reg) flashrom_pci_mmio_byte_read(device, (reg)) #define mmio_write(reg, val) flashrom_pci_mmio_long_write(device, (reg), (val)) #define mmio_mask(reg, val, mask) flashrom_pci_mmio_long_mask(device, (reg), (val), (mask)) @@ -33,6 +34,8 @@ int (*save) (struct flashrom_pci_device *device); int (*restore) (struct flashrom_pci_device *device); int (*enable) (struct flashrom_pci_device *device); + + struct spi_master *master; }; #define R600_GENERAL_PWRMGT 0x0618 @@ -45,7 +48,13 @@ #define R600_ROM_CNTL 0x1600 #define R600_ROM_CLK_CTRL 0x1604 +#define R600_ROM_SW_CNTL 0x1618 #define R600_ROM_SW_STATUS 0x161C +#define R600_ROM_SW_COMMAND 0x1620 +#define R600_ROM_SW_DATA_0x00 0x1624 +/* ... */ +#define R600_ROM_SW_DATA_0xFC 0x1720 +#define R600_ROM_SW_DATA(off) (R600_ROM_SW_DATA_0x00 + (off)) #define R600_GPIOPAD_MASK 0x1798 #define R600_GPIOPAD_A 0x179C @@ -53,6 +62,8 @@ #define R600_ROM_SW_STATUS_LOOP_COUNT 1000 +#define R600_SPI_TRANSFER_SIZE 0x100 + struct r600_spi_data { uint32_t reg_general_pwrmgt; uint32_t reg_lower_gpio_enable; @@ -209,11 +220,110 @@ return 0; } +/* + * + */ +static int +r600_spi_command(struct flashctx *flash, + unsigned int writecnt, unsigned int readcnt, + const unsigned char *writearr, unsigned char *readarr) +{ + const struct spi_master spi_master = flash->mst->spi; + struct flashrom_pci_device *device = + (struct flashrom_pci_device *) spi_master.data; + uint32_t command, control; + int i, command_size; + + msg_pdbg("%s(%p(%p), %d, %d, %p (0x%02X), %p);\n", __func__, flash, + device, writecnt, readcnt, writearr, writearr[0], readarr); + + if (!device) { + msg_perr("%s: no device specified!\n", __func__); + return -1; + } + + command = *((uint32_t *) writearr); + if (writecnt < 4) { + uint32_t mask = 1 << (8 * writecnt); + + command &= (mask - 1); + command_size = writecnt; + } else + command_size = 4; + + mmio_write(R600_ROM_SW_COMMAND, command); + + /* + * For some reason, we have an endianness difference between reading + * and writing. Also, ati hw only does 32bit register write accesses. + * If you write 8bits, the upper bytes will be nulled. Reading is fine. + * Furthermore, due to flashrom infrastructure, we need to skip the + * command in the writearr. + */ + for (i = 4; i < writecnt; i += 4) { + uint32_t value = 0; + int remainder = writecnt - i; + + if (remainder > 4) + remainder = 4; + + if (remainder > 0) + value |= writearr[i + 0] << 24; + if (remainder > 1) + value |= writearr[i + 1] << 16; + if (remainder > 2) + value |= writearr[i + 2] << 8; + if (remainder > 3) + value |= writearr[i + 3] << 0; + + mmio_write(R600_ROM_SW_DATA(i - 4), value); + } + + control = (command_size - 1) << 0x10; + if (readcnt) + control |= 0x40000 | readcnt; + else if (writecnt > 4) + control |= writecnt - 4; + mmio_write(R600_ROM_SW_CNTL, control); + + for (i = 0; i < R600_ROM_SW_STATUS_LOOP_COUNT; i++) { + if (mmio_read(R600_ROM_SW_STATUS)) + break; + programmer_delay(1000); + } + + if (i == R600_ROM_SW_STATUS_LOOP_COUNT) { + msg_perr("%s: still waiting for R600_ROM_SW_STATUS\n", + __func__); + return -1; + } + mmio_write(R600_ROM_SW_STATUS, 0); + + for (i = 0; i < readcnt; i++) + readarr[i] = mmio_read_byte(R600_ROM_SW_DATA(i)); + + return 0; +} + +static struct spi_master r600_spi_master = { + .type = SPI_CONTROLLER_ATI, + .features = 0, + .max_data_read = R600_SPI_TRANSFER_SIZE, + .max_data_write = R600_SPI_TRANSFER_SIZE + 1, + .command = r600_spi_command, + .multicommand = default_spi_send_multicommand, + .read = default_spi_read, + .write_256 = default_spi_write_256, + .write_aai = default_spi_write_aai, + .data = NULL, /* make this our flashrom_pci_device... */ +}; + static const struct ati_spi_pci_private r600_spi_pci_private = { .io_bar = 2, .save = r600_spi_save, .restore = r600_spi_restore, .enable = r600_spi_enable, + .master = &r600_spi_master, }; const struct flashrom_pci_match ati_spi_pci_devices[] = { @@ -259,5 +369,9 @@ if (ret) return ret; + private->master->data = device; + if (register_spi_master(private->master)) + return 1; + return 0; } diff --git a/programmer.h b/programmer.h index 3398427..73b4ec9 100644 --- a/programmer.h +++ b/programmer.h @@ -659,6 +659,9 @@ #if CONFIG_DIGILENT_SPI == 1 SPI_CONTROLLER_DIGILENT_SPI, #endif +#if CONFIG_ATI_SPI == 1 + SPI_CONTROLLER_ATI, +#endif }; #define MAX_DATA_UNSPECIFIED 0 -- To view, visit https://review.coreboot.org/29090 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I3d0bc682898f8eadadfe1f6db0d1383eb7639054 Gerrit-Change-Number: 29090 Gerrit-PatchSet: 1 Gerrit-Owner: Luc Verhaegen <libv(a)skynet.be>

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Change in flashrom[master]: ati: add further spi initialization
by Luc Verhaegen (Code Review) 13 Oct '18

13 Oct '18

Luc Verhaegen has uploaded this change for review. ( https://review.coreboot.org/29089 Change subject: ati: add further spi initialization ...................................................................... ati: add further spi initialization Change-Id: I14fb218d001c1e12888225675bd8fdd46e7d8fae Signed-off-by: Luc Verhaegen <libv(a)skynet.be> --- M ati_spi.c 1 file changed, 33 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/89/29089/1 diff --git a/ati_spi.c b/ati_spi.c index ee5041d..7d1e909 100644 --- a/ati_spi.c +++ b/ati_spi.c @@ -44,11 +44,15 @@ #define R600_LOW_VID_LOWER_GPIO_CNTL 0x0724 #define R600_ROM_CNTL 0x1600 +#define R600_ROM_CLK_CTRL 0x1604 +#define R600_ROM_SW_STATUS 0x161C #define R600_GPIOPAD_MASK 0x1798 #define R600_GPIOPAD_A 0x179C #define R600_GPIOPAD_EN 0x17A0 +#define R600_ROM_SW_STATUS_LOOP_COUNT 1000 + struct r600_spi_data { uint32_t reg_general_pwrmgt; uint32_t reg_lower_gpio_enable; @@ -58,6 +62,7 @@ uint32_t reg_low_vid_lower_gpio_cntl; uint32_t reg_rom_cntl; + uint32_t reg_rom_clk_ctrl; uint32_t reg_gpiopad_mask; uint32_t reg_gpiopad_a; uint32_t reg_gpiopad_en; @@ -94,6 +99,7 @@ mmio_read(R600_LOW_VID_LOWER_GPIO_CNTL); data->reg_rom_cntl = mmio_read(R600_ROM_CNTL); + data->reg_rom_clk_ctrl = mmio_read(R600_ROM_CLK_CTRL); data->reg_gpiopad_mask = mmio_read(R600_GPIOPAD_MASK); data->reg_gpiopad_a = mmio_read(R600_GPIOPAD_A); @@ -139,6 +145,8 @@ mmio_write(R600_LOWER_GPIO_ENABLE, data->reg_lower_gpio_enable); + mmio_write(R600_ROM_CLK_CTRL, data->reg_rom_clk_ctrl); + free(data); device->private_data = NULL; @@ -151,6 +159,8 @@ static int r600_spi_enable(struct flashrom_pci_device *device) { + int i; + msg_pdbg("%s();\n", __func__); /* software enable clock gating and set sck divider to 1 */ @@ -173,6 +183,29 @@ mmio_mask(R600_LOWER_GPIO_ENABLE, 0x0400, 0x0400); + programmer_delay(1000); + + mmio_mask(R600_GPIOPAD_MASK, 0, 0x700); + mmio_mask(R600_GPIOPAD_EN, 0, 0x700); + mmio_mask(R600_GPIOPAD_A, 0, 0x00080000); + + mmio_mask(R600_ROM_CLK_CTRL, 0x04000000, 0x0C000000); + + if (mmio_read(R600_ROM_SW_STATUS)) { + for (i = 0; i < R600_ROM_SW_STATUS_LOOP_COUNT; i++) { + mmio_write(R600_ROM_SW_STATUS, 0); + programmer_delay(1000); + if (!mmio_read(R600_ROM_SW_STATUS)) + break; + } + + if (i == R600_ROM_SW_STATUS_LOOP_COUNT) { + msg_perr("%s: failed to clear R600_ROM_SW_STATUS\n", + __func__); + return -1; + } + } + return 0; } -- To view, visit https://review.coreboot.org/29089 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I14fb218d001c1e12888225675bd8fdd46e7d8fae Gerrit-Change-Number: 29089 Gerrit-PatchSet: 1 Gerrit-Owner: Luc Verhaegen <libv(a)skynet.be>

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Change in flashrom[master]: ati: add spi access enable
by Luc Verhaegen (Code Review) 13 Oct '18

13 Oct '18

Luc Verhaegen has uploaded this change for review. ( https://review.coreboot.org/29088 Change subject: ati: add spi access enable ...................................................................... ati: add spi access enable Change-Id: Ibd68fb11237a39857ba6a4bb69e89589afd8c198 Signed-off-by: Luc Verhaegen <libv(a)skynet.be> --- M ati_spi.c 1 file changed, 37 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/88/29088/1 diff --git a/ati_spi.c b/ati_spi.c index 97c056a..ee5041d 100644 --- a/ati_spi.c +++ b/ati_spi.c @@ -32,6 +32,7 @@ int (*save) (struct flashrom_pci_device *device); int (*restore) (struct flashrom_pci_device *device); + int (*enable) (struct flashrom_pci_device *device); }; #define R600_GENERAL_PWRMGT 0x0618 @@ -144,10 +145,42 @@ return 0; } +/* + * Enable SPI Access. + */ +static int +r600_spi_enable(struct flashrom_pci_device *device) +{ + msg_pdbg("%s();\n", __func__); + + /* software enable clock gating and set sck divider to 1 */ + mmio_mask(R600_ROM_CNTL, 0x10000002, 0xF0000002); + + /* set gpio7,8,9 low */ + mmio_mask(R600_GPIOPAD_A, 0, 0x0700); + /* gpio7 is input, gpio8/9 are output */ + mmio_mask(R600_GPIOPAD_EN, 0x0600, 0x0700); + /* only allow software control on gpio7,8,9 */ + mmio_mask(R600_GPIOPAD_MASK, 0x0700, 0x0700); + + /* disable open drain pads */ + mmio_mask(R600_GENERAL_PWRMGT, 0, 0x0800); + + mmio_mask(R600_CTXSW_VID_LOWER_GPIO_CNTL, 0, 0x0400); + mmio_mask(R600_HIGH_VID_LOWER_GPIO_CNTL, 0, 0x0400); + mmio_mask(R600_MEDIUM_VID_LOWER_GPIO_CNTL, 0, 0x0400); + mmio_mask(R600_LOW_VID_LOWER_GPIO_CNTL, 0, 0x0400); + + mmio_mask(R600_LOWER_GPIO_ENABLE, 0x0400, 0x0400); + + return 0; +} + static const struct ati_spi_pci_private r600_spi_pci_private = { .io_bar = 2, .save = r600_spi_save, .restore = r600_spi_restore, + .enable = r600_spi_enable, }; const struct flashrom_pci_match ati_spi_pci_devices[] = { @@ -189,5 +222,9 @@ if (ret) return ret; + ret = private->enable(device); + if (ret) + return ret; + return 0; } -- To view, visit https://review.coreboot.org/29088 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ibd68fb11237a39857ba6a4bb69e89589afd8c198 Gerrit-Change-Number: 29088 Gerrit-PatchSet: 1 Gerrit-Owner: Luc Verhaegen <libv(a)skynet.be>

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Change in flashrom[master]: ati: add save/restore
by Luc Verhaegen (Code Review) 13 Oct '18

13 Oct '18

Luc Verhaegen has uploaded this change for review. ( https://review.coreboot.org/29087 Change subject: ati: add save/restore ...................................................................... ati: add save/restore Change-Id: I392c3ecc07facdeb2454ec1702bd277f7ebbf50d Signed-off-by: Luc Verhaegen <libv(a)skynet.be> --- M ati_spi.c 1 file changed, 141 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/87/29087/1 diff --git a/ati_spi.c b/ati_spi.c index 2db0681..97c056a 100644 --- a/ati_spi.c +++ b/ati_spi.c @@ -17,15 +17,137 @@ * This adds support for the ATI/AMD Radeon SPI interfaces. */ +#include <stdlib.h> + #include "programmer.h" #include "spi.h" +/* improve readability */ +#define mmio_read(reg) flashrom_pci_mmio_long_read(device, (reg)) +#define mmio_write(reg, val) flashrom_pci_mmio_long_write(device, (reg), (val)) +#define mmio_mask(reg, val, mask) flashrom_pci_mmio_long_mask(device, (reg), (val), (mask)) + struct ati_spi_pci_private { int io_bar; + + int (*save) (struct flashrom_pci_device *device); + int (*restore) (struct flashrom_pci_device *device); }; +#define R600_GENERAL_PWRMGT 0x0618 + +#define R600_LOWER_GPIO_ENABLE 0x0710 +#define R600_CTXSW_VID_LOWER_GPIO_CNTL 0x0718 +#define R600_HIGH_VID_LOWER_GPIO_CNTL 0x071c +#define R600_MEDIUM_VID_LOWER_GPIO_CNTL 0x0720 +#define R600_LOW_VID_LOWER_GPIO_CNTL 0x0724 + +#define R600_ROM_CNTL 0x1600 + +#define R600_GPIOPAD_MASK 0x1798 +#define R600_GPIOPAD_A 0x179C +#define R600_GPIOPAD_EN 0x17A0 + +struct r600_spi_data { + uint32_t reg_general_pwrmgt; + uint32_t reg_lower_gpio_enable; + uint32_t reg_ctxsw_vid_lower_gpio_cntl; + uint32_t reg_high_vid_lower_gpio_cntl; + uint32_t reg_medium_vid_lower_gpio_cntl; + uint32_t reg_low_vid_lower_gpio_cntl; + + uint32_t reg_rom_cntl; + uint32_t reg_gpiopad_mask; + uint32_t reg_gpiopad_a; + uint32_t reg_gpiopad_en; +}; + +/* + * Save for later restore. + */ +static int +r600_spi_save(struct flashrom_pci_device *device) +{ + struct r600_spi_data *data; + + msg_pdbg("%s();\n", __func__); + + if (device->private_data) { + msg_perr("%s: device->private_data is already assigned.\n", + __func__); + return -1; + } + + data = calloc(1, sizeof(struct r600_spi_data)); + + data->reg_general_pwrmgt = mmio_read(R600_GENERAL_PWRMGT); + + data->reg_lower_gpio_enable = mmio_read(R600_LOWER_GPIO_ENABLE); + data->reg_ctxsw_vid_lower_gpio_cntl = + mmio_read(R600_CTXSW_VID_LOWER_GPIO_CNTL); + data->reg_high_vid_lower_gpio_cntl = + mmio_read(R600_HIGH_VID_LOWER_GPIO_CNTL); + data->reg_medium_vid_lower_gpio_cntl = + mmio_read(R600_MEDIUM_VID_LOWER_GPIO_CNTL); + data->reg_low_vid_lower_gpio_cntl = + mmio_read(R600_LOW_VID_LOWER_GPIO_CNTL); + + data->reg_rom_cntl = mmio_read(R600_ROM_CNTL); + + data->reg_gpiopad_mask = mmio_read(R600_GPIOPAD_MASK); + data->reg_gpiopad_a = mmio_read(R600_GPIOPAD_A); + data->reg_gpiopad_en = mmio_read(R600_GPIOPAD_EN); + + device->private_data = data; + + return 0; +} + +/* + * Restore saved registers, in the order of enable writes. + */ +static int +r600_spi_restore(struct flashrom_pci_device *device) +{ + struct r600_spi_data *data = device->private_data; + + msg_pdbg("%s();\n", __func__); + + if (!data) { + msg_perr("%s: device->private_data is not assigned.\n", + __func__); + return -1; + } + + mmio_write(R600_ROM_CNTL, data->reg_rom_cntl); + + mmio_write(R600_GPIOPAD_A, data->reg_gpiopad_a); + mmio_write(R600_GPIOPAD_EN, data->reg_gpiopad_en); + mmio_write(R600_GPIOPAD_MASK, data->reg_gpiopad_mask); + + mmio_write(R600_GENERAL_PWRMGT, data->reg_general_pwrmgt); + + mmio_write(R600_CTXSW_VID_LOWER_GPIO_CNTL, + data->reg_ctxsw_vid_lower_gpio_cntl); + mmio_write(R600_HIGH_VID_LOWER_GPIO_CNTL, + data->reg_high_vid_lower_gpio_cntl); + mmio_write(R600_MEDIUM_VID_LOWER_GPIO_CNTL, + data->reg_medium_vid_lower_gpio_cntl); + mmio_write(R600_LOW_VID_LOWER_GPIO_CNTL, + data->reg_low_vid_lower_gpio_cntl); + + mmio_write(R600_LOWER_GPIO_ENABLE, data->reg_lower_gpio_enable); + + free(data); + device->private_data = NULL; + + return 0; +} + static const struct ati_spi_pci_private r600_spi_pci_private = { .io_bar = 2, + .save = r600_spi_save, + .restore = r600_spi_restore, }; const struct flashrom_pci_match ati_spi_pci_devices[] = { @@ -33,11 +155,24 @@ {}, }; +/* + * + */ +static int +ati_spi_shutdown(void *data) +{ + struct flashrom_pci_device *device = data; + const struct ati_spi_pci_private *private = device->private; + + return private->restore(device); +} + int ati_spi_init(void) { struct flashrom_pci_device *device; const struct ati_spi_pci_private *private; + int ret; device = flashrom_pci_init(ati_spi_pci_devices); if (!device) @@ -48,5 +183,11 @@ if (flashrom_pci_mmio_map(device, private->io_bar)) return 1; + register_shutdown(ati_spi_shutdown, device); + + ret = private->save(device); + if (ret) + return ret; + return 0; } -- To view, visit https://review.coreboot.org/29087 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I392c3ecc07facdeb2454ec1702bd277f7ebbf50d Gerrit-Change-Number: 29087 Gerrit-PatchSet: 1 Gerrit-Owner: Luc Verhaegen <libv(a)skynet.be>

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Change in flashrom[master]: ati: map mmio
by Luc Verhaegen (Code Review) 13 Oct '18

13 Oct '18

Luc Verhaegen has uploaded this change for review. ( https://review.coreboot.org/29086 Change subject: ati: map mmio ...................................................................... ati: map mmio Change-Id: Ifaf964aa7ff12e2397aaec3c9aaae07a7ac9309a Signed-off-by: Luc Verhaegen <libv(a)skynet.be> --- M ati_spi.c 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/86/29086/1 diff --git a/ati_spi.c b/ati_spi.c index ba672f7..2db0681 100644 --- a/ati_spi.c +++ b/ati_spi.c @@ -37,10 +37,16 @@ ati_spi_init(void) { struct flashrom_pci_device *device; + const struct ati_spi_pci_private *private; device = flashrom_pci_init(ati_spi_pci_devices); if (!device) return 1; + private = device->private; + + if (flashrom_pci_mmio_map(device, private->io_bar)) + return 1; + return 0; } -- To view, visit https://review.coreboot.org/29086 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ifaf964aa7ff12e2397aaec3c9aaae07a7ac9309a Gerrit-Change-Number: 29086 Gerrit-PatchSet: 1 Gerrit-Owner: Luc Verhaegen <libv(a)skynet.be>

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Change in flashrom[master]: ati: initial commit
by Luc Verhaegen (Code Review) 13 Oct '18

13 Oct '18

Luc Verhaegen has uploaded this change for review. ( https://review.coreboot.org/29085 Change subject: ati: initial commit ...................................................................... ati: initial commit Change-Id: Ia5f755ae7a0723372933216516625bc156b1f4bc Signed-off-by: Luc Verhaegen <libv(a)skynet.be> --- M Makefile A ati_spi.c M flashrom.c M programmer.h 4 files changed, 77 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/85/29085/1 diff --git a/Makefile b/Makefile index b13cf7e..1e924af 100644 --- a/Makefile +++ b/Makefile @@ -656,6 +656,9 @@ # Digilent Development board JTAG CONFIG_DIGILENT_SPI ?= yes +# ATI Radeon SPI +CONFIG_ATI_SPI ?= yes + # Disable wiki printing by default. It is only useful if you have wiki access. CONFIG_PRINT_WIKI ?= no @@ -703,6 +706,7 @@ override CONFIG_NICINTEL_EEPROM = no override CONFIG_OGP_SPI = no override CONFIG_SATAMV = no +override CONFIG_ATI_SPI = no endif # Bitbanging SPI infrastructure, default off unless needed. @@ -964,6 +968,12 @@ NEED_LIBUSB1 += CONFIG_DIGILENT_SPI endif +ifeq ($(CONFIG_ATI_SPI), yes) +FEATURE_CFLAGS += -D'CONFIG_ATI_SPI=1' +PROGRAMMER_OBJS += ati_spi.o +NEED_LIBPCI += CONFIG_ATI_SPI +endif + ifneq ($(NEED_SERIAL), ) LIB_OBJS += serial.o custom_baud.o endif diff --git a/ati_spi.c b/ati_spi.c new file mode 100644 index 0000000..ba672f7 --- /dev/null +++ b/ati_spi.c @@ -0,0 +1,46 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2018 Luc Verhaegen <libv(a)skynet.be> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * This adds support for the ATI/AMD Radeon SPI interfaces. + */ + +#include "programmer.h" +#include "spi.h" + +struct ati_spi_pci_private { + int io_bar; +}; + +static const struct ati_spi_pci_private r600_spi_pci_private = { + .io_bar = 2, +}; + +const struct flashrom_pci_match ati_spi_pci_devices[] = { + {0x1002, 0x958d, NT, &r600_spi_pci_private}, + {}, +}; + +int +ati_spi_init(void) +{ + struct flashrom_pci_device *device; + + device = flashrom_pci_init(ati_spi_pci_devices); + if (!device) + return 1; + + return 0; +} diff --git a/flashrom.c b/flashrom.c index 3b3e9bb..30c605d 100644 --- a/flashrom.c +++ b/flashrom.c @@ -437,6 +437,18 @@ }, #endif +#if CONFIG_ATI_SPI == 1 + { + .name = "ati_spi", + .type = PCI2, + .devs.pci_match = ati_spi_pci_devices, + .init = ati_spi_init, + .map_flash_region = fallback_map, + .unmap_flash_region = fallback_unmap, + .delay = internal_delay, + }, +#endif + {0}, /* This entry corresponds to PROGRAMMER_INVALID. */ }; diff --git a/programmer.h b/programmer.h index a5a1360..3398427 100644 --- a/programmer.h +++ b/programmer.h @@ -118,6 +118,9 @@ #if CONFIG_DIGILENT_SPI == 1 PROGRAMMER_DIGILENT_SPI, #endif +#if CONFIG_ATI_SPI == 1 + PROGRAMMER_ATI_SPI, +#endif PROGRAMMER_INVALID /* This must always be the last entry. */ }; @@ -582,6 +585,12 @@ extern const struct dev_entry devs_digilent_spi[]; #endif +/* ati_spi.c */ +#if CONFIG_ATI_SPI == 1 +int ati_spi_init(void); +extern const struct flashrom_pci_match ati_spi_pci_devices[]; +#endif + /* flashrom.c */ struct decode_sizes { uint32_t parallel; -- To view, visit https://review.coreboot.org/29085 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ia5f755ae7a0723372933216516625bc156b1f4bc Gerrit-Change-Number: 29085 Gerrit-PatchSet: 1 Gerrit-Owner: Luc Verhaegen <libv(a)skynet.be>

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flashrom-gerrit October 2018