October 2019 - flashrom-gerrit

Change in ...flashrom[master]: dediprog: Use 4BA page program without 0x12
by David Hendricks (Code Review) 25 Aug '20

25 Aug '20

David Hendricks has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/30521 Change subject: dediprog: Use 4BA page program without 0x12 ...................................................................... dediprog: Use 4BA page program without 0x12 It's not clear exactly what the difference is between WRITE_MODE_4B_ADDR_256B_PAGE_PGM with and without _0x12 from the SF600 command spec, but the former seems to work more reliably. Tested using an SF600 (FW v7.2.21), IS25LP256D, W25Q256JV, and MX25L25735. Change-Id: I3cb37ec8838f5bb02948ed52b4a2906fa033cf83 Signed-off-by: David Hendricks <david.hendricks(a)gmail.com> --- M dediprog.c 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/21/30521/1 diff --git a/dediprog.c b/dediprog.c index 2a190d2..303f1d5 100644 --- a/dediprog.c +++ b/dediprog.c @@ -398,7 +398,8 @@ } } else if (dedi_spi_cmd == WRITE_MODE_PAGE_PGM) { if (flash->chip->feature_bits & FEATURE_4BA_WRITE) { - data_packet[3] = WRITE_MODE_4B_ADDR_256B_PAGE_PGM_0x12; +// data_packet[3] = WRITE_MODE_4B_ADDR_256B_PAGE_PGM_0x12; + data_packet[3] = WRITE_MODE_4B_ADDR_256B_PAGE_PGM; data_packet[4] = JEDEC_BYTE_PROGRAM_4BA; use_4ba = true; } else if (flash->in_4ba_mode) { -- To view, visit https://review.coreboot.org/c/flashrom/+/30521 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I3cb37ec8838f5bb02948ed52b4a2906fa033cf83 Gerrit-Change-Number: 30521 Gerrit-PatchSet: 1 Gerrit-Owner: David Hendricks <david.hendricks(a)gmail.com> Gerrit-MessageType: newchange

1 1

Change in flashrom[master]: sb600spi -> fchspi: Rename AMD SPI programmer
by Edward O'Callaghan (Code Review) 24 Jun '20

24 Jun '20

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/36434 ) Change subject: sb600spi -> fchspi: Rename AMD SPI programmer ...................................................................... sb600spi -> fchspi: Rename AMD SPI programmer The AMD FCH controller has two main SPI ip core variants, the so-called 'sb600' variant and the newer 'spi100' variant. The sb600spi.c driver supports both variants and so its name isn't very general. Here we rename it to be more general. Change-Id: Iad92fb224954d66968e7aeb75cb515f075a26ac8 Signed-off-by: Edward O'Callaghan <quasisec(a)chromium.org> --- M Makefile M chipset_enable.c R fchspi.c M meson.build M programmer.h 5 files changed, 11 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/34/36434/1 diff --git a/Makefile b/Makefile index f0a1b61..143a8c1 100644 --- a/Makefile +++ b/Makefile @@ -767,7 +767,7 @@ FEATURE_CFLAGS += -D'CONFIG_INTERNAL=1' PROGRAMMER_OBJS += processor_enable.o chipset_enable.o board_enable.o cbtable.o internal.o ifeq ($(ARCH), x86) -PROGRAMMER_OBJS += it87spi.o it85spi.o sb600spi.o amd_imc.o wbsio_spi.o mcp6x_spi.o +PROGRAMMER_OBJS += it87spi.o it85spi.o fchspi.o amd_imc.o wbsio_spi.o mcp6x_spi.o PROGRAMMER_OBJS += ichspi.o dmi.o ifeq ($(CONFIG_INTERNAL_DMI), yes) FEATURE_CFLAGS += -D'CONFIG_INTERNAL_DMI=1' diff --git a/chipset_enable.c b/chipset_enable.c index b55852c..e57a18e 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -1297,7 +1297,7 @@ return enable_flash_amd_via(dev, name, 0xE0); } -static int enable_flash_sb600(struct pci_dev *dev, const char *name) +static int enable_flash_fch(struct pci_dev *dev, const char *name) { uint32_t prot; uint8_t reg; @@ -1330,7 +1330,7 @@ internal_buses_supported &= BUS_LPC | BUS_FWH; - ret = sb600_probe_spi(dev); + ret = fch_probe_spi(dev); /* Read ROM strap override register. */ OUTB(0x8f, 0xcd6); @@ -1685,16 +1685,16 @@ const struct penable chipset_enables[] = { #if defined(__i386__) || defined(__x86_64__) {0x1002, 0x4377, B_PFL, OK, "ATI", "SB400", enable_flash_sb400}, - {0x1002, 0x438d, B_FLS, OK, "AMD", "SB600", enable_flash_sb600}, - {0x1002, 0x439d, B_FLS, OK, "AMD", "SB7x0/SB8x0/SB9x0", enable_flash_sb600}, + {0x1002, 0x438d, B_FLS, OK, "AMD", "SB600", enable_flash_fch}, + {0x1002, 0x439d, B_FLS, OK, "AMD", "SB7x0/SB8x0/SB9x0", enable_flash_fch}, {0x100b, 0x0510, B_PFL, NT, "AMD", "SC1100", enable_flash_sc1100}, {0x1022, 0x2080, B_PFL, OK, "AMD", "CS5536", enable_flash_cs5536}, {0x1022, 0x2090, B_PFL, OK, "AMD", "CS5536", enable_flash_cs5536}, {0x1022, 0x3000, B_PFL, OK, "AMD", "Elan SC520", get_flashbase_sc520}, {0x1022, 0x7440, B_PFL, OK, "AMD", "AMD-768", enable_flash_amd_768_8111}, {0x1022, 0x7468, B_PFL, OK, "AMD", "AMD-8111", enable_flash_amd_768_8111}, - {0x1022, 0x780e, B_FLS, OK, "AMD", "FCH", enable_flash_sb600}, - {0x1022, 0x790e, B_FLS, OK, "AMD", "FP4", enable_flash_sb600}, + {0x1022, 0x780e, B_FLS, OK, "AMD", "FCH", enable_flash_fch}, + {0x1022, 0x790e, B_FLS, OK, "AMD", "FP4", enable_flash_fch}, {0x1039, 0x0406, B_PFL, NT, "SiS", "501/5101/5501", enable_flash_sis501}, {0x1039, 0x0496, B_PFL, NT, "SiS", "85C496+497", enable_flash_sis85c496}, {0x1039, 0x0530, B_PFL, OK, "SiS", "530", enable_flash_sis530}, diff --git a/sb600spi.c b/fchspi.c similarity index 99% rename from sb600spi.c rename to fchspi.c index 7bdd11f..e0eab07 100644 --- a/sb600spi.c +++ b/fchspi.c @@ -579,7 +579,7 @@ return amd_imc_shutdown(dev); } -int sb600_probe_spi(struct pci_dev *dev) +int fch_probe_spi(struct pci_dev *dev) { struct pci_dev *smbus_dev; uint32_t tmp; diff --git a/meson.build b/meson.build index d1f663f..d4bbff7 100644 --- a/meson.build +++ b/meson.build @@ -182,7 +182,7 @@ srcs += 'it85spi.c' srcs += 'it87spi.c' srcs += 'mcp6x_spi.c' - srcs += 'sb600spi.c' + srcs += 'fchspi.c' srcs += 'wbsio_spi.c' endif config_bitbang_spi = true diff --git a/programmer.h b/programmer.h index e42c6bb..e2cadd9 100644 --- a/programmer.h +++ b/programmer.h @@ -657,8 +657,8 @@ /* mcp6x_spi.c */ int mcp6x_spi_init(int want_spi); -/* sb600spi.c */ -int sb600_probe_spi(struct pci_dev *dev); +/* fchspi.c */ +int fch_probe_spi(struct pci_dev *dev); /* wbsio_spi.c */ int wbsio_check_for_spi(void); -- To view, visit https://review.coreboot.org/c/flashrom/+/36434 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Iad92fb224954d66968e7aeb75cb515f075a26ac8 Gerrit-Change-Number: 36434 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

3 2

Change in flashrom[master]: sb600spi.c: Improve IMC runtime detection in handle_imc()
by Edward O'Callaghan (Code Review) 24 Jun '20

24 Jun '20

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/36424 ) Change subject: sb600spi.c: Improve IMC runtime detection in handle_imc() ...................................................................... sb600spi.c: Improve IMC runtime detection in handle_imc() The IMC detection in sb600spi is very rudimentary and incomplete. This expands it so that it can actually detect not only whether an IMC is in the system, but whether it's active or not. This is based off ChromiumOS's fork of flashrom where the solution looks to be originally authored by Martin Roth in b/62141938. Change-Id: I13fb2300475c06aad09a4f0e8cd032e212556b14 Signed-off-by: Edward O'Callaghan <quasisec(a)chromium.org> --- M sb600spi.c 1 file changed, 34 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/24/36424/1 diff --git a/sb600spi.c b/sb600spi.c index c89d5a9..3c83b7b 100644 --- a/sb600spi.c +++ b/sb600spi.c @@ -55,6 +55,15 @@ #define FIFO_SIZE_OLD 8 #define FIFO_SIZE_YANGTZE 71 +#define PM_INDEX 0xCD6 +#define PM_DATA 0xCD7 +#define ISA_CONTROL 0x04 +#define MMIO_EN 0x02 +#define ACPI_MMIO_BASE 0xFED80000 +#define MISC_BASE 0xE00 +#define STRAP_STATUS 0x80 +#define EC_ENABLE_STRAP 0x04 + static int sb600_spi_send_command(struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); static int spi100_spi_send_command(struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, @@ -80,6 +89,12 @@ .write_aai = default_spi_write_aai, }; +static uint8_t pm_ioread(uint8_t addr) +{ + OUTB(addr, PM_INDEX); + return INB(PM_DATA); +} + static int find_smbus_dev(uint16_t vendor, uint16_t device) { struct pci_dev *smbus_dev = pci_dev_find(vendor, device); @@ -522,6 +537,25 @@ return 0; } + /* On Yangtze and newer chips, check the EcEnableStrap bit */ + if ((amd_gen >= CHIPSET_YANGTZE) && (pm_ioread(ISA_CONTROL) & MMIO_EN )) { + uint8_t *AcpiMMIO = rphysmap("AMD ACPI registers", ACPI_MMIO_BASE & 0xfffff000, 0x1000); + if (AcpiMMIO != ERROR_PTR) { + AcpiMMIO += MISC_BASE + STRAP_STATUS; + uint32_t straps = mmio_readl(AcpiMMIO); + if ((straps & EC_ENABLE_STRAP) == 0){ + msg_pinfo("IMC is not active.\n"); + return 0; + } else { + msg_pinfo("IMC IS active! Straps: %08x (%p)\n", straps, (void *)AcpiMMIO); + msg_pinfo("StrapOverride: %08x\n", mmio_readl(AcpiMMIO + 4)); + } + + } else { + msg_pinfo("Error reading AMD ACPI registers.\n"); + } + } + if (!amd_imc_force) programmer_may_write = 0; msg_pinfo("Writes have been disabled for safety reasons because the presence of the IMC\n" -- To view, visit https://review.coreboot.org/c/flashrom/+/36424 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I13fb2300475c06aad09a4f0e8cd032e212556b14 Gerrit-Change-Number: 36424 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

3 4

Change in flashrom[master]: flashchips: add W25M512JV
by Joel Stanley (Code Review) 08 Apr '20

08 Apr '20

Joel Stanley has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/34595 ) Change subject: flashchips: add W25M512JV ...................................................................... flashchips: add W25M512JV https://www.winbond.com/resource-files/w25m512jv%20revd%2009052017.pdf Change-Id: I8d16f0918785795cc49500435a03641b87d706e9 Signed-off-by: Joel Stanley <joel(a)jms.id.au> --- M flashchips.c M flashchips.h 2 files changed, 20 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/95/34595/1 diff --git a/flashchips.c b/flashchips.c index 166af6a..304ebe7 100644 --- a/flashchips.c +++ b/flashchips.c @@ -15902,6 +15902,25 @@ { .vendor = "Winbond", + .name = "W25Q512JV", + .bustype = BUS_SPI, + .manufacture_id = WINBOND_NEX_ID, + .model_id = WINBOND_NEX_W25Q512JV, + .total_size = 64 * 1024, + .page_size = 1024, + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA, + .tested = TEST_OK_PREW, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .printlock = spi_prettyprint_status_register_plain, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {2700, 3600}, + }, + + { + .vendor = "Winbond", .name = "W25Q256JV_M", .bustype = BUS_SPI, .manufacture_id = WINBOND_NEX_ID, diff --git a/flashchips.h b/flashchips.h index 006b95e..c606161 100644 --- a/flashchips.h +++ b/flashchips.h @@ -921,6 +921,7 @@ #define WINBOND_NEX_W25Q64_V 0x4017 /* W25Q64BV, W25Q64CV; W25Q64FV in SPI mode (default) */ #define WINBOND_NEX_W25Q128_V 0x4018 /* W25Q128BV; W25Q128FV in SPI mode (default) */ #define WINBOND_NEX_W25Q256_V 0x4019 /* W25Q256FV or W25Q256JV_Q (QE=1) */ +#define WINBOND_NEX_W25Q512JV 0x4020 /* W25Q512JV */ #define WINBOND_NEX_W25Q20_W 0x5012 /* W25Q20BW */ #define WINBOND_NEX_W25Q40BW 0x5013 /* W25Q40BW */ #define WINBOND_NEX_W25Q80BW 0x5014 /* W25Q80BW */ -- To view, visit https://review.coreboot.org/c/flashrom/+/34595 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I8d16f0918785795cc49500435a03641b87d706e9 Gerrit-Change-Number: 34595 Gerrit-PatchSet: 1 Gerrit-Owner: Joel Stanley Gerrit-MessageType: newchange

4 10

Change in flashrom[master]: Add support for STLINK V3 debugger/programmer via it's SPI bridge
by Miklós Márton (Code Review) 31 Dec '19

31 Dec '19

Miklós Márton has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/34661 ) Change subject: Add support for STLINK V3 debugger/programmer via it's SPI bridge ...................................................................... Add support for STLINK V3 debugger/programmer via it's SPI bridge Change-Id: Icffab87ac8f2c570187ed753ec70f054541873a4 Signed-off-by: Miklós Márton <martonmiklosqdev(a)gmail.com> --- M Makefile M flashrom.8.tmpl M flashrom.c M meson.build M programmer.h A stlinkv3_spi.c 6 files changed, 670 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/61/34661/1 diff --git a/Makefile b/Makefile index 545e84a..58dc86a 100644 --- a/Makefile +++ b/Makefile @@ -190,6 +190,11 @@ else override CONFIG_CH341A_SPI = no endif +ifeq ($(CONFIG_STLINKV3_SPI), yes) +UNSUPPORTED_FEATURES += CONFIG_STLINKV3_SPI=yes +else +override CONFIG_STLINKV3_SPI = no +endif # libjaylink is also not available for DOS ifeq ($(CONFIG_JLINK_SPI), yes) UNSUPPORTED_FEATURES += CONFIG_JLINK_SPI=yes @@ -353,6 +358,11 @@ else override CONFIG_PICKIT2_SPI = no endif +ifeq ($(CONFIG_STLINKV3_SPI), yes) +UNSUPPORTED_FEATURES += CONFIG_STLINKV3_SPI=yes +else +override CONFIG_STLINKV3_SPI = no +endif ifeq ($(CONFIG_CH341A_SPI), yes) UNSUPPORTED_FEATURES += CONFIG_CH341A_SPI=yes else @@ -618,6 +628,9 @@ # Always enable PICkit2 SPI dongles for now. CONFIG_PICKIT2_SPI ?= yes +# Always enable STLink V3 +CONFIG_STLINKV3_SPI ?= yes + # Always enable dummy tracing for now. CONFIG_DUMMY ?= yes @@ -696,6 +709,7 @@ override CONFIG_DIGILENT_SPI = no override CONFIG_DEVELOPERBOX_SPI = no override CONFIG_PICKIT2_SPI = no +override CONFIG_STLINKV3_SPI = no endif ifeq ($(CONFIG_ENABLE_LIBPCI_PROGRAMMERS), no) override CONFIG_INTERNAL = no @@ -863,6 +877,12 @@ NEED_LIBUSB1 += CONFIG_PICKIT2_SPI endif +ifeq ($(CONFIG_STLINKV3_SPI), yes) +FEATURE_CFLAGS += -D'CONFIG_STLINKV3_SPI=1' +PROGRAMMER_OBJS += stlinkv3_spi.o +NEED_LIBUSB1 += CONFIG_STLINKV3_SPI +endif + ifneq ($(NEED_LIBFTDI), ) FTDILIBS := $(call debug_shell,[ -n "$(PKG_CONFIG_LIBDIR)" ] && export PKG_CONFIG_LIBDIR="$(PKG_CONFIG_LIBDIR)" ; $(PKG_CONFIG) --libs libftdi1 || $(PKG_CONFIG) --libs libftdi || printf "%s" "-lftdi -lusb") FEATURE_CFLAGS += $(call debug_shell,grep -q "FT232H := yes" .features && printf "%s" "-D'HAVE_FT232H=1'") diff --git a/flashrom.8.tmpl b/flashrom.8.tmpl index 30dc97d..5f518a4 100644 --- a/flashrom.8.tmpl +++ b/flashrom.8.tmpl @@ -333,6 +333,8 @@ .sp .BR "* jlink_spi" " (for SPI flash ROMs attached to SEGGER J-Link and compatible devices)" .sp +.BR "* stlinkv3_spi" " (for SPI flash ROMs attached to STMicroelectronics STLINK V3 devices)" +.sp Some programmers have optional or mandatory parameters which are described in detail in the .B PROGRAMMER-SPECIFIC INFORMATION @@ -1186,6 +1188,31 @@ .sp syntax where \fBfrequency\fP is the SPI clock frequency in kHz. The maximum speed depends on the device in use. +SS +.BR "stlinkv3_spi " programmer +.IP +This module supports SPI flash programming through the STMicroelectronics +STLINK V3 programmer/debugger's SPI bridge interface +.sp +.B " flashrom \-p stlinkv3_spi" +.sp +If there is more than one compatible device connected, you can select which one +should be used by specifying its serial number with the +.sp +.B " flashrom \-p stlinkv3_spi:serial=number" +.sp +syntax where +.B number +is the serial number of the device (which can be found for example in the +output of lsusb -v). +.sp +The SPI speed can be selected by using the +.sp +.B " flashrom \-p stlinkv3_spi:spispeed=frequency" +.sp +syntax where \fBfrequency\fP is the SPI clock frequency in kHz. +If the passed frequency is not supported by the adapter the nearest lower +supported frequency will be used. .SS .SH EXAMPLES diff --git a/flashrom.c b/flashrom.c index cb1dca6..fdb77b6 100644 --- a/flashrom.c +++ b/flashrom.c @@ -449,6 +449,18 @@ }, #endif +#if CONFIG_STLINKV3_SPI == 1 + { + .name = "stlinkv3_spi", + .type = USB, + .devs.dev = devs_stlinkv3_spi, + .init = stlinkv3_spi_init, + .map_flash_region = fallback_map, + .unmap_flash_region = fallback_unmap, + .delay = internal_delay, + }, +#endif + {0}, /* This entry corresponds to PROGRAMMER_INVALID. */ }; diff --git a/meson.build b/meson.build index e1b6c16..2b5ef2e 100644 --- a/meson.build +++ b/meson.build @@ -62,6 +62,7 @@ config_satasii = get_option('config_satasii') config_serprog = get_option('config_serprog') config_usbblaster_spi = get_option('config_usbblaster_spi') +config_stlinkv3_spi = get_option('config_stlinkv3_spi') cargs = [] deps = [] @@ -272,6 +273,10 @@ srcs += 'usbblaster_spi.c' cargs += '-DCONFIG_USBBLASTER_SPI=1' endif +if config_stlinkv3_spi + srcs += 'stlinkv3_spi.c' + cargs += '-DCONFIG_STLINKV3_SPI=1' +endif # bitbanging SPI infrastructure if config_bitbang_spi diff --git a/programmer.h b/programmer.h index f4e8b46..1843426 100644 --- a/programmer.h +++ b/programmer.h @@ -121,6 +121,9 @@ #if CONFIG_JLINK_SPI == 1 PROGRAMMER_JLINK_SPI, #endif +#if CONFIG_STLINKV3_SPI == 1 + PROGRAMMER_STLINKV3_SPI, +#endif PROGRAMMER_INVALID /* This must always be the last entry. */ }; @@ -498,6 +501,12 @@ extern const struct dev_entry devs_pickit2_spi[]; #endif +/* stlinkv3_spi.c */ +#if CONFIG_STLINKV3_SPI == 1 +int stlinkv3_spi_init(void); +extern const struct dev_entry devs_stlinkv3_spi[]; +#endif + /* rayer_spi.c */ #if CONFIG_RAYER_SPI == 1 int rayer_spi_init(void); diff --git a/stlinkv3_spi.c b/stlinkv3_spi.c new file mode 100644 index 0000000..817d28f --- /dev/null +++ b/stlinkv3_spi.c @@ -0,0 +1,597 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2019 Miklós Márton martonmiklosqdev(a)gmail.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +/* + * Driver for programming SPI flash chips using the SPI port + * of the STMicroelectronics's STLINK-V3 programmer/debugger. + * + * The implementation is inspired by the ST's STLINK-V3-BRIDGE C++ API: + * https://www.st.com/en/development-tools/stlink-v3-bridge.html + */ + +#include "flash.h" +#include "programmer.h" +#include "spi.h" + +#include <libusb.h> +#include <limits.h> +#include <stdint.h> +#include <stdlib.h> +#include <string.h> + +typedef enum { + FW_VERSION_OK, + FW_VERSION_OLD, +} fw_version_check_result_t; + +typedef enum { + SPI_BAUDRATEPRESCALER_2 = 0, + SPI_BAUDRATEPRESCALER_4 = 1, + SPI_BAUDRATEPRESCALER_8 = 2, + SPI_BAUDRATEPRESCALER_16 = 3, + SPI_BAUDRATEPRESCALER_32 = 4, + SPI_BAUDRATEPRESCALER_64 = 5, + SPI_BAUDRATEPRESCALER_128 = 6, + SPI_BAUDRATEPRESCALER_256 = 7 +} SPI_prescaler_t; + +typedef enum { + SPI_DIRECTION_2LINES_FULLDUPLEX = 0, + SPI_DIRECTION_2LINES_RXONLY = 1, + SPI_DIRECTION_1LINE_RX = 2, + SPI_DIRECTION_1LINE_TX = 3 +} SPI_dir_t; + +typedef enum { + SPI_MODE_SLAVE = 0, + SPI_MODE_MASTER = 1 +} SPI_mode_t; + +typedef enum { + SPI_DATASIZE_16B = 0, + SPI_DATASIZE_8B = 1 +} SPI_datasize_t; + +typedef enum { + SPI_CPOL_LOW = 0, + SPI_CPOL_HIGH = 1 +} SPI_CPOL_t; + +typedef enum { + SPI_CPHA_1EDGE = 0, + SPI_CPHA_2EDGE = 1 +} SPI_CPHA_t; + +typedef enum { + SPI_FIRSTBIT_LSB = 0, + SPI_FIRSTBIT_MSB = 1 +} SPI_firstbit_t; + +typedef enum { + SPI_NSS_SOFT = 0, + SPI_NSS_HARD = 1 +} SPI_NSS_t; + +typedef enum { + SPI_NSS_LOW = 0, + SPI_NSS_HIGH = 1 +} SPI_NSS_Level_t; + +#define ST_GETVERSION_EXT 0xFB + +#define STLINK_BRIDGE_COMMAND 0xFC +#define STLINK_BRIDGE_CLOSE 0x01 +#define STLINK_BRIDGE_GET_RWCMD_STATUS 0x02 +#define STLINK_BRIDGE_GET_CLOCK 0x03 +#define STLINK_BRIDGE_INIT_SPI 0x20 +#define STLINK_BRIDGE_WRITE_SPI 0x21 +#define STLINK_BRIDGE_READ_SPI 0x22 +#define STLINK_BRIDGE_CS_SPI 0x23 + +#define STLINK_BRIDGE_SPI_ERROR 0x02 + +#define STLINK_SPI_COM 0x02 + +#define STLINK_EP_OUT 0x06 +#define STLINK_EP_IN 0x86 + +#define FIRMWARE_BRIDGE_STLINK_V3_LAST_VERSION 3 + +#define USB_TIMEOUT 5000 + +const struct dev_entry devs_stlinkv3_spi[] = { + {0x0483, 0x374F, OK, "STMicroelectronics", "STLINK-V3"}, + {0} +}; + +static struct libusb_context *usb_ctx; +static libusb_device_handle *stlinkv3_handle; + +/** + * @param[out] bridge_input_clk Current input frequency in kHz of the given com. + */ +static int stlinkv3_get_clk(uint32_t *bridge_input_clk) +{ + uint8_t command[16]; + uint8_t answer[12]; + int actualLength = 0; + int rc = 0; + + if (bridge_input_clk == NULL) + return -1; + + memset(command, 0, sizeof(command)); + memset(answer, 0, sizeof(answer)); + + command[0] = STLINK_BRIDGE_COMMAND; + command[1] = STLINK_BRIDGE_GET_CLOCK; + command[2] = STLINK_SPI_COM; + + rc = libusb_bulk_transfer(stlinkv3_handle, STLINK_EP_OUT, + command, sizeof(command), + &actualLength, USB_TIMEOUT); + if (rc != LIBUSB_TRANSFER_COMPLETED || actualLength != sizeof(command)) { + msg_perr("Failed to issue the STLINK_BRIDGE_GET_CLOCK command: '%s'\n", + libusb_error_name(rc)); + return -1; + } + + rc = libusb_bulk_transfer(stlinkv3_handle, STLINK_EP_IN, + answer, sizeof(answer), + &actualLength, USB_TIMEOUT); + if (rc != LIBUSB_TRANSFER_COMPLETED || actualLength != sizeof(answer)) { + msg_perr("Failed to get STLINK_BRIDGE_GET_CLOCK answer: '%s'\n", + libusb_error_name(rc)); + return -1; + } + + *bridge_input_clk = (uint32_t)answer[4] + | (uint32_t)answer[5]<<8 + | (uint32_t)answer[6]<<16 + | (uint32_t)answer[7]<<24; + return 0; + +} + +static int stlinkv3_spi_calc_prescaler(uint16_t reqd_freq_in_kHz, + SPI_prescaler_t *prescaler, + uint16_t *calculated_freq_in_kHz) +{ + uint32_t bridge_clk_in_kHz; + uint32_t calculated_prescaler = 1; + uint16_t prescaler_value; + + if (stlinkv3_get_clk(&bridge_clk_in_kHz)) + return -1; + + calculated_prescaler = bridge_clk_in_kHz/reqd_freq_in_kHz; + // Apply a smaller frequency if not exact + if (calculated_prescaler <= 2) { + *prescaler = SPI_BAUDRATEPRESCALER_2; + prescaler_value = 2; + } else if (calculated_prescaler <= 4) { + *prescaler = SPI_BAUDRATEPRESCALER_4; + prescaler_value = 4; + } else if (calculated_prescaler <= 8) { + *prescaler = SPI_BAUDRATEPRESCALER_8; + prescaler_value = 8; + } else if (calculated_prescaler <= 16) { + *prescaler = SPI_BAUDRATEPRESCALER_16; + prescaler_value = 16; + } else if (calculated_prescaler <= 32) { + *prescaler = SPI_BAUDRATEPRESCALER_32; + prescaler_value = 32; + } else if (calculated_prescaler <= 64) { + *prescaler = SPI_BAUDRATEPRESCALER_64; + prescaler_value = 64; + } else if (calculated_prescaler <= 128) { + *prescaler = SPI_BAUDRATEPRESCALER_128; + prescaler_value = 128; + } else if (calculated_prescaler <= 256) { + *prescaler = SPI_BAUDRATEPRESCALER_256; + prescaler_value = 256; + } else { + // smaller frequency not possible + *prescaler = SPI_BAUDRATEPRESCALER_256; + prescaler_value = 256; + } + + *calculated_freq_in_kHz = bridge_clk_in_kHz / prescaler_value; + + return 0; +} + +static int stlinkv3_check_version(fw_version_check_result_t *result) +{ + uint8_t answer[12]; + uint8_t command[16]; + int actualLength = 0; + int rc = 0; + + memset(command, 0, sizeof(command)); + + command[0] = ST_GETVERSION_EXT; + command[1] = 0x80; + + rc = libusb_bulk_transfer(stlinkv3_handle, STLINK_EP_OUT, + command, sizeof(command), + &actualLength, USB_TIMEOUT); + if (rc != LIBUSB_TRANSFER_COMPLETED || actualLength != sizeof(command)) { + msg_perr("Failed to issue the ST_GETVERSION_EXT command: '%s'\n", + libusb_error_name(rc)); + return -1; + } + + rc = libusb_bulk_transfer(stlinkv3_handle, STLINK_EP_IN, + answer, sizeof(answer), + &actualLength, USB_TIMEOUT); + if (rc != LIBUSB_TRANSFER_COMPLETED || actualLength != sizeof(answer)) { + msg_perr("Failed to retrive the ST_GETVERSION_EXT answer: '%s'\n", + libusb_error_name(rc)); + return -1; + } + + msg_pinfo("Connected to STLink V3 with bridge FW version: %d\n", answer[4]); + *result = answer[4] >= FIRMWARE_BRIDGE_STLINK_V3_LAST_VERSION + ? FW_VERSION_OK + : FW_VERSION_OLD; + return 0; +} + +static int stlinkv3_spi_open(uint16_t reqested_freq_in_kHz) +{ + uint8_t command[16]; + uint8_t answer[2]; + uint16_t SCK_freq_in_kHz; + int actualLength = 0; + int rc = 0; + SPI_prescaler_t prescaler; + fw_version_check_result_t fw_check_result; + + if (stlinkv3_check_version(&fw_check_result)) { + msg_perr("Failed to query FW version"); + return -1; + } + + if (fw_check_result != FW_VERSION_OK) { + msg_pinfo("Your STLink V3 has too old version of the bridge interface\n" + "Please update the firmware with the " + "STSW-LINK007 which can be downloaded from here:\n" + "https://www.st.com/en/development-tools/stsw-link007.html"); + return -1; + } + + if (stlinkv3_spi_calc_prescaler(reqested_freq_in_kHz, + &prescaler, + &SCK_freq_in_kHz)) { + msg_perr("Failed to calculate SPI clock prescaler"); + return -1; + } + msg_pinfo("SCK frequency set to %d kHz\n", SCK_freq_in_kHz); + + memset(command, 0, sizeof(command)); + memset(answer, 0, sizeof(answer)); + + command[0] = STLINK_BRIDGE_COMMAND; + command[1] = STLINK_BRIDGE_INIT_SPI; + command[2] = SPI_DIRECTION_2LINES_FULLDUPLEX; + command[3] = (SPI_MODE_MASTER + | (SPI_CPHA_1EDGE << 1) + | (SPI_CPOL_LOW << 2) + | (SPI_FIRSTBIT_MSB << 3)); + command[4] = SPI_DATASIZE_8B; + command[5] = SPI_NSS_SOFT; + command[6] = (uint8_t)prescaler; + + rc = libusb_bulk_transfer(stlinkv3_handle, STLINK_EP_OUT, + command, sizeof(command), + &actualLength, USB_TIMEOUT); + if (rc != LIBUSB_TRANSFER_COMPLETED && actualLength != sizeof(command)) { + msg_perr("Failed to issue the STLINK_BRIDGE_INIT_SPI command: '%s'\n", + libusb_error_name(rc)); + return -1; + } + + rc = libusb_bulk_transfer(stlinkv3_handle, STLINK_EP_IN, + answer, sizeof(answer), + &actualLength, USB_TIMEOUT); + if (rc != LIBUSB_TRANSFER_COMPLETED || actualLength != sizeof(answer)) { + msg_perr("Failed to retrive the STLINK_BRIDGE_INIT_SPI answer: '%s'\n", + libusb_error_name(rc)); + return -1; + } + return 0; +} + +static int stlinkv3_get_last_readwrite_status(uint32_t *status) +{ + uint8_t command[16]; + uint16_t answer[4]; + int rc = 0; + int actualLength = 0; + + memset(command, 0, sizeof(command)); + memset(answer, 0, sizeof(answer)); + + command[0] = STLINK_BRIDGE_COMMAND; + command[1] = STLINK_BRIDGE_GET_RWCMD_STATUS; + + rc = libusb_bulk_transfer(stlinkv3_handle, STLINK_EP_OUT, + command, sizeof(command), + &actualLength, USB_TIMEOUT); + if (rc != LIBUSB_TRANSFER_COMPLETED || actualLength != sizeof(command)) { + msg_perr("Failed to issue the STLINK_BRIDGE_GET_RWCMD_STATUS command: '%s'\n", + libusb_error_name(rc)); + return -1; + } + + rc = libusb_bulk_transfer(stlinkv3_handle, + STLINK_EP_IN, + (uint8_t *)answer, + sizeof(answer), + &actualLength, + USB_TIMEOUT); + if (rc != LIBUSB_TRANSFER_COMPLETED || actualLength != sizeof(answer)) { + msg_perr("Failed to retrive the STLINK_BRIDGE_GET_RWCMD_STATUS answer: '%s'\n", + libusb_error_name(rc)); + return -1; + } + + *status = (uint32_t)answer[2] | (uint32_t)answer[3]<<16; + return 0; +} + +static int stlinkv3_spi_set_SPI_NSS(SPI_NSS_Level_t NSS_level) +{ + uint8_t command[16]; + uint8_t answer[2]; + int rc = 0; + int actualLength = 0; + + memset(command, 0, sizeof(command)); + memset(answer, 0, sizeof(answer)); + + command[0] = STLINK_BRIDGE_COMMAND; + command[1] = STLINK_BRIDGE_CS_SPI; + command[2] = (uint8_t) (NSS_level); + + rc = libusb_bulk_transfer(stlinkv3_handle, STLINK_EP_OUT, + command, sizeof(command), + &actualLength, USB_TIMEOUT); + if (rc != LIBUSB_TRANSFER_COMPLETED || actualLength != sizeof(command)) { + msg_perr("Failed to issue the STLINK_BRIDGE_CS_SPI command: '%s'\n", + libusb_error_name(rc)); + return -1; + } + + rc = libusb_bulk_transfer(stlinkv3_handle, + STLINK_EP_IN, + (uint8_t *)answer, + sizeof(answer), + &actualLength, + USB_TIMEOUT); + if (rc != LIBUSB_TRANSFER_COMPLETED || actualLength != sizeof(answer)) { + msg_perr("Failed to retrive the STLINK_BRIDGE_CS_SPI answer: '%s'\n", + libusb_error_name(rc)); + return -1; + } + return 0; +} + +static int stlinkv3_spi_transmit(struct flashctx *flash, + unsigned int write_cnt, + unsigned int read_cnt, + const unsigned char *write_arr, + unsigned char *read_arr) +{ + uint8_t command[16]; + int rc = 0 ; + int actualLength = 0; + uint32_t rw_status = 0; + + if (stlinkv3_spi_set_SPI_NSS(SPI_NSS_LOW)) { + msg_perr("Failed to set the NSS pin to low\n"); + return -1; + } + + memset(command, 0, sizeof(command)); + + command[0] = STLINK_BRIDGE_COMMAND; + command[1] = STLINK_BRIDGE_WRITE_SPI; + command[2] = (uint8_t)write_cnt; + command[3] = (uint8_t)(write_cnt >> 8); + + for (unsigned int i = 0; (i < 8) && (i < write_cnt); i++) + command[4+i] = write_arr[i]; + + rc = libusb_bulk_transfer(stlinkv3_handle, STLINK_EP_OUT, + command, sizeof(command), + &actualLength, USB_TIMEOUT); + if (rc != LIBUSB_TRANSFER_COMPLETED || actualLength != sizeof(command)) { + msg_perr("Failed to issue the STLINK_BRIDGE_WRITE_SPI command: '%s'\n", + libusb_error_name(rc)); + goto transmit_err; + } + + if (write_cnt > 8) { + rc = libusb_bulk_transfer(stlinkv3_handle, + STLINK_EP_OUT, + (unsigned char *)&write_arr[8], + (unsigned int)(write_cnt - 8), + &actualLength, + USB_TIMEOUT); + if (rc != LIBUSB_TRANSFER_COMPLETED || actualLength != (write_cnt - 8)) { + msg_perr("Failed to send the data after the " + "STLINK_BRIDGE_WRITE_SPI command: '%s'\n", + libusb_error_name(rc)); + goto transmit_err; + } + } + + if (stlinkv3_get_last_readwrite_status(&rw_status)) + return -1; + + if (rw_status != 0) { + msg_perr("SPI read/write failure: %d\n", rw_status); + goto transmit_err; + } + + if (read_cnt) { + command[1] = STLINK_BRIDGE_READ_SPI; + command[2] = (uint8_t)read_cnt; + command[3] = (uint8_t)(read_cnt >> 8); + + rc = libusb_bulk_transfer(stlinkv3_handle, STLINK_EP_OUT, + command, sizeof(command), + &actualLength, USB_TIMEOUT); + if (rc != LIBUSB_TRANSFER_COMPLETED || actualLength != sizeof(command)) { + msg_perr("Failed to issue the STLINK_BRIDGE_READ_SPI command: '%s'\n", + libusb_error_name(rc)); + goto transmit_err; + } + + rc = libusb_bulk_transfer(stlinkv3_handle, + STLINK_EP_IN, + (unsigned char *)read_arr, + (int)read_cnt, + &actualLength, + USB_TIMEOUT); + if (rc != LIBUSB_TRANSFER_COMPLETED || actualLength != read_cnt) { + msg_perr("Failed to retrive the STLINK_BRIDGE_READ_SPI answer: '%s'\n", + libusb_error_name(rc)); + goto transmit_err; + } + } + + if (stlinkv3_get_last_readwrite_status(&rw_status)) + goto transmit_err; + + if (rw_status != 0) { + msg_perr("SPI read/write failure: %d\n", rw_status); + goto transmit_err; + } + + if (stlinkv3_spi_set_SPI_NSS(SPI_NSS_HIGH)) { + msg_perr("Failed to set the NSS pin to high\n"); + return -1; + } + return 0; + +transmit_err: + if (stlinkv3_spi_set_SPI_NSS(SPI_NSS_HIGH)) + msg_perr("Failed to set the NSS pin to high\n"); + return -1; +} + +static int stlinkv3_spi_shutdown(void *data) +{ + uint8_t command[16]; + uint8_t answer[2]; + int actualLength = 0; + int rc = 0; + + memset(command, 0, sizeof(command)); + memset(answer, 0, sizeof(answer)); + + command[0] = STLINK_BRIDGE_COMMAND; + command[1] = STLINK_BRIDGE_CLOSE; + command[2] = STLINK_SPI_COM; + + rc = libusb_bulk_transfer(stlinkv3_handle, STLINK_EP_OUT, + command, sizeof(command), &actualLength, USB_TIMEOUT); + if (rc != LIBUSB_TRANSFER_COMPLETED || actualLength != sizeof(command)) + msg_perr("Failed to issue the STLINK_BRIDGE_CLOSE command: '%s'\n", + libusb_error_name(rc)); + + rc = libusb_bulk_transfer(stlinkv3_handle, STLINK_EP_IN, + answer, sizeof(answer), &actualLength, USB_TIMEOUT); + if (rc != LIBUSB_TRANSFER_COMPLETED || actualLength != sizeof(answer)) + msg_perr("Failed to retrive the STLINK_BRIDGE_CLOSE answer: '%s'\n", + libusb_error_name(rc)); + + libusb_close(stlinkv3_handle); + libusb_exit(usb_ctx); + + return 0; +} + +static const struct spi_master spi_programmer_stlinkv3 = { + .max_data_read = UINT16_MAX, + .max_data_write = UINT16_MAX, + .command = stlinkv3_spi_transmit, + .multicommand = default_spi_send_multicommand, + .read = default_spi_read, + .write_256 = default_spi_write_256, + .write_aai = default_spi_write_aai, +}; + +int stlinkv3_spi_init(void) +{ + uint16_t sck_freq_kHz = 1000; // selecting 1 MHz SCK is a good bet + char *speed_str = NULL; + char *serialno = NULL; + char *endptr = NULL; + + libusb_init(&usb_ctx); + if (!usb_ctx) { + msg_perr("Could not initialize libusb!\n"); + return 1; + } + + serialno = extract_programmer_param("serial"); + if (serialno) + msg_pdbg("Opening STLINK-V3 with serial: %s\n", serialno); + stlinkv3_handle = usb_dev_get_by_vid_pid_serial(usb_ctx, + devs_stlinkv3_spi[0].vendor_id, devs_stlinkv3_spi[0].device_id, serialno); + + if (!stlinkv3_handle) { + if (serialno) + msg_perr("No STLINK-V3 seems to be connected with serial %s\n", serialno); + else + msg_perr("Could not find any connected STLINK-V3\n"); + free(serialno); + goto err_exit; + } + free(serialno); + + speed_str = extract_programmer_param("spispeed"); + if (speed_str) { + sck_freq_kHz = strtoul(speed_str, &endptr, 0); + if (*endptr) { + msg_perr("The spispeed parameter passed with invalid format: %s\n", + speed_str); + msg_perr("Please pass the parameter with a simple number in kHz\n"); + return -1; + } + free(speed_str); + } + + if (stlinkv3_spi_open(sck_freq_kHz)) + goto err_exit; + + if (register_shutdown(stlinkv3_spi_shutdown, NULL)) + goto err_exit; + + if (register_spi_master(&spi_programmer_stlinkv3)) + goto err_exit; + + return 0; + +err_exit: + libusb_exit(usb_ctx); + return 1; +} -- To view, visit https://review.coreboot.org/c/flashrom/+/34661 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Icffab87ac8f2c570187ed753ec70f054541873a4 Gerrit-Change-Number: 34661 Gerrit-PatchSet: 1 Gerrit-Owner: Miklós Márton <martonmiklosqdev(a)gmail.com> Gerrit-MessageType: newchange

4 25

Change in ...flashrom[master]: Add "--dangerous-bruteforce" mode for the unreliable ISP environments
by mikeb mikeb (Code Review) 29 Dec '19

29 Dec '19

Hello Mike Banon, I'd like you to do a code review. Please visit https://review.coreboot.org/c/flashrom/+/31830 to review the following change. Change subject: Add "--dangerous-bruteforce" mode for the unreliable ISP environments ...................................................................... Add "--dangerous-bruteforce" mode for the unreliable ISP environments Some in-system-programming environments are very unreliable, e.g. when you connect a SOIC8 test clip to the flash chip of WR841ND v9 wireless router: because the low power SOC of this router becomes powered and is constantly trying to boot, the router's flash chip is correctly detected only 30% of times, and when it is detected just 30% of the read operations are successful - the rest result in zeroes or garbage data being read from a flash chip. While in this new "--dangerous-bruteforce" mode, flashrom will be constantly probing for a flash chip until it is correctly detected - and then, depending on the operation selected by a user, at the moments of chip availability it will be reading or writing by the small chunks of 256 bytes maximum size, verifying each small chunk and retrying the operation until the success or timeout (~ 60 sec). Constant probing between the small chunk operations is also being done - to avoid a possible situation where we have got two identical blocks of zeroes while reading a chunk and erroneously accepted it. Currently this mode is active only for those SPI25 chips which are ".write = spi_chip_write_256" and ".read = spi_chip_read", but later could be expanded to more functions to become useful for more chips. NOTE: this mode is experimental! Also, some targets like WR841ND v9 could block the ISP chip access completely if there is no bootable firmware inside (e.g. after you've tried to erase the chip contents). In such a situation it could be hard to recover the firmware without desoldering a flash chip and flashing it separately. Please do not erase or write to a flash chip using this mode if you are not sure. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: If47476793721a0061fd65bc6d1f98d48b03dc6c1 --- M cli_classic.c M flash.h M flashrom.c M libflashrom.c M libflashrom.h M spi25.c 6 files changed, 148 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/30/31830/1 diff --git a/cli_classic.c b/cli_classic.c index ced08c6..454df2b 100644 --- a/cli_classic.c +++ b/cli_classic.c @@ -51,6 +51,7 @@ " -V | --verbose more verbose output\n" " -c | --chip <chipname> probe only for specified flash chip\n" " -f | --force force specific operations (see man page)\n" + " --dangerous-bruteforce verify each small chunk and probe constantly\n" " -n | --noverify don't auto-verify\n" " -N | --noverify-all verify included regions only (cf. -i)\n" " -l | --layout <layoutfile> read ROM layout from <layoutfile>\n" @@ -104,7 +105,7 @@ #if CONFIG_PRINT_WIKI == 1 int list_supported_wiki = 0; #endif - int read_it = 0, write_it = 0, erase_it = 0, verify_it = 0; + int read_it = 0, write_it = 0, erase_it = 0, verify_it = 0, bruteforce = 0, timeout = 30000; int dont_verify_it = 0, dont_verify_all = 0, list_supported = 0, operation_specified = 0; struct flashrom_layout *layout = NULL; enum programmer prog = PROGRAMMER_INVALID; @@ -113,6 +114,7 @@ OPTION_FMAP, OPTION_FMAP_FILE, OPTION_FLASH_CONTENTS, + OPTION_BRUTEFORCE, }; int ret = 0; @@ -127,6 +129,7 @@ {"chip", 1, NULL, 'c'}, {"verbose", 0, NULL, 'V'}, {"force", 0, NULL, 'f'}, + {"dangerous-bruteforce", 0, NULL, OPTION_BRUTEFORCE}, {"layout", 1, NULL, 'l'}, {"ifd", 0, NULL, OPTION_IFD}, {"fmap", 0, NULL, OPTION_FMAP}, @@ -228,6 +231,9 @@ case 'f': force = 1; break; + case OPTION_BRUTEFORCE: + bruteforce = 1; + break; case 'l': if (layoutfile) { fprintf(stderr, "Error: --layout specified " @@ -503,16 +509,27 @@ msg_pdbg("The following protocols are supported: %s.\n", tempstr); free(tempstr); - for (j = 0; j < registered_master_count; j++) { - startchip = 0; - while (chipcount < ARRAY_SIZE(flashes)) { - startchip = probe_flash(&registered_masters[j], startchip, &flashes[chipcount], 0); - if (startchip == -1) - break; - chipcount++; - startchip++; + do { + chipcount = 0; + for (j = 0; j < registered_master_count; j++) { + startchip = 0; + while (chipcount < ARRAY_SIZE(flashes)) { + startchip = probe_flash(&registered_masters[j], startchip, &flashes[chipcount], 0); + if (startchip == -1) + break; + chipcount++; + startchip++; + } } - } + timeout--; + if (!timeout) { + msg_cerr("Error: Timed out trying to detect a chip.\n"); + ret = 1; + goto out_shutdown; + } + } while (bruteforce && ( !chipcount || // wait for the correct chip detection + ((flashes[0].chip->manufacture_id == GENERIC_MANUF_ID) || + (flashes[0].chip->model_id == GENERIC_DEVICE_ID)) ) ); if (chipcount > 1) { msg_cinfo("Multiple flash chip definitions match the detected chip(s): \"%s\"", @@ -650,6 +667,7 @@ #if CONFIG_INTERNAL == 1 flashrom_flag_set(fill_flash, FLASHROM_FLAG_FORCE_BOARDMISMATCH, !!force_boardmismatch); #endif + flashrom_flag_set(fill_flash, FLASHROM_FLAG_BRUTEFORCE, !!bruteforce); flashrom_flag_set(fill_flash, FLASHROM_FLAG_VERIFY_AFTER_WRITE, !dont_verify_it); flashrom_flag_set(fill_flash, FLASHROM_FLAG_VERIFY_WHOLE_CHIP, !dont_verify_all); diff --git a/flash.h b/flash.h index 911214c..6ba116e 100644 --- a/flash.h +++ b/flash.h @@ -256,6 +256,7 @@ struct { bool force; bool force_boardmismatch; + bool bruteforce; bool verify_after_write; bool verify_whole_chip; } flags; diff --git a/flashrom.c b/flashrom.c index e82c32e..8f2c859 100644 --- a/flashrom.c +++ b/flashrom.c @@ -1641,6 +1641,8 @@ size_t i, j; bool first = true; struct block_eraser *const eraser = &flashctx->chip->block_erasers[erasefunction]; + unsigned int bruteforce = flashrom_flag_get(flashctx, FLASHROM_FLAG_BRUTEFORCE); + int timeout; info->erase_start = 0; for (i = 0; i < NUM_ERASEREGIONS; ++i) { @@ -1662,9 +1664,34 @@ msg_cdbg(", "); msg_cdbg("0x%06x-0x%06x:", info->erase_start, info->erase_end); - ret = per_blockfn(flashctx, info, eraser->block_erase); - if (ret) - return ret; + if (!bruteforce) { + ret = per_blockfn(flashctx, info, eraser->block_erase); + if (ret) + return ret; + } else { + timeout = 30000; + while(1) { + timeout--; + if (!timeout) { + msg_cerr("%s timeout during command execution\n", __func__); + return 2; + } + + /* First probe. */ + if (flashctx->chip->probe(flashctx) != 1) + continue; + + ret = per_blockfn(flashctx, info, eraser->block_erase); + if (ret) + continue; + + /* Second probe. */ + if (flashctx->chip->probe(flashctx) != 1) + continue; + + break; + } + } } if (info->region_end < info->erase_start) break; diff --git a/libflashrom.c b/libflashrom.c index f90a22c..6dd0167 100644 --- a/libflashrom.c +++ b/libflashrom.c @@ -250,6 +250,7 @@ switch (flag) { case FLASHROM_FLAG_FORCE: flashctx->flags.force = value; break; case FLASHROM_FLAG_FORCE_BOARDMISMATCH: flashctx->flags.force_boardmismatch = value; break; + case FLASHROM_FLAG_BRUTEFORCE: flashctx->flags.bruteforce = value; break; case FLASHROM_FLAG_VERIFY_AFTER_WRITE: flashctx->flags.verify_after_write = value; break; case FLASHROM_FLAG_VERIFY_WHOLE_CHIP: flashctx->flags.verify_whole_chip = value; break; } @@ -267,6 +268,7 @@ switch (flag) { case FLASHROM_FLAG_FORCE: return flashctx->flags.force; case FLASHROM_FLAG_FORCE_BOARDMISMATCH: return flashctx->flags.force_boardmismatch; + case FLASHROM_FLAG_BRUTEFORCE: return flashctx->flags.bruteforce; case FLASHROM_FLAG_VERIFY_AFTER_WRITE: return flashctx->flags.verify_after_write; case FLASHROM_FLAG_VERIFY_WHOLE_CHIP: return flashctx->flags.verify_whole_chip; default: return false; diff --git a/libflashrom.h b/libflashrom.h index 38c95d2..0f2ead8 100644 --- a/libflashrom.h +++ b/libflashrom.h @@ -51,6 +51,7 @@ enum flashrom_flag { FLASHROM_FLAG_FORCE, FLASHROM_FLAG_FORCE_BOARDMISMATCH, + FLASHROM_FLAG_BRUTEFORCE, FLASHROM_FLAG_VERIFY_AFTER_WRITE, FLASHROM_FLAG_VERIFY_WHOLE_CHIP, }; diff --git a/spi25.c b/spi25.c index 8b6c462..832c836 100644 --- a/spi25.c +++ b/spi25.c @@ -21,6 +21,7 @@ #include <stddef.h> #include <string.h> #include <stdbool.h> +#include <stdlib.h> #include "flash.h" #include "flashchips.h" #include "chipdrivers.h" @@ -655,6 +656,48 @@ return spi_send_command(flash, 1 + addr_len, len, cmd, bytes); } +static int spi_rw_bruteforce(struct flashctx *flash, uint8_t *buf1, uint8_t *buf2, + unsigned int startrw_here, unsigned int torw_len, bool rw_flag) { + int rc = 0; + int timeout = 30000; + while (1) { + timeout--; + if (!timeout) { + msg_cerr("%s timeout during command execution\n", __func__); + return -1; + } + + /* First probe. */ + if (flash->chip->probe(flash) != 1) + continue; + + /* First operation. */ + if (rw_flag == 0) + rc = spi_nbyte_read(flash, startrw_here, buf1, torw_len); + else + rc = spi_nbyte_program(flash, startrw_here, buf1, torw_len); + + if (rc != 0) + break; + + /* Second probe. */ + if (flash->chip->probe(flash) != 1) + continue; + + /* Second operation. */ + rc = spi_nbyte_read(flash, startrw_here, buf2, torw_len); + if (rc != 0) + break; + + /* Compare two buffers. */ + if (memcmp(buf1, buf2, torw_len)) + continue; + + break; + } + return rc; +} + /* * Read a part of the flash chip. * FIXME: Use the chunk code from Michael Karcher instead. @@ -668,6 +711,19 @@ /* Limit for multi-die 4-byte-addressing chips. */ unsigned int area_size = min(flash->chip->total_size * 1024, 16 * 1024 * 1024); + unsigned int bruteforce = flashrom_flag_get(flash, FLASHROM_FLAG_BRUTEFORCE); + uint8_t *const buf1 = bruteforce ? malloc(chunksize) : NULL; + uint8_t *const buf2 = bruteforce ? malloc(chunksize) : NULL; + + if (bruteforce) { + if (!buf1 || !buf2) { + msg_gerr("Out of memory!\n"); + goto _free_ret; + } + msg_cdbg("spi_read_chunked: chunksize %i ---> %i\n", chunksize, min(chunksize, 256)); + chunksize = min(chunksize, 256); + } + /* Warning: This loop has a very unusual condition and body. * The loop needs to go through each area with at least one affected * byte. The lowest area number is (start / area_size) since that @@ -685,7 +741,11 @@ lenhere = min(start + len, (i + 1) * area_size) - starthere; for (j = 0; j < lenhere; j += chunksize) { toread = min(chunksize, lenhere - j); - rc = spi_nbyte_read(flash, starthere + j, buf + starthere - start + j, toread); + if (bruteforce) { + rc = spi_rw_bruteforce(flash, buf1, buf2, starthere + j, toread, 0 /* read */); + memcpy(buf + starthere - start + j, buf1, toread); + } else + rc = spi_nbyte_read(flash, starthere + j, buf + starthere - start + j, toread); if (rc) break; } @@ -693,6 +753,9 @@ break; } +_free_ret: + free(buf1); + free(buf2); return rc; } @@ -712,6 +775,19 @@ */ unsigned int page_size = flash->chip->page_size; + unsigned int bruteforce = flashrom_flag_get(flash, FLASHROM_FLAG_BRUTEFORCE); + uint8_t *const buf1 = bruteforce ? malloc(chunksize) : NULL; + uint8_t *const buf2 = bruteforce ? malloc(chunksize) : NULL; + + if (bruteforce) { + if (!buf1 || !buf2) { + msg_gerr("Out of memory!\n"); + goto _free_ret; + } + msg_cdbg("spi_write_chunked: chunksize %i ---> %i\n", chunksize, min(chunksize, 256)); + chunksize = min(chunksize, 256); + } + /* Warning: This loop has a very unusual condition and body. * The loop needs to go through each page with at least one affected * byte. The lowest page number is (start / page_size) since that @@ -731,12 +807,20 @@ int rc; towrite = min(chunksize, lenhere - j); - rc = spi_nbyte_program(flash, starthere + j, buf + starthere - start + j, towrite); + if (bruteforce) { + memcpy(buf1, buf + starthere - start + j, towrite); + rc = spi_rw_bruteforce(flash, buf1, buf2, starthere + j, towrite, 1 /* write */); + } else + rc = spi_nbyte_program(flash, starthere + j, buf + starthere - start + j, towrite); + if (rc) return rc; } } +_free_ret: + free(buf1); + free(buf2); return 0; } -- To view, visit https://review.coreboot.org/c/flashrom/+/31830 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: If47476793721a0061fd65bc6d1f98d48b03dc6c1 Gerrit-Change-Number: 31830 Gerrit-PatchSet: 1 Gerrit-Owner: mikeb mikeb <mikebdp2(a)gmail.com> Gerrit-Reviewer: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

3 6

Change in flashrom[master]: flashrom: Add support for ARC platform
by David Hendricks (Code Review) 14 Dec '19

14 Dec '19

David Hendricks has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/35831 ) Change subject: flashrom: Add support for ARC platform ...................................................................... flashrom: Add support for ARC platform Change-Id: I88cbe74b716d5fab16133fbf2ce9c35b74c25f32 Signed-off-by: Rosen Penev <rosenp(a)gmail.com> --- M Makefile M hwaccess.h M platform.h 3 files changed, 16 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/31/35831/1 diff --git a/Makefile b/Makefile index 7a21d12..cc9c444 100644 --- a/Makefile +++ b/Makefile @@ -453,7 +453,7 @@ # Disable all drivers needing raw access (memory, PCI, port I/O) on # architectures with unknown raw access properties. # Right now those architectures are alpha hppa m68k sh s390 -ifneq ($(ARCH),$(filter $(ARCH),x86 mips ppc arm sparc)) +ifneq ($(ARCH),$(filter $(ARCH),x86 mips ppc arm sparc arc)) ifeq ($(CONFIG_RAYER_SPI), yes) UNSUPPORTED_FEATURES += CONFIG_RAYER_SPI=yes else diff --git a/hwaccess.h b/hwaccess.h index af7054b..5602c15 100644 --- a/hwaccess.h +++ b/hwaccess.h @@ -291,6 +291,10 @@ /* Non memory mapped I/O is not supported on ARM. */ +#elif IS_ARC + +/* Non memory mapped I/O is not supported on ARC. */ + #else #error Unknown architecture, please check if it supports PCI port IO. diff --git a/platform.h b/platform.h index d290afc..195ba56 100644 --- a/platform.h +++ b/platform.h @@ -74,9 +74,12 @@ #elif defined(__s390__) || defined(__s390x__) || defined(__zarch__) #define __FLASHROM_ARCH__ "s390" #define IS_S390 1 +#elif defined(__arc__) + #define __FLASHROM_ARCH__ "arc" + #define IS_ARC 1 #endif -#if !(IS_X86 || IS_MIPS || IS_PPC || IS_ARM || IS_SPARC || IS_ALPHA || IS_HPPA || IS_M68K || IS_RISCV || IS_SH || IS_S390) +#if !(IS_X86 || IS_MIPS || IS_PPC || IS_ARM || IS_SPARC || IS_ALPHA || IS_HPPA || IS_M68K || IS_RISCV || IS_SH || IS_S390 || IS_ARC) #error Unknown architecture #endif @@ -123,6 +126,13 @@ /* SPARC is big endian in general (but allows to access data in little endian too). */ #define __FLASHROM_BIG_ENDIAN__ 1 +#elif IS_ARC +#if defined(__arceb__) +#define __FLASHROM_BIG_ENDIAN__ 1 +#else +#define __FLASHROM_LITTLE_ENDIAN__ 1 +#endif + #endif /* IS_? */ #if !defined (__FLASHROM_BIG_ENDIAN__) && !defined (__FLASHROM_LITTLE_ENDIAN__) -- To view, visit https://review.coreboot.org/c/flashrom/+/35831 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I88cbe74b716d5fab16133fbf2ce9c35b74c25f32 Gerrit-Change-Number: 35831 Gerrit-PatchSet: 1 Gerrit-Owner: David Hendricks <david.hendricks(a)gmail.com> Gerrit-MessageType: newchange

2 10

Change in ...flashrom[master]: nicintel_eeprom: Reduce usage of is_i210()
by Nico Huber (Code Review) 10 Dec '19

10 Dec '19

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/33637 Change subject: nicintel_eeprom: Reduce usage of is_i210() ...................................................................... nicintel_eeprom: Reduce usage of is_i210() Don't entagle the code paths for the two NIC classes if it's not necessary. Only compile tested. Change-Id: I59164ccf54afbbd64a0598282d13e80ff7fd6fa4 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M nicintel_eeprom.c 1 file changed, 52 insertions(+), 46 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/37/33637/1 diff --git a/nicintel_eeprom.c b/nicintel_eeprom.c index 4e01fcb..4d45f79 100644 --- a/nicintel_eeprom.c +++ b/nicintel_eeprom.c @@ -145,14 +145,6 @@ return 1; } -static int nicintel_ee_probe(struct flashctx *flash) -{ - if (is_i210(nicintel_pci->device_id)) - return nicintel_ee_probe_i210(flash); - - return nicintel_ee_probe_82580(flash); -} - #define MAX_ATTEMPTS 10000000 static int nicintel_ee_read_word(unsigned int addr, uint16_t *data) { @@ -281,6 +273,11 @@ return 0; } +static int nicintel_ee_erase_i210(struct flashctx *flash, unsigned int addr, unsigned int len) +{ + return nicintel_ee_write_i210(flash, NULL, addr, len); +} + static int nicintel_ee_bitset(int reg, int bit, bool val) { uint32_t tmp; @@ -392,24 +389,24 @@ nicintel_ee_bitset(EEC, EE_REQ, 0); /* Give up direct access. */ return ret; } -static int nicintel_ee_write(struct flashctx *flash, const uint8_t *buf, unsigned int addr, unsigned int len) -{ - if (is_i210(nicintel_pci->device_id)) - return nicintel_ee_write_i210(flash, buf, addr, len); - return nicintel_ee_write_82580(flash, buf, addr, len); +static int nicintel_ee_erase_82580(struct flashctx *flash, unsigned int addr, unsigned int len) +{ + return nicintel_ee_write_82580(flash, NULL, addr, len); } -static int nicintel_ee_erase(struct flashctx *flash, unsigned int addr, unsigned int len) -{ - return nicintel_ee_write(flash, NULL, addr, len); -} - -static const struct opaque_master opaque_master_nicintel_ee = { - .probe = nicintel_ee_probe, +static const struct opaque_master opaque_master_nicintel_ee_82580 = { + .probe = nicintel_ee_probe_82580, .read = nicintel_ee_read, - .write = nicintel_ee_write, - .erase = nicintel_ee_erase, + .write = nicintel_ee_write_82580, + .erase = nicintel_ee_erase_82580, +}; + +static const struct opaque_master opaque_master_nicintel_ee_i210 = { + .probe = nicintel_ee_probe_i210, + .read = nicintel_ee_read, + .write = nicintel_ee_write_i210, + .erase = nicintel_ee_erase_i210, }; static int nicintel_ee_shutdown_i210(void *arg) @@ -432,7 +429,7 @@ return -1; } -static int nicintel_ee_shutdown(void *eecp) +static int nicintel_ee_shutdown_82580(void *eecp) { uint32_t old_eec = *(uint32_t *)eecp; /* Request bitbanging and unselect the chip first to be safe. */ @@ -463,35 +460,44 @@ if (!io_base_addr) return 1; - nicintel_eebar = rphysmap("Intel Gigabit NIC w/ SPI EEPROM", - io_base_addr + (is_i210(dev->device_id) ? 0x12000 : 0), MEMMAP_SIZE); - if (!nicintel_eebar) - return 1; - - nicintel_pci = dev; - if ((dev->device_id != UNPROG_DEVICE) && ! is_i210(dev->device_id)) - { - uint32_t eec = pci_mmio_readl(nicintel_eebar + EEC); - - /* C.f. 3.3.1.5 for the detection mechanism (maybe? contradicting the EE_PRES definition), - * and 3.3.1.7 for possible recovery. */ - if (!(eec & BIT(EE_PRES))) { - msg_perr("Controller reports no EEPROM is present.\n"); + if (!is_i210(dev->device_id)) { + nicintel_eebar = rphysmap("Intel Gigabit NIC w/ SPI EEPROM", io_base_addr, MEMMAP_SIZE); + if (!nicintel_eebar) return 1; + + nicintel_pci = dev; + if ((dev->device_id != UNPROG_DEVICE)) { + uint32_t eec = pci_mmio_readl(nicintel_eebar + EEC); + + /* C.f. 3.3.1.5 for the detection mechanism (maybe? contradicting + the EE_PRES definition), + and 3.3.1.7 for possible recovery. */ + if (!(eec & BIT(EE_PRES))) { + msg_perr("Controller reports no EEPROM is present.\n"); + return 1; + } + + uint32_t *eecp = malloc(sizeof(uint32_t)); + if (eecp == NULL) + return 1; + *eecp = eec; + + if (register_shutdown(nicintel_ee_shutdown_82580, eecp)) + return 1; } - uint32_t *eecp = malloc(sizeof(uint32_t)); - if (eecp == NULL) + return register_opaque_master(&opaque_master_nicintel_ee_82580); + } else { + nicintel_eebar = rphysmap("Intel i210 NIC w/ emulated EEPROM", + io_base_addr + 0x12000, MEMMAP_SIZE); + if (!nicintel_eebar) return 1; - *eecp = eec; - if (register_shutdown(nicintel_ee_shutdown, eecp)) - return 1; - } - - if (is_i210(dev->device_id)) if (register_shutdown(nicintel_ee_shutdown_i210, NULL)) return 1; - return register_opaque_master(&opaque_master_nicintel_ee); + return register_opaque_master(&opaque_master_nicintel_ee_i210); + } + + return 1; } -- To view, visit https://review.coreboot.org/c/flashrom/+/33637 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I59164ccf54afbbd64a0598282d13e80ff7fd6fa4 Gerrit-Change-Number: 33637 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

3 4

Change in ...flashrom[master]: Implement IFWI layout reading
by Nico Huber (Code Review) 02 Dec '19

02 Dec '19

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/31018 Change subject: Implement IFWI layout reading ...................................................................... Implement IFWI layout reading Alas, yet another conflicting command-line option before we overhaul the internal layout handling. Change-Id: I1f1ef4c5d109b81dec7a11bca04ba89204fa84eb Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M Makefile M cli_classic.c A ifwi.c M libflashrom.c M libflashrom.h 5 files changed, 463 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/18/31018/1 diff --git a/Makefile b/Makefile index 1e7db3e..4a1094d 100644 --- a/Makefile +++ b/Makefile @@ -536,7 +536,7 @@ ############################################################################### # Library code. -LIB_OBJS = libflashrom.o layout.o flashrom.o udelay.o programmer.o helpers.o ich_descriptors.o fmap.o +LIB_OBJS = libflashrom.o layout.o flashrom.o udelay.o programmer.o helpers.o ich_descriptors.o fmap.o ifwi.o ############################################################################### # Frontend related stuff. diff --git a/cli_classic.c b/cli_classic.c index 536ef24..f764a6d 100644 --- a/cli_classic.c +++ b/cli_classic.c @@ -57,6 +57,7 @@ " --fmap read ROM layout from fmap embedded in ROM\n" " --fmap-file <fmapfile> read ROM layout from fmap in <fmapfile>\n" " --ifd read layout from an Intel Firmware Descriptor\n" + " --ifwi read layout from an Integrated Firmware Image\n" " -i | --image <name> only flash image <name> from flash layout\n" " -o | --output <logfile> log output to <logfile>\n" " --flash-contents <ref-file> assume flash contents to be <ref-file>\n" @@ -100,7 +101,7 @@ struct flashctx *fill_flash; const char *name; int namelen, opt, i, j; - int startchip = -1, chipcount = 0, option_index = 0, force = 0, ifd = 0, fmap = 0; + int startchip = -1, chipcount = 0, option_index = 0, force = 0, ifd = 0, ifwi = 0, fmap = 0; #if CONFIG_PRINT_WIKI == 1 int list_supported_wiki = 0; #endif @@ -110,6 +111,7 @@ enum programmer prog = PROGRAMMER_INVALID; enum { OPTION_IFD = 0x0100, + OPTION_IFWI, OPTION_FMAP, OPTION_FMAP_FILE, OPTION_FLASH_CONTENTS, @@ -129,6 +131,7 @@ {"force", 0, NULL, 'f'}, {"layout", 1, NULL, 'l'}, {"ifd", 0, NULL, OPTION_IFD}, + {"ifwi", 0, NULL, OPTION_IFWI}, {"fmap", 0, NULL, OPTION_FMAP}, {"fmap-file", 1, NULL, OPTION_FMAP_FILE}, {"image", 1, NULL, 'i'}, @@ -238,6 +241,10 @@ fprintf(stderr, "Error: --layout and --ifd both specified. Aborting.\n"); cli_classic_abort_usage(); } + if (ifwi) { + fprintf(stderr, "Error: --layout and --ifwi both specified. Aborting.\n"); + cli_classic_abort_usage(); + } if (fmap) { fprintf(stderr, "Error: --layout and --fmap-file both specified. Aborting.\n"); cli_classic_abort_usage(); @@ -249,12 +256,31 @@ fprintf(stderr, "Error: --layout and --ifd both specified. Aborting.\n"); cli_classic_abort_usage(); } + if (ifwi) { + fprintf(stderr, "Error: --ifwi and --ifd both specified. Aborting.\n"); + cli_classic_abort_usage(); + } if (fmap) { fprintf(stderr, "Error: --fmap-file and --ifd both specified. Aborting.\n"); cli_classic_abort_usage(); } ifd = 1; break; + case OPTION_IFWI: + if (layoutfile) { + fprintf(stderr, "Error: --layout and --ifwi both specified. Aborting.\n"); + cli_classic_abort_usage(); + } + if (ifd) { + fprintf(stderr, "Error: --ifd and --ifwi both specified. Aborting.\n"); + cli_classic_abort_usage(); + } + if (fmap) { + fprintf(stderr, "Error: --fmap-file and --ifwi both specified. Aborting.\n"); + cli_classic_abort_usage(); + } + ifwi = 1; + break; case OPTION_FMAP_FILE: if (fmap) { fprintf(stderr, "Error: --fmap or --fmap-file specified " @@ -265,6 +291,10 @@ fprintf(stderr, "Error: --fmap-file and --ifd both specified. Aborting.\n"); cli_classic_abort_usage(); } + if (ifwi) { + fprintf(stderr, "Error: --fmap-file and --ifwi both specified. Aborting.\n"); + cli_classic_abort_usage(); + } if (layoutfile) { fprintf(stderr, "Error: --fmap-file and --layout both specified. Aborting.\n"); cli_classic_abort_usage(); @@ -282,6 +312,10 @@ fprintf(stderr, "Error: --fmap and --ifd both specified. Aborting.\n"); cli_classic_abort_usage(); } + if (ifwi) { + fprintf(stderr, "Error: --fmap and --ifwi both specified. Aborting.\n"); + cli_classic_abort_usage(); + } if (layoutfile) { fprintf(stderr, "Error: --layout and --fmap both specified. Aborting.\n"); cli_classic_abort_usage(); @@ -452,7 +486,7 @@ goto out; } - if (!ifd && !fmap && process_include_args(get_global_layout())) { + if (!ifd && !ifwi && !fmap && process_include_args(get_global_layout())) { ret = 1; goto out; } @@ -611,6 +645,10 @@ process_include_args(layout))) { ret = 1; goto out_shutdown; + } else if (ifwi && (flashrom_layout_read_from_ifwi(&layout, fill_flash) || + process_include_args(layout))) { + ret = 1; + goto out_shutdown; } else if (fmap && fmapfile) { struct stat s; if (stat(fmapfile, &s) != 0) { diff --git a/ifwi.c b/ifwi.c new file mode 100644 index 0000000..320335a --- /dev/null +++ b/ifwi.c @@ -0,0 +1,359 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2019 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdio.h> +#include <stddef.h> +#include <stdint.h> +#include <inttypes.h> +#include <stdbool.h> +#include <stdlib.h> +#include <string.h> + +#include "hwaccess.h" +#include "layout.h" +#include "flash.h" +#include "ifwi.h" + +static size_t bpdt_size(const struct bpdt *const header) +{ + return BPDT_HEADER_LENGTH + header->desc_count * BPDT_ENTRY_LENGTH; +} + +static int deserialize_bpdt_header(struct bpdt *const header, const uint8_t *const from) +{ + header->signature = read_le32(from + 0); + header->desc_count = read_le16(from + 4); + header->version = read_le16(from + 6); + header->xorsum = read_le32(from + 8); + header->ifwi_version = read_le32(from + 12); + + if (header->signature != BPDT_SIGNATURE) { + msg_gerr("IFWI: BPDT signature mismatch. Found 0x%08"PRIx32", expected 0x%08x.\n", + header->signature, BPDT_SIGNATURE); + return -4; + } + if (header->version != 1) { + msg_gerr("IFWI: Unknown BPDT version: %"PRIu32".\n", header->version); + return -3; + } + return 0; +} + +static int deserialize_bpdt_entries(struct bpdt *const bpdt, const uint8_t *const from, const size_t limit) +{ + unsigned int i; + size_t offset; + + for (i = 0, offset = 0; i < bpdt->desc_count; ++i, offset += BPDT_ENTRY_LENGTH) { + bpdt->entries[i].type = read_le16(from + offset + 0); + bpdt->entries[i].flags = read_le16(from + offset + 2); + bpdt->entries[i].offset = read_le32(from + offset + 4); + bpdt->entries[i].size = read_le32(from + offset + 8); + msg_gdbg("IFWI: BPDT entry #%u (0x%04"PRIx16", 0x%04"PRIx16", 0x%08"PRIx32", 0x%08"PRIx32")\n", + i, bpdt->entries[i].type, bpdt->entries[i].flags, + bpdt->entries[i].offset, bpdt->entries[i].size); + + const uint32_t end = bpdt->entries[i].offset + bpdt->entries[i].size; + if (end < bpdt->entries[i].offset) { + msg_gerr("IFWI: BPDT entry overflows 32-bit space; " + "offset 0x%08"PRIx32" size 0x%08"PRIx32"\n", + bpdt->entries[i].offset, bpdt->entries[i].size); + return -4; + } + if (end > limit) { + msg_gerr("IFWI: BPDT entry points outside of the partition: %08"PRIx32":%08"PRIx32"\n", + bpdt->entries[i].offset, end - 1); + return -4; + } + } + return (int)i; +} + +static int read_bpdt(struct bpdt **bpdt, + const size_t flash_offset, const size_t partition_limit, + int (*const read)(void *args, uint8_t *buf, unsigned int start, unsigned int len), + void *const read_args) +{ + uint8_t *buf; + int ret; + + buf = malloc(BPDT_HEADER_LENGTH); + *bpdt = malloc(sizeof(**bpdt)); + if (!buf || !*bpdt) { + msg_gerr("Out of memory!\n"); + ret = -1; + goto _free_bpdt_ret; + } + + if (read(read_args, buf, flash_offset, BPDT_HEADER_LENGTH)) { + ret = -2; + goto _free_bpdt_ret; + } + ret = deserialize_bpdt_header(*bpdt, buf); + if (ret < 0) + goto _free_bpdt_ret; + + buf = realloc_or_free(buf, bpdt_size(*bpdt)); + *bpdt = realloc_or_free(*bpdt, offsetof(struct bpdt, entries) + + (*bpdt)->desc_count * sizeof((*bpdt)->entries[0])); + if (!buf || !*bpdt) { + ret = -1; + goto _free_bpdt_ret; + } + + if (read(read_args, buf + BPDT_HEADER_LENGTH, + flash_offset + BPDT_HEADER_LENGTH, bpdt_size(*bpdt) - BPDT_HEADER_LENGTH)) { + ret = -2; + goto _free_bpdt_ret; + } + ret = deserialize_bpdt_entries(*bpdt, (uint8_t *)buf + BPDT_HEADER_LENGTH, partition_limit); + if (ret < 0) + goto _free_bpdt_ret; + + ret = 0; + goto _free_buf_ret; + +_free_bpdt_ret: + free(*bpdt); +_free_buf_ret: + free(buf); + return ret; +} + +static size_t spd_size(const struct spd *const header) +{ + return header->header_length + header->num_entries * SPD_ENTRY_LENGTH; +} + +static int deserialize_spd_header(struct spd *const header, const uint8_t *const from) +{ + header->marker = read_le32(from + 0); + header->num_entries = read_le32(from + 4); + header->header_version = read_le8 (from + 8); + header->entry_version = read_le8 (from + 9); + header->header_length = read_le8 (from + 10); + header->checksum = read_le8 (from + 11); + memcpy(header->name, from + 12, sizeof(header->name) - 1); + header->name[sizeof(header->name) - 1] = '\0'; + + if (header->marker != SPD_MARKER) { + msg_gerr("IFWI: SPD marker mismatch. Found 0x%08"PRIx32", expected 0x%08x.\n", + header->marker, SPD_MARKER); + return -4; + } + if (header->header_version != 1) { + msg_gerr("IFWI: Unknown SPD header version: %"PRIu8".\n", header->header_version); + return -3; + } + if (header->entry_version != 1) { + msg_gerr("IFWI: Unknown SPD entry version: %"PRIu8".\n", header->entry_version); + return -3; + } + return 0; +} + +static int deserialize_spd_entries(struct spd *const spd, const uint8_t *const from, const size_t limit) +{ + unsigned int i; + size_t offset; + + for (i = 0, offset = 0; i < spd->num_entries; ++i, offset += SPD_ENTRY_LENGTH) { + memcpy(spd->entries[i].name, from + offset, sizeof(spd->entries[i].name) - 1); + spd->entries[i].name[sizeof(spd->entries[i].name) - 1] = '\0'; + spd->entries[i].offset = read_le32(from + offset + 12); + spd->entries[i].length = read_le32(from + offset + 16); + msg_gdbg("IFWI: SPD entry #%u (%s, 0x%08"PRIx32", 0x%08"PRIx32")\n", + i, spd->entries[i].name, spd->entries[i].offset, spd->entries[i].length); + + const uint32_t end = spd->entries[i].offset + spd->entries[i].length; + if (end < spd->entries[i].offset) { + msg_gerr("IFWI: SPD entry overflows 32-bit space; " + "offset 0x%08"PRIx32" size 0x%08"PRIx32"\n", + spd->entries[i].offset, spd->entries[i].length); + return -4; + } + if (end > limit) { + msg_gerr("IFWI: SPD entry points outside of the partition: %08"PRIx32":%08"PRIx32"\n", + spd->entries[i].offset, end - 1); + return -4; + } + } + return (int)i; +} + +static int read_spd(struct spd **spd, + const size_t flash_offset, const size_t partition_limit, + int (*const read)(void *args, uint8_t *buf, unsigned int start, unsigned int len), + void *const read_args) +{ + uint8_t *buf; + int ret; + + buf = malloc(SPD_MIN_HEADER_LENGTH); + *spd = malloc(sizeof(**spd)); + if (!buf || !*spd) { + msg_gerr("Out of memory!\n"); + ret = -1; + goto _free_spd_ret; + } + + if (read(read_args, buf, flash_offset, SPD_MIN_HEADER_LENGTH)) { + ret = -2; + goto _free_spd_ret; + } + ret = deserialize_spd_header(*spd, (uint8_t *)buf); + if (ret < 0) + goto _free_spd_ret; + + buf = realloc_or_free(buf, spd_size(*spd)); + *spd = realloc_or_free(*spd, offsetof(struct spd, entries) + + (*spd)->num_entries * sizeof((*spd)->entries[0])); + if (!buf || !*spd) { + ret = -1; + goto _free_spd_ret; + } + + if (read(read_args, buf + (*spd)->header_length, + flash_offset + (*spd)->header_length, spd_size(*spd) - (*spd)->header_length)) { + ret = -2; + goto _free_spd_ret; + } + ret = deserialize_spd_entries(*spd, (uint8_t *)buf + (*spd)->header_length, partition_limit); + if (ret < 0) + goto _free_spd_ret; + + ret = 0; + goto _free_buf_ret; + +_free_spd_ret: + free(*spd); +_free_buf_ret: + free(buf); + return ret; +} + +static int layout_from_ifwi(struct flashrom_layout **const layout, + const size_t primary_offset, const size_t secondary_offset, + const size_t partition_limit, + int (*const read)(void *args, uint8_t *buf, unsigned int start, unsigned int len), + void *const read_args) +{ + struct bpdt *bpdt; + struct spd *spd; + size_t bpdt_offset, offset; + unsigned int i, j; + int ret = -1; + + if (!secondary_offset) + bpdt_offset = primary_offset; + else + bpdt_offset = secondary_offset; + + ret = read_bpdt(&bpdt, bpdt_offset, partition_limit - primary_offset, read, read_args); + if (ret < 0) + return ret; + + if (!secondary_offset && !(*layout = new_layout(32))) { + ret = -1; + goto _free_bpdt_ret; + } + + ret = add_layout_entry(layout, secondary_offset ? "S-BPDT" : "BPDT", + bpdt_offset, bpdt_offset + bpdt_size(bpdt) - 1); + if (ret < 0) + goto _free_layout_ret; + + for (i = 0; i < bpdt->desc_count; ++i) { + offset = primary_offset + bpdt->entries[i].offset; + + if (!bpdt->entries[i].offset || !bpdt->entries[i].size) { + msg_gdbg("IFWI: Skipping empty BPDT entry #%u of type %"PRIu16".\n", + i, bpdt->entries[i].type); + continue; + } + + switch (bpdt->entries[i].type) { + case 5: + /* recurse into secondary BPDT */ + ret = layout_from_ifwi(layout, primary_offset, offset, + partition_limit, read, read_args); + if (ret) + goto _free_layout_ret; + continue; + case 0: /* Fall through.*/ + case 1: /* Fall through.*/ + case 2: /* Fall through.*/ + case 3: /* Fall through.*/ + case 4: /* Fall through.*/ + case 6: /* Fall through.*/ + case 7: /* Fall through.*/ + case 8: /* Fall through.*/ + case 9: /* Fall through.*/ + case 14: /* Fall through.*/ + case 15: + break; + default: + continue; + } + + ret = read_spd(&spd, offset, partition_limit - offset, read, read_args); + switch (ret) { + case 0: + break; + case -1: /* Fall through. */ + case -2: + goto _free_layout_ret; + default: + continue; + } + + ret = add_layout_entry(layout, spd->name, offset, offset + bpdt->entries[i].size - 1); + if (ret < 0) { + free(spd); + goto _free_layout_ret; + } + for (j = 0; j < spd->num_entries; ++j) { + offset = primary_offset + bpdt->entries[i].offset + + (spd->entries[j].offset & SPD_ENTRY_OFFSET_MASK); + ret = add_layout_entry( + layout, spd->entries[j].name, + offset, offset + spd->entries[j].length - 1); + if (ret < 0) { + free(spd); + goto _free_layout_ret; + } + } + free(spd); + } + + ret = 0; + goto _free_bpdt_ret; + +_free_layout_ret: + free(*layout); +_free_bpdt_ret: + free(bpdt); + return ret; +} + +int layout_from_ifwi_rom(struct flashrom_layout **const layout, + struct flashrom_flashctx *const flashctx, + const size_t flash_offset) +{ + return layout_from_ifwi(layout, flash_offset, 0, flashctx->chip->total_size * 1024, + (int (*)(void *, uint8_t *, unsigned int, unsigned int))flashctx->chip->read, + flashctx); +} diff --git a/libflashrom.c b/libflashrom.c index f90a22c..96e34cc 100644 --- a/libflashrom.c +++ b/libflashrom.c @@ -30,6 +30,7 @@ #include "layout.h" #include "hwaccess.h" #include "ich_descriptors.h" +#include "ifwi.h" #include "libflashrom.h" /** @@ -383,6 +384,67 @@ #endif } +/** + * @brief Read a layout from the Intel IFWI in the flash. + * + * @param[out] layout Points to a struct flashrom_layout pointer that + * gets set if the descriptor is read and parsed + * successfully. + * @param[in] flashctx Flash context to read the descriptor from flash. + * + * @return 0 on success, + * 6 if descriptor parsing isn't implemented for the host, + * 3 if the data on flash couldn't be parsed, + * 2 if the data on flash couldn't be read, + * 1 on any other error. + */ +int flashrom_layout_read_from_ifwi(struct flashrom_layout **const layout, + struct flashrom_flashctx *const flashctx) +{ + struct flashrom_layout *ifd_layout; + unsigned int i; + int ret; + + ret = flashrom_layout_read_from_ifd(&ifd_layout, flashctx, NULL, 0); + if (ret) + return ret; + + for (i = 0; i < ifd_layout->num_entries; ++i) { + if (strcmp(ifd_layout->entries[i].name, "bios") == 0) + break; + } + if (i >= ifd_layout->num_entries) { + msg_gerr("Cannot find BIOS region in Intel Firmware Descriptor (IFD).\n"); + ret = 3; + goto _free_ifd_ret; + } + + msg_cinfo("Reading IFWI layout... "); + ret = layout_from_ifwi_rom(layout, flashctx, ifd_layout->entries[i].start); + switch (ret) { + case -4: /* Fall through. */ + case -3: + ret = 3; + break; + case -2: + ret = 2; + break; + case 0: + break; + default: + ret = 1; + break; + } + if (ret) + msg_cinfo("FAILED.\n"); + else + msg_cinfo("done.\n"); + +_free_ifd_ret: + free(ifd_layout); + return ret; +} + static int flashrom_layout_parse_fmap(struct flashrom_layout **layout, struct flashctx *const flashctx, const struct fmap *const fmap) { diff --git a/libflashrom.h b/libflashrom.h index 38c95d2..9ca7ea0 100644 --- a/libflashrom.h +++ b/libflashrom.h @@ -63,6 +63,7 @@ struct flashrom_layout; int flashrom_layout_read_from_ifd(struct flashrom_layout **, struct flashrom_flashctx *, const void *dump, size_t len); +int flashrom_layout_read_from_ifwi(struct flashrom_layout **, struct flashrom_flashctx *); int flashrom_layout_read_fmap_from_rom(struct flashrom_layout **, struct flashrom_flashctx *, off_t offset, size_t length); int flashrom_layout_read_fmap_from_buffer(struct flashrom_layout **layout, -- To view, visit https://review.coreboot.org/c/flashrom/+/31018 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I1f1ef4c5d109b81dec7a11bca04ba89204fa84eb Gerrit-Change-Number: 31018 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

3 6

Change in ...flashrom[master]: ifwi: Add definitions for the Integrated Firmware Image format
by Nico Huber (Code Review) 02 Dec '19

02 Dec '19

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/31017 Change subject: ifwi: Add definitions for the Integrated Firmware Image format ...................................................................... ifwi: Add definitions for the Integrated Firmware Image format The Integrated Firmware Image (IFWI) is used as a partitioning format on some Intel SoCs (e.g. Apollo Lake). It is not tied to NOR flashes, rather to have a common format between different types of boot media. Change-Id: I4bdf47637bfb68560e6d4269f89710572c1bb82a Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- A ifwi.h 1 file changed, 80 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/17/31017/1 diff --git a/ifwi.h b/ifwi.h new file mode 100644 index 0000000..622fccf --- /dev/null +++ b/ifwi.h @@ -0,0 +1,80 @@ +/* + * This file is part of the flashrom project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * The Integrated Firmware Image (IFWI) is used as a partitioning + * format on some Intel SoCs (e.g. Apollo Lake). It is not tied to + * NOR flashes, rather to have a common format between different + * types of boot media. + */ + +#ifndef __IFWI_H__ +#define __IFWI_H__ 1 + +#include <stdint.h> + +#include "layout.h" + +int layout_from_ifwi_rom(struct flashrom_layout **, struct flashrom_flashctx *, const size_t flash_offset); + +/*********** Boot Partition Descriptor Table (BPDT) ***********/ + +#define BPDT_ENTRY_LENGTH 12 + +struct bpdt_entry { /* points to a Sub-Partition */ + uint16_t type; + uint16_t flags; + uint32_t offset; /* from start of Logical Boot Partition */ + uint32_t size; +}; + +#define BPDT_SIGNATURE 0x000055aa +#define BPDT_HEADER_LENGTH 24 + +struct bpdt { + uint32_t signature; + uint16_t desc_count; + uint16_t version; + uint32_t xorsum; /* covers BPDT to S-BPDT (inclusive), iff there is + a redundant Logical Boot Partition, otherwise 0 */ + uint32_t ifwi_version; /* revision of this IFWI build */ + struct bpdt_entry entries[]; +}; + +/**************** Sub-Partition Directory (SPD) ***************/ + +#define SPD_ENTRY_OFFSET_MASK 0x01ffffff +#define SPD_ENTRY_LENGTH 24 + +struct spd_entry { + char name[12 + 1]; /* serialized as 12 chars w/o terminator */ + uint32_t offset; /* from start of the SPD header */ + uint32_t length; +}; + +#define SPD_MARKER 0x44504324 /* $CPD */ +#define SPD_MIN_HEADER_LENGTH 16 + +struct spd { + uint32_t marker; + uint32_t num_entries; + uint8_t header_version; + uint8_t entry_version; + uint8_t header_length; + uint8_t checksum; /* xor-sum covering header + entries */ + char name[4 + 1]; /* serialized as 4 chars w/o terminator */ + struct spd_entry entries[]; +}; + +#endif /* __IFWI_H__ */ -- To view, visit https://review.coreboot.org/c/flashrom/+/31017 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I4bdf47637bfb68560e6d4269f89710572c1bb82a Gerrit-Change-Number: 31017 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

5 8

2024

2023

2022

2021

2020

2019

2018

2017

flashrom-gerrit October 2019