October 2019 - flashrom-gerrit

Change in ...flashrom[master]: manibuilder: Add list of tags used for the 1.1.x branch
by Nico Huber (Code Review) March 16, 2021

March 16, 2021

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/33340 Change subject: manibuilder: Add list of tags used for the 1.1.x branch ...................................................................... manibuilder: Add list of tags used for the 1.1.x branch Change-Id: I243aa11f4a017a4209efcc227cec56eb12020e28 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M util/manibuilder/Makefile.targets 1 file changed, 48 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/40/33340/1 diff --git a/util/manibuilder/Makefile.targets b/util/manibuilder/Makefile.targets index 044b0a4..079c181 100644 --- a/util/manibuilder/Makefile.targets +++ b/util/manibuilder/Makefile.targets @@ -112,6 +112,46 @@ # can only run what is still maintained 10X_TAGS := $(filter $(10X_TAGS),$(ALL_TAGS)) +# original 1.1.x tags +11X_TAGS := \ + anita\:amd64 \ + djgpp\:6.1.0 \ + fedora\:25-x86_64 \ + fedora\:25-ppc64le \ + fedora\:25-aarch64 \ + fedora\:24-x86_64 \ + centos\:7.3-aarch64-clean \ + centos\:7.3-amd64-clean \ + centos\:7.2-amd64-clean \ + debian-debootstrap\:ppc64el-stretch \ + debian-debootstrap\:armhf-stretch \ + debian-debootstrap\:mips-stretch \ + debian-debootstrap\:mipsel-stretch \ + debian-debootstrap\:amd64-stretch \ + debian-debootstrap\:i386-stretch \ + debian-debootstrap\:amd64-sid \ + ubuntu-debootstrap\:arm64-xenial \ + ubuntu-debootstrap\:amd64-xenial \ + ubuntu-debootstrap\:powerpc-xenial \ + ubuntu-debootstrap\:amd64-bionic \ + alpine\:amd64-v3.7 \ + alpine\:amd64-v3.8 \ + alpine\:amd64-v3.6 \ + alpine\:armhf-v3.8 \ + alpine\:i386-v3.6 \ + alpine\:i386-v3.7 \ + alpine\:i386-v3.8 \ + debian-debootstrap\:amd64-buster \ + debian-debootstrap\:i386-buster \ + debian-debootstrap\:i386-sid \ + ubuntu-debootstrap\:armhf-xenial \ + ubuntu-debootstrap\:i386-bionic \ + ubuntu-debootstrap\:i386-xenial \ + ubuntu-debootstrap\:ppc64el-xenial \ + +# can only run what is still maintained +11X_TAGS := $(filter $(11X_TAGS),$(ALL_TAGS)) + default: $(DEFAULT_TAGS) native: $(NATIVE_TAGS) @@ -121,6 +161,9 @@ 1.0.x: export TEST_REVISION=refs/heads/1.0.x 1.0.x: $(10X_TAGS) +1.1.x: export TEST_REVISION=refs/heads/1.1.x +1.1.x: $(11X_TAGS) + show-default: @printf "%s\n" $(DEFAULT_TAGS) @@ -133,6 +176,9 @@ show-1.0.x: @printf "%s\n" $(10X_TAGS) -.PHONY: default native all 1.0.x -.PHONY: show-default show-native show-all show-1.0.x +show-1.1.x: + @printf "%s\n" $(11X_TAGS) + +.PHONY: default native all 1.0.x 1.1.x +.PHONY: show-default show-native show-all show-1.0.x show-1.1.x .PHONY: $(ALL_TAGS) -- To view, visit https://review.coreboot.org/c/flashrom/+/33340 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I243aa11f4a017a4209efcc227cec56eb12020e28 Gerrit-Change-Number: 33340 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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Change in ...flashrom[master]: manibuilder: Add newer targets for Alpine, CentOS, Fedora
by Nico Huber (Code Review) March 16, 2021

March 16, 2021

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/33342 Change subject: manibuilder: Add newer targets for Alpine, CentOS, Fedora ...................................................................... manibuilder: Add newer targets for Alpine, CentOS, Fedora Change-Id: I6c9939601abd3bd67424b8fa9a5ec800e50e3a51 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M util/manibuilder/Makefile.targets 1 file changed, 8 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/42/33342/1 diff --git a/util/manibuilder/Makefile.targets b/util/manibuilder/Makefile.targets index 044b0a4..f5a142c 100644 --- a/util/manibuilder/Makefile.targets +++ b/util/manibuilder/Makefile.targets @@ -1,8 +1,12 @@ ANITA_TAGS := anita\:amd64 anita\:i386 MULTIARCH_TAGS := \ + centos\:7.6-armhfp-clean centos\:7.6-amd64-clean \ centos\:7.3-aarch64-clean centos\:7.3-amd64-clean \ centos\:7.2-amd64-clean \ + $(foreach a,x86_64 s390x aarch64, fedora\:30-$(a)) \ + $(foreach a,x86_64 s390x ppc64le aarch64, fedora\:29-$(a)) \ + fedora\:28-armhfp \ $(foreach a,x86_64 ppc64le aarch64, \ $(foreach v,25 24, \ fedora\:$(v)-$(a))) \ @@ -14,7 +18,7 @@ ubuntu-debootstrap\:$(a)-$(v))) \ ubuntu-debootstrap\:powerpc-xenial \ $(foreach a,aarch64 armhf amd64 i386, \ - $(foreach v,v3.8 v3.7 v3.6, \ + $(foreach v,v3.9 v3.8 v3.7 v3.6, \ alpine\:$(a)-$(v))) \ OTHER_TAGS := djgpp\:6.1.0 @@ -41,6 +45,7 @@ DEFAULT_TAGS := \ anita\:amd64 \ djgpp\:6.1.0 \ + fedora\:30-aarch64 \ fedora\:25-x86_64 \ fedora\:25-ppc64le \ fedora\:25-aarch64 \ @@ -59,8 +64,9 @@ ubuntu-debootstrap\:amd64-xenial \ ubuntu-debootstrap\:powerpc-xenial \ ubuntu-debootstrap\:amd64-bionic \ - alpine\:amd64-v3.7 \ + alpine\:aarch64-v3.9 \ alpine\:amd64-v3.8 \ + alpine\:amd64-v3.7 \ # also run all native tests by default DEFAULT_TAGS += $(filter-out $(DEFAULT_TAGS),$(NATIVE_TAGS)) -- To view, visit https://review.coreboot.org/c/flashrom/+/33342 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I6c9939601abd3bd67424b8fa9a5ec800e50e3a51 Gerrit-Change-Number: 33342 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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Change in ...flashrom[master]: manibuilder: Allow warnings in NetBSD and CentOS builds
by Nico Huber (Code Review) March 16, 2021

March 16, 2021

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/33339 Change subject: manibuilder: Allow warnings in NetBSD and CentOS builds ...................................................................... manibuilder: Allow warnings in NetBSD and CentOS builds Their old compilers stumble because of `-Wmissing-braces`. Change-Id: Ia9ee17fd1f0c8b191091f89ffbf44329c6521d7d Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M util/manibuilder/Makefile 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/39/33339/1 diff --git a/util/manibuilder/Makefile b/util/manibuilder/Makefile index d93abec..7f76c33 100644 --- a/util/manibuilder/Makefile +++ b/util/manibuilder/Makefile @@ -53,9 +53,10 @@ djgpp\:6.1.0: LIBS_BASE=../ djgpp\:6.1.0: MAKEARGS+=strip CONFIG_JLINK_SPI=no $(ANITA_TAGS): MAKECMD=gmake -$(ANITA_TAGS): MAKEARGS+=CONFIG_JLINK_SPI=no +$(ANITA_TAGS): MAKEARGS+=CONFIG_JLINK_SPI=no WARNERROR=no $(filter alpine% centos%,$(MULTIARCH_TAGS)): MAKEARGS+=CONFIG_JLINK_SPI=no $(filter %-xenial %-stretch,$(MULTIARCH_TAGS)): MAKEARGS+=CONFIG_JLINK_SPI=no +$(filter centos%,$(MULTIARCH_TAGS)): MAKEARGS+=WARNERROR=no $(ALL_TAGS): export QUIET_SETUP=$(QUIET_TEST) $(ALL_TAGS): %: %-check-build $(QUIET_TEST)docker rm -f mani_$(call ident,$*) >/dev/null 2>&1 || true -- To view, visit https://review.coreboot.org/c/flashrom/+/33339 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ia9ee17fd1f0c8b191091f89ffbf44329c6521d7d Gerrit-Change-Number: 33339 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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Change in ...flashrom[master]: manibuilder: Add libjaylink where possible, disable where not
by Nico Huber (Code Review) March 16, 2021

March 16, 2021

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/33338 Change subject: manibuilder: Add libjaylink where possible, disable where not ...................................................................... manibuilder: Add libjaylink where possible, disable where not Change-Id: I2f7aebe602ebdb0a4748640e281b9a92146f0ca8 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M util/manibuilder/Dockerfile.debian-debootstrap M util/manibuilder/Dockerfile.fedora M util/manibuilder/Dockerfile.ubuntu-debootstrap M util/manibuilder/Makefile 4 files changed, 10 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/38/33338/1 diff --git a/util/manibuilder/Dockerfile.debian-debootstrap b/util/manibuilder/Dockerfile.debian-debootstrap index c6648e8..ce201f8 100644 --- a/util/manibuilder/Dockerfile.debian-debootstrap +++ b/util/manibuilder/Dockerfile.debian-debootstrap @@ -5,8 +5,9 @@ apt-get -qq update && \ apt-get -qq upgrade && \ apt-get -qq dist-upgrade && \ - apt-get -qqy install gcc make git doxygen ccache \ + apt-get -qqy install gcc make git doxygen ccache pkg-config \ libpci-dev libusb-dev libftdi-dev libusb-1.0-0-dev && \ + { apt-get -qqy install libjaylink-dev || true; } && \ apt-get clean USER mani diff --git a/util/manibuilder/Dockerfile.fedora b/util/manibuilder/Dockerfile.fedora index 927e487..319039b 100644 --- a/util/manibuilder/Dockerfile.fedora +++ b/util/manibuilder/Dockerfile.fedora @@ -3,7 +3,8 @@ RUN \ useradd -p locked -m mani && \ dnf install -q -y git gcc ccache make \ - pciutils-devel libusb-devel libusbx-devel libftdi-devel && \ + pciutils-devel libusb-devel libusbx-devel libftdi-devel \ + libjaylink-devel && \ dnf clean -q -y all USER mani diff --git a/util/manibuilder/Dockerfile.ubuntu-debootstrap b/util/manibuilder/Dockerfile.ubuntu-debootstrap index f50047c..fe3ad1e 100644 --- a/util/manibuilder/Dockerfile.ubuntu-debootstrap +++ b/util/manibuilder/Dockerfile.ubuntu-debootstrap @@ -18,8 +18,9 @@ apt-get -qq update && \ apt-get -qq upgrade && \ apt-get -qq dist-upgrade && \ - apt-get -qqy install gcc make git doxygen ccache \ + apt-get -qqy install gcc make git doxygen ccache pkg-config \ libpci-dev libusb-dev libftdi-dev libusb-1.0-0-dev && \ + { apt-get -qqy install libjaylink-dev || true; } && \ apt-get clean USER mani diff --git a/util/manibuilder/Makefile b/util/manibuilder/Makefile index 9b87f45..d93abec 100644 --- a/util/manibuilder/Makefile +++ b/util/manibuilder/Makefile @@ -51,8 +51,11 @@ djgpp\:6.1.0: CC=ccache i586-pc-msdosdjgpp-gcc djgpp\:6.1.0: STRIP=i586-pc-msdosdjgpp-strip djgpp\:6.1.0: LIBS_BASE=../ -djgpp\:6.1.0: MAKEARGS+=strip +djgpp\:6.1.0: MAKEARGS+=strip CONFIG_JLINK_SPI=no $(ANITA_TAGS): MAKECMD=gmake +$(ANITA_TAGS): MAKEARGS+=CONFIG_JLINK_SPI=no +$(filter alpine% centos%,$(MULTIARCH_TAGS)): MAKEARGS+=CONFIG_JLINK_SPI=no +$(filter %-xenial %-stretch,$(MULTIARCH_TAGS)): MAKEARGS+=CONFIG_JLINK_SPI=no $(ALL_TAGS): export QUIET_SETUP=$(QUIET_TEST) $(ALL_TAGS): %: %-check-build $(QUIET_TEST)docker rm -f mani_$(call ident,$*) >/dev/null 2>&1 || true -- To view, visit https://review.coreboot.org/c/flashrom/+/33338 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I2f7aebe602ebdb0a4748640e281b9a92146f0ca8 Gerrit-Change-Number: 33338 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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Change in ...flashrom[master]: manibuilder: Enable CONFIG_EVERYTHING=yes
by Nico Huber (Code Review) March 16, 2021

March 16, 2021

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/33337 Change subject: manibuilder: Enable CONFIG_EVERYTHING=yes ...................................................................... manibuilder: Enable CONFIG_EVERYTHING=yes Change-Id: I4651b55744d730956aa8fda8fdfccbbd68cdda19 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M util/manibuilder/Makefile 1 file changed, 3 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/37/33337/1 diff --git a/util/manibuilder/Makefile b/util/manibuilder/Makefile index b1e161c..9b87f45 100644 --- a/util/manibuilder/Makefile +++ b/util/manibuilder/Makefile @@ -4,6 +4,7 @@ CC := ccache cc MAKECMD := make +MAKEARGS := CONFIG_EVERYTHING=yes spc := spc += @@ -50,7 +51,7 @@ djgpp\:6.1.0: CC=ccache i586-pc-msdosdjgpp-gcc djgpp\:6.1.0: STRIP=i586-pc-msdosdjgpp-strip djgpp\:6.1.0: LIBS_BASE=../ -djgpp\:6.1.0: TARGET=strip +djgpp\:6.1.0: MAKEARGS+=strip $(ANITA_TAGS): MAKECMD=gmake $(ALL_TAGS): export QUIET_SETUP=$(QUIET_TEST) $(ALL_TAGS): %: %-check-build @@ -65,7 +66,7 @@ $(MAKECMD) clean && $(MAKECMD) -j$${CPUS:-1} CC='$(CC)' \ $(if $(STRIP),STRIP='$(STRIP)') \ $(if $(LIBS_BASE),LIBS_BASE='$(LIBS_BASE)') \ - $(TARGET)" \ + $(MAKEARGS)" \ $(if $(QUIET_TEST),>/dev/null 2>&1) || echo $*: $$? $(addsuffix -shell,$(ALL_TAGS)): %-shell: %-check-build -- To view, visit https://review.coreboot.org/c/flashrom/+/33337 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I4651b55744d730956aa8fda8fdfccbbd68cdda19 Gerrit-Change-Number: 33337 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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Change in flashrom[master]: libflashrom: add querying functions with meson integration
by Michał Żygowski (Code Review) March 13, 2021

March 13, 2021

Hello ?ukasz Dmitrowski, I'd like you to do a code review. Please visit https://review.coreboot.org/c/flashrom/+/34363 to review the following change. Change subject: libflashrom: add querying functions with meson integration ...................................................................... libflashrom: add querying functions with meson integration Work based on lukasz.dmitrowski(a)gmail.com code Change-Id: I49041b8fa5700dabe59fef0d2337339d34cd6c6f Signed-off-by: Artur Raglis <artur.raglis(a)3mdeb.com> Signed-off-by: Lukasz Dmitrowski <lukasz.dmitrowski(a)gmail.com> --- M libflashrom.c M libflashrom.h M libflashrom.map M meson.build 4 files changed, 187 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/63/34363/1 diff --git a/libflashrom.c b/libflashrom.c index f90a22c..cc26835 100644 --- a/libflashrom.c +++ b/libflashrom.c @@ -103,7 +103,142 @@ * @{ */ -/* TBD */ +/** + * @brief Returns flashrom version + * @return Flashrom version + */ +const char *flashrom_version_info(void) +{ + return flashrom_version; +} + +/** + * @brief Returns list of supported programmers + * @return List of supported programmers + */ +const char **flashrom_supported_programmers(void) +{ + enum programmer p = 0; + const char **supported_programmers = NULL; + supported_programmers = malloc((PROGRAMMER_INVALID + 1) * sizeof(char*)); + + if (supported_programmers != NULL) { + for (; p < PROGRAMMER_INVALID; ++p) { + supported_programmers[p] = programmer_table[p].name; + } + } else { + msg_gerr("Memory allocation error!\n"); + } + + return supported_programmers; +} + +/** + * @brief Returns list of supported flash chips + * @return List of supported flash chips + */ +flashrom_flashchip_info *flashrom_supported_flash_chips(void) +{ + int i = 0; + flashrom_flashchip_info *supported_flashchips = malloc(flashchips_size * sizeof(flashrom_flashchip_info)); + + if (supported_flashchips != NULL) { + for (; i < flashchips_size; ++i) { + supported_flashchips[i].vendor = flashchips[i].vendor; + supported_flashchips[i].name = flashchips[i].name; + supported_flashchips[i].tested.erase = (flashrom_test_state) flashchips[i].tested.erase; + supported_flashchips[i].tested.probe = (flashrom_test_state) flashchips[i].tested.probe; + supported_flashchips[i].tested.read = (flashrom_test_state) flashchips[i].tested.read; + supported_flashchips[i].tested.write = (flashrom_test_state) flashchips[i].tested.write; + supported_flashchips[i].total_size = flashchips[i].total_size; + } + } else { + msg_gerr("Memory allocation error!\n"); + } + + return supported_flashchips; +} + +/** + * @brief Returns list of supported mainboards + * @return List of supported mainboards + */ +flashrom_board_info *flashrom_supported_boards(void) +{ + int boards_known_size = 0; + int i = 0; + const struct board_info *binfo = boards_known; + + while ((binfo++)->vendor) + ++boards_known_size; + binfo = boards_known; + /* add place for {0} */ + ++boards_known_size; + + flashrom_board_info *supported_boards = malloc(boards_known_size * sizeof(flashrom_board_info)); + + if (supported_boards != NULL) { + for (; i < boards_known_size; ++i) { + supported_boards[i].vendor = binfo[i].vendor; + supported_boards[i].name = binfo[i].name; + supported_boards[i].working = binfo[i].working; + } + } else { + msg_gerr("Memory allocation error!\n"); + } + + return supported_boards; +} + +/** + * @brief Returns list of supported chipsets + * @return List of supported chipsets + */ +flashrom_chipset_info *flashrom_supported_chipsets(void) +{ + int chipset_enables_size = 0; + int i = 0; + const struct penable *chipset = chipset_enables; + + while ((chipset++)->vendor_name) + ++chipset_enables_size; + chipset = chipset_enables; + /* add place for {0}*/ + ++chipset_enables_size; + + flashrom_chipset_info *supported_chipsets = malloc(chipset_enables_size * sizeof(flashrom_chipset_info)); + + if (supported_chipsets != NULL) { + for (; i < chipset_enables_size; ++i) { + supported_chipsets[i].vendor = chipset[i].vendor_name; + supported_chipsets[i].chipset = chipset[i].device_name; + supported_chipsets[i].vendor_id = chipset[i].vendor_id; + supported_chipsets[i].chipset_id = chipset[i].device_id; + supported_chipsets[i].status = chipset[i].status; + } + } else { + msg_gerr("Memory allocation error!\n"); + } + + return supported_chipsets; +} + +/** + * @brief Frees memory allocated by libflashrom API + * @param Pointer to block of memory which should be freed + * @return 0 on success + * 1 on null pointer error + */ +int flashrom_data_free(void *const p) +{ + if (!p) { + msg_gerr("flashrom_data_free - Null pointer!\n"); + return 1; + } else { + free(p); + return 0; + } +} /** @} */ /* end flashrom-query */ diff --git a/libflashrom.h b/libflashrom.h index 38c95d2..ebba16b 100644 --- a/libflashrom.h +++ b/libflashrom.h @@ -37,6 +37,50 @@ typedef int(flashrom_log_callback)(enum flashrom_log_level, const char *format, va_list); void flashrom_set_log_callback(flashrom_log_callback *); +/** @ingroup flashrom-query */ +typedef enum { + FLASHROM_TESTED_OK = 0, + FLASHROM_TESTED_NT = 1, + FLASHROM_TESTED_BAD = 2, + FLASHROM_TESTED_DEP = 3, + FLASHROM_TESTED_NA = 4, +} flashrom_test_state; + +typedef struct flashrom_flashchip_info { + const char *vendor; + const char *name; + unsigned int total_size; + struct flashrom_tested { + flashrom_test_state probe; + flashrom_test_state read; + flashrom_test_state erase; + flashrom_test_state write; + } tested; +} flashrom_flashchip_info; + +typedef struct flashrom_board_info { + const char *vendor; + const char *name; + flashrom_test_state working; +} flashrom_board_info; + +typedef struct flashrom_chipset_info { + const char *vendor; + const char *chipset; + uint16_t vendor_id; + uint16_t chipset_id; + flashrom_test_state status; +} flashrom_chipset_info; + +const char *flashrom_version_info(void); +void flashrom_system_info(void); +const char **flashrom_supported_programmers(void); +flashrom_flashchip_info *flashrom_supported_flash_chips(void); +flashrom_board_info *flashrom_supported_boards(void); +flashrom_chipset_info *flashrom_supported_chipsets(void); +int flashrom_data_free(void *const p); + +/** @ingroup flashrom-prog */ struct flashrom_programmer; int flashrom_programmer_init(struct flashrom_programmer **, const char *prog_name, const char *prog_params); int flashrom_programmer_shutdown(struct flashrom_programmer *); diff --git a/libflashrom.map b/libflashrom.map index 3c287ff..d6dd24d 100644 --- a/libflashrom.map +++ b/libflashrom.map @@ -1,7 +1,11 @@ LIBFLASHROM_1.0 { global: + flashrom_board_info; + flashrom_chipset_info; + flashrom_data_free; flashrom_flag_get; flashrom_flag_set; + flashrom_flashchip_info; flashrom_flash_erase; flashrom_flash_getsize; flashrom_flash_probe; @@ -20,5 +24,8 @@ flashrom_programmer_shutdown; flashrom_set_log_callback; flashrom_shutdown; + flashrom_supported_programmers; + flashrom_system_info; + flashrom_version_info; local: *; }; diff --git a/meson.build b/meson.build index 1923fdf..00f4a2f 100644 --- a/meson.build +++ b/meson.build @@ -68,8 +68,6 @@ srcs = [] need_libusb0 = false -need_raw_access = false -need_serial = false # check for required symbols if cc.has_function('clock_gettime') -- To view, visit https://review.coreboot.org/c/flashrom/+/34363 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I49041b8fa5700dabe59fef0d2337339d34cd6c6f Gerrit-Change-Number: 34363 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: ?ukasz Dmitrowski <lukasz.dmitrowski(a)gmail.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: flashchips.c: Take GD25LQ128C/D from downstream
by Alan Green (Code Review) Jan. 6, 2021

Jan. 6, 2021

Alan Green has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/35478 ) Change subject: flashchips.c: Take GD25LQ128C/D from downstream ...................................................................... flashchips.c: Take GD25LQ128C/D from downstream Take the diffs for GD25LQ128C/D from the ChromiumOS flashrom repo. This chips was added in Chromium OS `commit 62cd8106` by furquan(a)google.com on 2016-07-18, and has been marked tested. Signed-off-by: Alan Green <avg(a)google.com> Change-Id: I4358392520507ddbfc654feb49fa982d49db2f28 --- M flashchips.c 1 file changed, 2 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/78/35478/1 diff --git a/flashchips.c b/flashchips.c index 3994c93..5c797fd 100644 --- a/flashchips.c +++ b/flashchips.c @@ -5894,7 +5894,7 @@ .page_size = 256, /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44 */ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, - .tested = TEST_UNTESTED, + .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = @@ -5916,8 +5916,7 @@ .block_erase = spi_block_erase_c7, } }, - .printlock = spi_prettyprint_status_register_bp4_srwd, - .unlock = spi_disable_blockprotect_bp4_srwd, /* TODO: 2nd status reg (read with 0x35) */ + .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ .voltage = {1695, 1950}, -- To view, visit https://review.coreboot.org/c/flashrom/+/35478 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I4358392520507ddbfc654feb49fa982d49db2f28 Gerrit-Change-Number: 35478 Gerrit-PatchSet: 1 Gerrit-Owner: Alan Green <avg(a)google.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: flashchips.c: Take GD25LQ40 from downstream
by Alan Green (Code Review) Jan. 6, 2021

Jan. 6, 2021

Alan Green has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/35479 ) Change subject: flashchips.c: Take GD25LQ40 from downstream ...................................................................... flashchips.c: Take GD25LQ40 from downstream Take definition of GD25LQ40 from ChromiumOS repository. This chip was added in `commit 59543cd1` by dnschneid(a)chromium.org on 2016-04-27. The commit message notes that some testing had been done, even thought the .tested attribute was left as UNTESTED. Signed-off-by: Alan Green <avg(a)google.com> Change-Id: I978745b38536cda807adf07af4e4d093d0d93ad1 --- M flashchips.c 1 file changed, 2 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/79/35479/1 diff --git a/flashchips.c b/flashchips.c index 5c797fd..ac07fa8 100644 --- a/flashchips.c +++ b/flashchips.c @@ -6009,7 +6009,7 @@ .total_size = 512, .page_size = 256, /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44 */ - .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, + .feature_bits = FEATURE_WRSR_WREN, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, @@ -6032,8 +6032,7 @@ .block_erase = spi_block_erase_c7, } }, - .printlock = spi_prettyprint_status_register_bp4_srwd, - .unlock = spi_disable_blockprotect_bp4_srwd, /* TODO: 2nd status reg (read with 0x35) */ + .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ .voltage = {1695, 1950}, -- To view, visit https://review.coreboot.org/c/flashrom/+/35479 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I978745b38536cda807adf07af4e4d093d0d93ad1 Gerrit-Change-Number: 35479 Gerrit-PatchSet: 1 Gerrit-Owner: Alan Green <avg(a)google.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: sb600spi.c: Don't access spibar directly
by Edward O'Callaghan (Code Review) Nov. 26, 2020

Nov. 26, 2020

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/36433 ) Change subject: sb600spi.c: Don't access spibar directly ...................................................................... sb600spi.c: Don't access spibar directly Constrain the manner in which the global state of spibar is set and then subsequently accessed. This makes it easier to write unit-tests and instrument the code. Change-Id: Ic26372b9c1baebb20716eea1db1e942239ed3e48 Signed-off-by: Edward O'Callaghan <quasisec(a)chromium.org> --- M sb600spi.c 1 file changed, 53 insertions(+), 38 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/33/36433/1 diff --git a/sb600spi.c b/sb600spi.c index 23b36ee..7bdd11f 100644 --- a/sb600spi.c +++ b/sb600spi.c @@ -40,7 +40,13 @@ *}; */ -static uint8_t *sb600_spibar = NULL; +static uint8_t *g_sb600_spibar = NULL; + +static inline uint8_t * get_spibar(void) +{ + return g_sb600_spibar; +} + enum amd_chipset { CHIPSET_AMD_UNKNOWN, CHIPSET_SB6XX, @@ -180,16 +186,18 @@ static void reset_internal_fifo_pointer(void) { - mmio_writeb(mmio_readb(sb600_spibar + 2) | 0x10, sb600_spibar + 2); + uint8_t *spibar = get_spibar(); + mmio_writeb(mmio_readb(spibar + 2) | 0x10, spibar + 2); /* FIXME: This loop needs a timeout and a clearer message. */ - while (mmio_readb(sb600_spibar + 0xD) & 0x7) + while (mmio_readb(spibar + 0xD) & 0x7) msg_pspew("reset\n"); } static int compare_internal_fifo_pointer(uint8_t want) { - uint8_t have = mmio_readb(sb600_spibar + 0xd) & 0x07; + uint8_t *spibar = get_spibar(); + uint8_t have = mmio_readb(spibar + 0xd) & 0x07; want %= FIFO_SIZE_OLD; if (have != want) { msg_perr("AMD SPI FIFO pointer corruption! Pointer is %d, wanted %d\n", have, want); @@ -224,8 +232,9 @@ static void execute_command(void) { msg_pspew("Executing... "); - mmio_writeb(mmio_readb(sb600_spibar + 2) | 1, sb600_spibar + 2); - while (mmio_readb(sb600_spibar + 2) & 1) + uint8_t *spibar = get_spibar(); + mmio_writeb(mmio_readb(spibar + 2) | 1, spibar + 2); + while (mmio_readb(spibar + 2) & 1) ; msg_pspew("done\n"); } @@ -239,7 +248,8 @@ unsigned char cmd = *writearr++; writecnt--; msg_pspew("%s, cmd=0x%02x, writecnt=%d, readcnt=%d\n", __func__, cmd, writecnt, readcnt); - mmio_writeb(cmd, sb600_spibar + 0); + uint8_t *spibar = get_spibar(); + mmio_writeb(cmd, spibar + 0); int ret = check_readwritecnt(flash, writecnt, readcnt); if (ret != 0) @@ -253,14 +263,14 @@ */ unsigned int readoffby1 = (writecnt > 0) ? 0 : 1; uint8_t readwrite = (readcnt + readoffby1) << 4 | (writecnt); - mmio_writeb(readwrite, sb600_spibar + 1); + mmio_writeb(readwrite, spibar + 1); reset_internal_fifo_pointer(); msg_pspew("Filling FIFO: "); unsigned int count; for (count = 0; count < writecnt; count++) { msg_pspew("[%02x]", writearr[count]); - mmio_writeb(writearr[count], sb600_spibar + 0xC); + mmio_writeb(writearr[count], spibar + 0xC); } msg_pspew("\n"); if (compare_internal_fifo_pointer(writecnt)) @@ -291,7 +301,7 @@ /* Skip the bytes we sent. */ msg_pspew("Skipping: "); for (count = 0; count < writecnt; count++) { - msg_pspew("[%02x]", mmio_readb(sb600_spibar + 0xC)); + msg_pspew("[%02x]", mmio_readb(spibar + 0xC)); } msg_pspew("\n"); if (compare_internal_fifo_pointer(writecnt)) @@ -299,14 +309,14 @@ msg_pspew("Reading FIFO: "); for (count = 0; count < readcnt; count++) { - readarr[count] = mmio_readb(sb600_spibar + 0xC); + readarr[count] = mmio_readb(spibar + 0xC); msg_pspew("[%02x]", readarr[count]); } msg_pspew("\n"); if (compare_internal_fifo_pointer(writecnt+readcnt)) return SPI_PROGRAMMER_ERROR; - if (mmio_readb(sb600_spibar + 1) != readwrite) { + if (mmio_readb(spibar + 1) != readwrite) { msg_perr("Unexpected change in AMD SPI read/write count!\n"); msg_perr("Something else is accessing the flash chip and causes random corruption.\n" "Please stop all applications and drivers and IPMI which access the flash chip.\n"); @@ -325,21 +335,22 @@ unsigned char cmd = *writearr++; writecnt--; msg_pspew("%s, cmd=0x%02x, writecnt=%d, readcnt=%d\n", __func__, cmd, writecnt, readcnt); - mmio_writeb(cmd, sb600_spibar + 0); + uint8_t *spibar = get_spibar(); + mmio_writeb(cmd, spibar + 0); int ret = check_readwritecnt(flash, writecnt, readcnt); if (ret != 0) return ret; /* Use the extended TxByteCount and RxByteCount registers. */ - mmio_writeb(writecnt, sb600_spibar + 0x48); - mmio_writeb(readcnt, sb600_spibar + 0x4b); + mmio_writeb(writecnt, spibar + 0x48); + mmio_writeb(readcnt, spibar + 0x4b); msg_pspew("Filling buffer: "); unsigned int count; for (count = 0; count < writecnt; count++) { msg_pspew("[%02x]", writearr[count]); - mmio_writeb(writearr[count], sb600_spibar + 0x80 + count); + mmio_writeb(writearr[count], spibar + 0x80 + count); } msg_pspew("\n"); @@ -347,7 +358,7 @@ msg_pspew("Reading buffer: "); for (count = 0; count < readcnt; count++) { - readarr[count] = mmio_readb(sb600_spibar + 0x80 + (writecnt + count) % FIFO_SIZE_YANGTZE); + readarr[count] = mmio_readb(spibar + 0x80 + (writecnt + count) % FIFO_SIZE_YANGTZE); msg_pspew("[%02x]", readarr[count]); } msg_pspew("\n"); @@ -375,16 +386,17 @@ { bool success = false; uint8_t speed = spispeed->speed; + uint8_t *spibar = get_spibar(); msg_pdbg("Setting SPI clock to %s (0x%x).\n", spispeed->name, speed); if (amd_gen >= CHIPSET_YANGTZE) { - rmmio_writew((speed << 12) | (speed << 8) | (speed << 4) | speed, sb600_spibar + 0x22); - uint16_t tmp = mmio_readw(sb600_spibar + 0x22); + rmmio_writew((speed << 12) | (speed << 8) | (speed << 4) | speed, spibar + 0x22); + uint16_t tmp = mmio_readw(spibar + 0x22); success = (((tmp >> 12) & 0xf) == speed && ((tmp >> 8) & 0xf) == speed && ((tmp >> 4) & 0xf) == speed && ((tmp >> 0) & 0xf) == speed); } else { - rmmio_writeb((mmio_readb(sb600_spibar + 0xd) & ~(0x3 << 4)) | (speed << 4), sb600_spibar + 0xd); - success = (speed == ((mmio_readb(sb600_spibar + 0xd) >> 4) & 0x3)); + rmmio_writeb((mmio_readb(spibar + 0xd) & ~(0x3 << 4)) | (speed << 4), spibar + 0xd); + success = (speed == ((mmio_readb(spibar + 0xd) >> 4) & 0x3)); } if (!success) { @@ -396,11 +408,12 @@ static int set_mode(struct pci_dev *dev, uint8_t read_mode) { - uint32_t tmp = mmio_readl(sb600_spibar + 0x00); + uint8_t *spibar = get_spibar(); + uint32_t tmp = mmio_readl(spibar + 0x00); tmp &= ~(0x6 << 28 | 0x1 << 18); /* Clear mode bits */ tmp |= ((read_mode & 0x6) << 28) | ((read_mode & 0x1) << 18); - rmmio_writel(tmp, sb600_spibar + 0x00); - if (tmp != mmio_readl(sb600_spibar + 0x00)) + rmmio_writel(tmp, spibar + 0x00); + if (tmp != mmio_readl(spibar + 0x00)) return 1; return 0; } @@ -409,6 +422,7 @@ { uint32_t tmp; uint8_t spispeed_idx = 3; /* Default to 16.5 MHz */ + uint8_t *spibar = get_spibar(); char *spispeed = extract_programmer_param("spispeed"); if (spispeed != NULL) { @@ -450,7 +464,7 @@ "Normal (up to 66 MHz)", /* 6 */ "Fast Read", /* 7 (Not defined in the Bolton datasheet.) */ }; - tmp = mmio_readl(sb600_spibar + 0x00); + tmp = mmio_readl(spibar + 0x00); uint8_t read_mode = ((tmp >> 28) & 0x6) | ((tmp >> 18) & 0x1); msg_pdbg("SpiReadMode=%s (%i)\n", spireadmodes[read_mode], read_mode); if (read_mode != 6) { @@ -463,11 +477,11 @@ } if (amd_gen >= CHIPSET_YANGTZE) { - tmp = mmio_readb(sb600_spibar + 0x20); + tmp = mmio_readb(spibar + 0x20); msg_pdbg("UseSpi100 is %sabled\n", (tmp & 0x1) ? "en" : "dis"); if ((tmp & 0x1) == 0) { - rmmio_writeb(tmp | 0x1, sb600_spibar + 0x20); - tmp = mmio_readb(sb600_spibar + 0x20) & 0x1; + rmmio_writeb(tmp | 0x1, spibar + 0x20); + tmp = mmio_readb(spibar + 0x20) & 0x1; if (tmp == 0) { msg_perr("Enabling Spi100 failed.\n"); return 1; @@ -475,7 +489,7 @@ msg_pdbg("Enabling Spi100 succeeded.\n"); } - tmp = mmio_readw(sb600_spibar + 0x22); /* SPI 100 Speed Config */ + tmp = mmio_readw(spibar + 0x22); /* SPI 100 Speed Config */ msg_pdbg("NormSpeedNew is %s\n", spispeeds[(tmp >> 12) & 0xf].name); msg_pdbg("FastSpeedNew is %s\n", spispeeds[(tmp >> 8) & 0xf].name); msg_pdbg("AltSpeedNew is %s\n", spispeeds[(tmp >> 4) & 0xf].name); @@ -483,15 +497,15 @@ } } else { if (amd_gen >= CHIPSET_SB89XX && amd_gen <= CHIPSET_HUDSON234) { - bool fast_read = (mmio_readl(sb600_spibar + 0x00) >> 18) & 0x1; + bool fast_read = (mmio_readl(spibar + 0x00) >> 18) & 0x1; msg_pdbg("Fast Reads are %sabled\n", fast_read ? "en" : "dis"); if (fast_read) { msg_pdbg("Disabling them temporarily.\n"); - rmmio_writel(mmio_readl(sb600_spibar + 0x00) & ~(0x1 << 18), - sb600_spibar + 0x00); + rmmio_writel(mmio_readl(spibar + 0x00) & ~(0x1 << 18), + spibar + 0x00); } } - tmp = (mmio_readb(sb600_spibar + 0xd) >> 4) & 0x3; + tmp = (mmio_readb(spibar + 0xd) >> 4) & 0x3; msg_pdbg("NormSpeed is %s\n", spispeeds[tmp].name); } return set_speed(dev, amd_gen, &spispeeds[spispeed_idx]); @@ -581,14 +595,14 @@ return 0; /* Physical memory has to be mapped at page (4k) boundaries. */ - sb600_spibar = rphysmap("SB600 SPI registers", tmp & 0xfffff000, 0x1000); - if (sb600_spibar == ERROR_PTR) + g_sb600_spibar = rphysmap("SB600 SPI registers", tmp & 0xfffff000, 0x1000); + if (g_sb600_spibar == ERROR_PTR) return ERROR_FATAL; /* The low bits of the SPI base address are used as offset into * the mapped page. */ - sb600_spibar += tmp & 0xfff; + g_sb600_spibar += tmp & 0xfff; int amd_gen = determine_generation(dev); if (amd_gen < 0) @@ -649,7 +663,8 @@ * * <1> see handle_speed */ - tmp = mmio_readl(sb600_spibar + 0x00); + uint8_t *spibar = get_spibar(); + tmp = mmio_readl(spibar + 0x00); msg_pdbg("(0x%08" PRIx32 ") SpiArbEnable=%i", tmp, (tmp >> 19) & 0x1); if (amd_gen >= CHIPSET_YANGTZE) msg_pdbg(", IllegalAccess=%i", (tmp >> 21) & 0x1); @@ -679,7 +694,7 @@ } if (amd_gen >= CHIPSET_SB89XX) { - tmp = mmio_readb(sb600_spibar + 0x1D); + tmp = mmio_readb(spibar + 0x1D); msg_pdbg("Using SPI_CS%d\n", tmp & 0x3); /* FIXME: Handle SpiProtect* configuration on Yangtze. */ } -- To view, visit https://review.coreboot.org/c/flashrom/+/36433 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ic26372b9c1baebb20716eea1db1e942239ed3e48 Gerrit-Change-Number: 36433 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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Change in flashrom[master]: sb600spi.c: Remove 'amd_gen' out of global state.
by Edward O'Callaghan (Code Review) Nov. 25, 2020

Nov. 25, 2020

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/36432 ) Change subject: sb600spi.c: Remove 'amd_gen' out of global state. ...................................................................... sb600spi.c: Remove 'amd_gen' out of global state. Have 'determine_generation()' explicitly return 'amd_gen' and then pass the state into what requires it. Thus making the code more pure, easier to read and more unit-testable. Change-Id: I99fbad9486123c6b921eab83756de54a53ddfa7a Signed-off-by: Edward O'Callaghan <quasisec(a)chromium.org> --- M sb600spi.c 1 file changed, 12 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/32/36432/1 diff --git a/sb600spi.c b/sb600spi.c index 8daaf03..23b36ee 100644 --- a/sb600spi.c +++ b/sb600spi.c @@ -51,7 +51,6 @@ CHIPSET_YANGTZE, CHIPSET_PROMONTORY, }; -static enum amd_chipset amd_gen = CHIPSET_AMD_UNKNOWN; #define FIFO_SIZE_OLD 8 #define FIFO_SIZE_YANGTZE 71 @@ -110,7 +109,7 @@ /* Determine the chipset's version and identify the respective SMBUS device. */ static int determine_generation(struct pci_dev *dev) { - amd_gen = CHIPSET_AMD_UNKNOWN; + enum amd_chipset amd_gen = CHIPSET_AMD_UNKNOWN; msg_pdbg2("Trying to determine the generation of the SPI interface... "); if (dev->device_id == 0x438d) { amd_gen = CHIPSET_SB6XX; @@ -173,11 +172,10 @@ "Please report this to flashrom(a)flashrom.org and include this log and\n" "the output of lspci -nnvx, thanks!\n", __func__, dev->vendor_id, dev->device_id); - if (amd_gen == CHIPSET_AMD_UNKNOWN) { + if (amd_gen == CHIPSET_AMD_UNKNOWN) msg_perr("Could not determine chipset generation."); - return -1; - } - return 0; + + return amd_gen; } static void reset_internal_fifo_pointer(void) @@ -373,7 +371,7 @@ { "800 kHz", 0x07 }, }; -static int set_speed(struct pci_dev *dev, const struct spispeed *spispeed) +static int set_speed(struct pci_dev *dev, enum amd_chipset amd_gen, const struct spispeed *spispeed) { bool success = false; uint8_t speed = spispeed->speed; @@ -407,7 +405,7 @@ return 0; } -static int handle_speed(struct pci_dev *dev) +static int handle_speed(struct pci_dev *dev, enum amd_chipset amd_gen) { uint32_t tmp; uint8_t spispeed_idx = 3; /* Default to 16.5 MHz */ @@ -496,10 +494,10 @@ tmp = (mmio_readb(sb600_spibar + 0xd) >> 4) & 0x3; msg_pdbg("NormSpeed is %s\n", spispeeds[tmp].name); } - return set_speed(dev, &spispeeds[spispeed_idx]); + return set_speed(dev, amd_gen, &spispeeds[spispeed_idx]); } -static int handle_imc(struct pci_dev *dev) +static int handle_imc(struct pci_dev *dev, enum amd_chipset amd_gen) { /* Handle IMC everywhere but sb600 which does not have one. */ if (amd_gen == CHIPSET_SB6XX) @@ -592,7 +590,8 @@ */ sb600_spibar += tmp & 0xfff; - if (determine_generation(dev) < 0) + int amd_gen = determine_generation(dev); + if (amd_gen < 0) return ERROR_NONFATAL; /* How to read the following table and similar ones in this file: @@ -725,10 +724,10 @@ return 0; } - if (handle_speed(dev) != 0) + if (handle_speed(dev, amd_gen) != 0) return ERROR_FATAL; - if (handle_imc(dev) != 0) + if (handle_imc(dev, amd_gen) != 0) return ERROR_FATAL; /* Starting with Yangtze the SPI controller got a different interface with a much bigger buffer. */ -- To view, visit https://review.coreboot.org/c/flashrom/+/36432 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I99fbad9486123c6b921eab83756de54a53ddfa7a Gerrit-Change-Number: 36432 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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