Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34180 )
Change subject: mb/google/hatch: Enable/disable GPIO clock gating ......................................................................
mb/google/hatch: Enable/disable GPIO clock gating
Before the system enters S0ix or S3, each GPIO community will have its dynamic clock gating turned on. Upon return to S0, the dynamic clock gating will be turned back off.
BUG=b:130764684 BRANCH=none TEST=Used dut-power to verify that the clock gating is enabled in S0ix and S3. Also used Store(..., Debug) statements in the ASL code to verify it was getting called.
Change-Id: I20ff2aac035eaa5912af6c946d837567a4918bbf Signed-off-by: Tim Wawrzynczak twawrzynczak@chromium.org --- M src/mainboard/google/hatch/dsdt.asl A src/mainboard/google/hatch/mainboard.asl 2 files changed, 90 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/34180/1
diff --git a/src/mainboard/google/hatch/dsdt.asl b/src/mainboard/google/hatch/dsdt.asl index 87e98ea..e2959a7 100644 --- a/src/mainboard/google/hatch/dsdt.asl +++ b/src/mainboard/google/hatch/dsdt.asl @@ -41,6 +41,9 @@ #include <soc/intel/cannonlake/acpi/northbridge.asl> #include <soc/intel/cannonlake/acpi/southbridge.asl> } + + /* Mainboard hooks */ + #include "mainboard.asl" }
#if CONFIG(CHROMEOS) diff --git a/src/mainboard/google/hatch/mainboard.asl b/src/mainboard/google/hatch/mainboard.asl new file mode 100644 index 0000000..a8f5dc1 --- /dev/null +++ b/src/mainboard/google/hatch/mainboard.asl @@ -0,0 +1,87 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <intelblocks/gpio.h> + +/* + * ConfiGure Power Management + * for GPIO communities + * + * Arg0: GPIO community (0-4) + * Arg1: 0=PM off, 1=PM on + */ +Method (CGPM, 2, Serialized) +{ + /* + * _SB.PCI0.GCFG = Get GPIO MISCCFG Register Address + */ + OperationRegion (PREG, SystemMemory, _SB.PCI0.GCFG (Arg0), 4) + Field (PREG, ByteAcc, NoLock, Preserve) + { + REG, 32 + } + + If (LEqual (Arg1, 0)) { + /* Read register, mask off PM bits, write back */ + Store (REG, Local1) + Store (LAnd (Local1, LNot (MISCCFG_ENABLE_GPIO_PM_CONFIG)), Local1) + Store (Local1, REG) + } Else { + /* Read register, OR in the PM bits, write back */ + Store (REG, Local1) + Store (LOr (Local1, MISCCFG_ENABLE_GPIO_PM_CONFIG), Local1) + Store (Local1, REG) + } +} + +/* + * Method called from _PTS prior to sleep state entry + * Enables dynamic clock gating for all 5 GPIO communities + */ +Method (MPTS, 1, Serialized) +{ + For (Local0 = 0, Local0 < 5, Local0++) + { + CGPM (Local0, 1) + } +} + +/* + * Method called from _WAK prior to system sleep state wakeup + * Disables dynamic clock gating for all 5 GPIO communities + */ +Method (MWAK, 1, Serialized) +{ + For (Local0 = 0, Local0 < 5, Local0++) + { + CGPM (Local0, 0) + } +} + +/* Called from _SB.LPID._DSM */ +Method (MS0X, 1, Serialized) +{ + If (Arg0 == 1) { + For (Local0 = 0, Local0 < 5, Local0++) + { + CGPM (Local0, 1) + } + } Else { + For (Local0 = 0, Local0 < 5, Local0++) + { + CGPM (Local0, 0) + } + } +}
Hello Subrata Banik, Duncan Laurie, Shelley Chen, Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34180
to look at the new patch set (#2).
Change subject: mb/google/hatch: Enable/disable GPIO clock gating ......................................................................
mb/google/hatch: Enable/disable GPIO clock gating
Before the system enters S0ix or S3, each GPIO community will have its dynamic clock gating turned on. Upon return to S0, the dynamic clock gating will be turned back off.
BUG=b:130764684 BRANCH=none TEST=Used dut-power to verify that the clock gating is enabled in S0ix and S3. Also used Store(..., Debug) statements in the ASL code to verify it was getting called.
Change-Id: I20ff2aac035eaa5912af6c946d837567a4918bbf Signed-off-by: Tim Wawrzynczak twawrzynczak@chromium.org --- M src/mainboard/google/hatch/dsdt.asl A src/mainboard/google/hatch/mainboard.asl 2 files changed, 90 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/34180/2
Hello Subrata Banik, Duncan Laurie, Shelley Chen, build bot (Jenkins), Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34180
to look at the new patch set (#3).
Change subject: mb/google/hatch: Enable/disable GPIO clock gating ......................................................................
mb/google/hatch: Enable/disable GPIO clock gating
Before the system enters S0ix or S3, each GPIO community will have its dynamic clock gating turned on. Upon return to S0, the dynamic clock gating will be turned back off.
BUG=b:130764684 BRANCH=none TEST=Used dut-power to verify that the clock gating is enabled in S0ix and S3. Also used Store(..., Debug) statements in the ASL code to verify it was getting called.
Change-Id: I20ff2aac035eaa5912af6c946d837567a4918bbf Signed-off-by: Tim Wawrzynczak twawrzynczak@chromium.org --- M src/mainboard/google/hatch/dsdt.asl A src/mainboard/google/hatch/mainboard.asl 2 files changed, 90 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/34180/3
Paul Fagerburg has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34180 )
Change subject: mb/google/hatch: Enable/disable GPIO clock gating ......................................................................
Patch Set 3: Code-Review+1
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34180 )
Change subject: mb/google/hatch: Enable/disable GPIO clock gating ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34180/3/src/mainboard/google/hatch/... File src/mainboard/google/hatch/mainboard.asl:
https://review.coreboot.org/c/coreboot/+/34180/3/src/mainboard/google/hatch/... PS3, Line 25: CGPM Why not add this method to soc/intel/cannonlake? It can take as parameter the value of PM config that needs to be set.
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34180 )
Change subject: mb/google/hatch: Enable/disable GPIO clock gating ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34180/3/src/mainboard/google/hatch/... File src/mainboard/google/hatch/mainboard.asl:
https://review.coreboot.org/c/coreboot/+/34180/3/src/mainboard/google/hatch/... PS3, Line 25: CGPM
Why not add this method to soc/intel/cannonlake? It can take as parameter the value of PM config tha […]
That seems fair.
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34180 )
Change subject: mb/google/hatch: Enable/disable GPIO clock gating ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34180/3/src/mainboard/google/hatch/... File src/mainboard/google/hatch/mainboard.asl:
https://review.coreboot.org/c/coreboot/+/34180/3/src/mainboard/google/hatch/... PS3, Line 25: CGPM
That seems fair.
Done
Hello Paul Fagerburg, Subrata Banik, Duncan Laurie, Shelley Chen, build bot (Jenkins), Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34180
to look at the new patch set (#4).
Change subject: mb/google/hatch: Enable/disable GPIO clock gating ......................................................................
mb/google/hatch: Enable/disable GPIO clock gating
Before the system enters S0ix or S3, each GPIO community will have its dynamic clock gating turned on. Upon return to S0, the dynamic clock gating will be turned back off.
BUG=b:130764684 BRANCH=none TEST=Used dut-power to verify that the clock gating is enabled in S0ix and S3. Also used Store(..., Debug) statements in the ASL code to verify it was getting called.
Change-Id: I20ff2aac035eaa5912af6c946d837567a4918bbf Signed-off-by: Tim Wawrzynczak twawrzynczak@chromium.org --- M src/mainboard/google/hatch/dsdt.asl A src/mainboard/google/hatch/mainboard.asl M src/soc/intel/cannonlake/acpi/gpio.asl 3 files changed, 86 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/34180/4
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34180 )
Change subject: mb/google/hatch: Enable/disable GPIO clock gating ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34180/4/src/soc/intel/cannonlake/ac... File src/soc/intel/cannonlake/acpi/gpio.asl:
PS4: It would be better to separate out SoC and mainboard specific changes into 2 CLs. This change can probably go along with the previous CL for adding GCFG.
Hello Patrick Rudolph, Paul Fagerburg, Subrata Banik, Duncan Laurie, Shelley Chen, build bot (Jenkins), Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34180
to look at the new patch set (#5).
Change subject: mb/google/hatch: Enable/disable GPIO clock gating ......................................................................
mb/google/hatch: Enable/disable GPIO clock gating
Before the system enters S0ix or S3, each GPIO community will have its dynamic clock gating turned on. Upon return to S0, the dynamic clock gating will be turned back off.
BUG=b:130764684 BRANCH=none TEST=Used dut-power to verify that the clock gating is enabled in S0ix and S3. Also used Store(..., Debug) statements in the ASL code to verify it was getting called.
Change-Id: I20ff2aac035eaa5912af6c946d837567a4918bbf Signed-off-by: Tim Wawrzynczak twawrzynczak@chromium.org --- M src/mainboard/google/hatch/dsdt.asl A src/mainboard/google/hatch/mainboard.asl 2 files changed, 61 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/34180/5
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34180 )
Change subject: mb/google/hatch: Enable/disable GPIO clock gating ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34180/4/src/soc/intel/cannonlake/ac... File src/soc/intel/cannonlake/acpi/gpio.asl:
PS4:
It would be better to separate out SoC and mainboard specific changes into 2 CLs. […]
Done
Paul Fagerburg has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34180 )
Change subject: mb/google/hatch: Enable/disable GPIO clock gating ......................................................................
Patch Set 5: Code-Review+1
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34180 )
Change subject: mb/google/hatch: Enable/disable GPIO clock gating ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34180/5/src/mainboard/google/hatch/... File src/mainboard/google/hatch/mainboard.asl:
https://review.coreboot.org/c/coreboot/+/34180/5/src/mainboard/google/hatch/... PS5, Line 24: For (Local0 = 0, Local0 < 5, Local0++) : { : _SB.PCI0.CGPM (Local0, MISCCFG_ENABLE_GPIO_PM_CONFIG) : } Put this in a method of its own which can be called by MPTS, MWAK and MS0X?
Hello Patrick Rudolph, Paul Fagerburg, Subrata Banik, Duncan Laurie, Shelley Chen, build bot (Jenkins), Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34180
to look at the new patch set (#6).
Change subject: mb/google/hatch: Enable/disable GPIO clock gating ......................................................................
mb/google/hatch: Enable/disable GPIO clock gating
Before the system enters S0ix or S3, each GPIO community will have its dynamic clock gating turned on. Upon return to S0, the dynamic clock gating will be turned back off.
BUG=b:130764684 BRANCH=none TEST=Used dut-power to verify that the clock gating is enabled in S0ix and S3. Also used Store(..., Debug) statements in the ASL code to verify it was getting called.
Change-Id: I20ff2aac035eaa5912af6c946d837567a4918bbf Signed-off-by: Tim Wawrzynczak twawrzynczak@chromium.org --- M src/mainboard/google/hatch/dsdt.asl A src/mainboard/google/hatch/mainboard.asl 2 files changed, 60 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/34180/6
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34180 )
Change subject: mb/google/hatch: Enable/disable GPIO clock gating ......................................................................
Patch Set 6: Code-Review+2
Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/34180 )
Change subject: mb/google/hatch: Enable/disable GPIO clock gating ......................................................................
mb/google/hatch: Enable/disable GPIO clock gating
Before the system enters S0ix or S3, each GPIO community will have its dynamic clock gating turned on. Upon return to S0, the dynamic clock gating will be turned back off.
BUG=b:130764684 BRANCH=none TEST=Used dut-power to verify that the clock gating is enabled in S0ix and S3. Also used Store(..., Debug) statements in the ASL code to verify it was getting called.
Change-Id: I20ff2aac035eaa5912af6c946d837567a4918bbf Signed-off-by: Tim Wawrzynczak twawrzynczak@chromium.org Reviewed-on: https://review.coreboot.org/c/coreboot/+/34180 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Furquan Shaikh furquan@google.com --- M src/mainboard/google/hatch/dsdt.asl A src/mainboard/google/hatch/mainboard.asl 2 files changed, 60 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved
diff --git a/src/mainboard/google/hatch/dsdt.asl b/src/mainboard/google/hatch/dsdt.asl index 87e98ea..e2959a7 100644 --- a/src/mainboard/google/hatch/dsdt.asl +++ b/src/mainboard/google/hatch/dsdt.asl @@ -41,6 +41,9 @@ #include <soc/intel/cannonlake/acpi/northbridge.asl> #include <soc/intel/cannonlake/acpi/southbridge.asl> } + + /* Mainboard hooks */ + #include "mainboard.asl" }
#if CONFIG(CHROMEOS) diff --git a/src/mainboard/google/hatch/mainboard.asl b/src/mainboard/google/hatch/mainboard.asl new file mode 100644 index 0000000..dff1a75 --- /dev/null +++ b/src/mainboard/google/hatch/mainboard.asl @@ -0,0 +1,57 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <intelblocks/gpio.h> + +Method (LOCL, 1, Serialized) +{ + For (Local0 = 0, Local0 < 5, Local0++) + { + _SB.PCI0.CGPM (Local0, Arg0) + } +} + +/* + * Method called from _PTS prior to system sleep state entry + * Enables dynamic clock gating for all 5 GPIO communities + */ +Method (MPTS, 1, Serialized) +{ + LOCL (MISCCFG_ENABLE_GPIO_PM_CONFIG) +} + +/* + * Method called from _WAK prior to system sleep state wakeup + * Disables dynamic clock gating for all 5 GPIO communities + */ +Method (MWAK, 1, Serialized) +{ + LOCL (0) +} + +/* + * S0ix Entry/Exit Notifications + * Called from _SB.LPID._DSM + */ +Method (MS0X, 1, Serialized) +{ + If (Arg0 == 1) { + /* S0ix Entry */ + LOCL (MISCCFG_ENABLE_GPIO_PM_CONFIG) + } Else { + /* S0ix Exit */ + LOCL (0) + } +}
-
Furquan Shaikh (Code Review) -
Martin Roth (Code Review)
-
Paul Fagerburg (Code Review)
-
Tim Wawrzynczak (Code Review)