[M] Change in coreboot[master]: soc/intel/alderlake/chip.h: Use boolean type where applicable

[Felix Singer (Code Review)]

Attention is currently required from: Michael Strosche, Subrata Banik, Tarun Tuli.

Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76830?usp=email )

Change subject: soc/intel/alderlake/chip.h: Use boolean type where applicable
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Patch Set 3:

(3 comments)

File src/soc/intel/alderlake/chip.h:

https://review.coreboot.org/c/coreboot/+/76830/comment/abefde18_994df44e :
PS1, Line 343: uint8_t
> Correct, will also be changed.

Done

https://review.coreboot.org/c/coreboot/+/76830/comment/7cbcdaa2_134ed220 :
PS1, Line 463: 	uint8_t skip_ext_gfx_scan;
> skip_ext_gfx_scan could also be removed for alderlake, because it is never used here. […]

It seems it's just not hooked up, as it is the case for other SoCs as well. Copy pasta.. However, let's leave it and hook it up in a separate commit. So please change this to bool as well.

https://review.coreboot.org/c/coreboot/+/76830/comment/cda6d331_23b9e66b :
PS1, Line 482: /*
             : 	 * GSPIn Default Chip Select Mode:
             : 	 * 0:Hardware Mode,
             : 	 * 1:Software Mode
             : 	 */
             : 	bool serial_io_gspi_cs_mode[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX];
             : 	/*
             : 	 * GSPIn Default Chip Select State:
             : 	 * 0: Low,
             : 	 * 1: High
             : 	 */
             : 	bool serial_io_gspi_cs_state[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX];
> In devicetree the configuration values are already enum values (PchSerialIoDisabled, PchSerialIoPci) […]

Done