Wonkyu Kim has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39419 )
Change subject: mb/intel/tglrvp: sync up variant folders with latet up3 ......................................................................
mb/intel/tglrvp: sync up variant folders with latet up3
During intial UP4 patch, below UP3 patches merged same time which should be apply for UP4. https://review.coreboot.org/c/coreboot/+/39201 https://review.coreboot.org/c/coreboot/+/39229 Merge this patches to UP4
BUG=none BRANCH=none TEST=Build TGL UP4
Signed-off-by: Wonkyu Kim wonkyu.kim@intel.com Change-Id: I7b24cb2b0d03309cf67c6c21ddc2031a054f6110 --- M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c 2 files changed, 14 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/39419/1
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index a937ab3..60bb938 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -48,6 +48,7 @@ # enabling EDP in PortA register "DdiPortAConfig" = "1"
+ register "DdiPortBHpd" = "1" register "DdiPort1Hpd" = "1" register "DdiPort1Ddc" = "1"
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c index cc810aa..2f952d2 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c @@ -24,6 +24,10 @@ PAD_CFG_GPO(GPP_H0, 1, PLTRST),
/* Camera */ + PAD_CFG_NF(GPP_H6, NONE, PLTRST, NF1), /* I2C3_SDA */ + PAD_CFG_NF(GPP_H7, NONE, PLTRST, NF1), /* I2C3_SCL */ + PAD_CFG_NF(GPP_B9, NONE, PLTRST, NF1), /* I2C5_SDA */ + PAD_CFG_NF(GPP_B10, NONE, PLTRST, NF1), /* I2C5_SCL */ PAD_CFG_GPO(GPP_B23, 0, PLTRST), PAD_CFG_GPO(GPP_C15, 0, PLTRST), PAD_CFG_GPO(GPP_E22, 0, PLTRST), @@ -83,6 +87,15 @@ PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2), /* DMIC0_CLK */ PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2), /* DMIC0_DATA */
+ /* DP */ + PAD_CFG_NF(GPP_L_BKLTEN, NONE, PLTRST, NF1), /* L_BKLTEN */ + PAD_CFG_NF(GPP_L_BKLTCTL, NONE, PLTRST, NF1), /* L_BKLTCTL */ + PAD_CFG_NF(GPP_L_VDDEN, NONE, PLTRST, NF1), /* L_VDDEN */ + PAD_CFG_NF(GPP_E14, NONE, PLTRST, NF1), /* HPD_A */ + PAD_CFG_NF(GPP_A18, NONE, PLTRST, NF1), /* HPD_B */ + PAD_CFG_NF(GPP_A19, NONE, PLTRST, NF1), /* HPD_1 */ + PAD_CFG_NF(GPP_E18, NONE, PLTRST, NF1), /* DDP_1_CTRCLK */ + PAD_CFG_NF(GPP_E19, NONE, PLTRST, NF1), /* DDP_1_CTRDATA */ };
const struct pad_config *variant_gpio_table(size_t *num)
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39419 )
Change subject: mb/intel/tglrvp: sync up variant folders with latet up3 ......................................................................
Patch Set 1: Code-Review+1
Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39419 )
Change subject: mb/intel/tglrvp: sync up variant folders with latet up3 ......................................................................
Patch Set 1: Code-Review+2
Shaunak Saha has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39419 )
Change subject: mb/intel/tglrvp: sync up variant folders with latet up3 ......................................................................
Patch Set 1: Code-Review+2
Hello Shaunak Saha, build bot (Jenkins), Furquan Shaikh, Caveh Jalali, Nick Vaccaro, Srinidhi N Kaushik, Raj Astekar,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39419
to look at the new patch set (#2).
Change subject: mb/intel/tglrvp: sync up variant folders with latest up3 ......................................................................
mb/intel/tglrvp: sync up variant folders with latest up3
During intial UP4 patch, below UP3 patches merged same time which should be apply for UP4. https://review.coreboot.org/c/coreboot/+/39201 https://review.coreboot.org/c/coreboot/+/39229 Merge this patches to UP4
BUG=none BRANCH=none TEST=Build TGL UP4
Signed-off-by: Wonkyu Kim wonkyu.kim@intel.com Change-Id: I7b24cb2b0d03309cf67c6c21ddc2031a054f6110 --- M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c 2 files changed, 14 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/39419/2
Hello Shaunak Saha, build bot (Jenkins), Furquan Shaikh, Caveh Jalali, Nick Vaccaro, Srinidhi N Kaushik, Raj Astekar,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39419
to look at the new patch set (#3).
Change subject: mb/intel/tglrvp: sync up variant folders with latest up3 ......................................................................
mb/intel/tglrvp: sync up variant folders with latest up3
During intial UP4 patch, below UP3 patches merged which should be applied for UP4. https://review.coreboot.org/c/coreboot/+/39201 https://review.coreboot.org/c/coreboot/+/39229 Merge these patches to UP4
BUG=none BRANCH=none TEST=Build TGL UP4
Signed-off-by: Wonkyu Kim wonkyu.kim@intel.com Change-Id: I7b24cb2b0d03309cf67c6c21ddc2031a054f6110 --- M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c 2 files changed, 14 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/39419/3
Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39419 )
Change subject: mb/intel/tglrvp: sync up variant folders with latest up3 ......................................................................
Patch Set 3: Code-Review+1
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39419 )
Change subject: mb/intel/tglrvp: sync up variant folders with latest up3 ......................................................................
mb/intel/tglrvp: sync up variant folders with latest up3
During intial UP4 patch, below UP3 patches merged which should be applied for UP4. https://review.coreboot.org/c/coreboot/+/39201 https://review.coreboot.org/c/coreboot/+/39229 Merge these patches to UP4
BUG=none BRANCH=none TEST=Build TGL UP4
Signed-off-by: Wonkyu Kim wonkyu.kim@intel.com Change-Id: I7b24cb2b0d03309cf67c6c21ddc2031a054f6110 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39419 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Caveh Jalali caveh@chromium.org Reviewed-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Reviewed-by: Shaunak Saha shaunak.saha@intel.com --- M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c 2 files changed, 14 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Shaunak Saha: Looks good to me, approved Srinidhi N Kaushik: Looks good to me, approved Caveh Jalali: Looks good to me, but someone else must approve Wonkyu Kim: Looks good to me, but someone else must approve
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index a3539aa..1f05e0e 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -48,6 +48,7 @@ # enabling EDP in PortA register "DdiPortAConfig" = "1"
+ register "DdiPortBHpd" = "1" register "DdiPort1Hpd" = "1" register "DdiPort1Ddc" = "1"
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c index cc810aa..2f952d2 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c @@ -24,6 +24,10 @@ PAD_CFG_GPO(GPP_H0, 1, PLTRST),
/* Camera */ + PAD_CFG_NF(GPP_H6, NONE, PLTRST, NF1), /* I2C3_SDA */ + PAD_CFG_NF(GPP_H7, NONE, PLTRST, NF1), /* I2C3_SCL */ + PAD_CFG_NF(GPP_B9, NONE, PLTRST, NF1), /* I2C5_SDA */ + PAD_CFG_NF(GPP_B10, NONE, PLTRST, NF1), /* I2C5_SCL */ PAD_CFG_GPO(GPP_B23, 0, PLTRST), PAD_CFG_GPO(GPP_C15, 0, PLTRST), PAD_CFG_GPO(GPP_E22, 0, PLTRST), @@ -83,6 +87,15 @@ PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2), /* DMIC0_CLK */ PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2), /* DMIC0_DATA */
+ /* DP */ + PAD_CFG_NF(GPP_L_BKLTEN, NONE, PLTRST, NF1), /* L_BKLTEN */ + PAD_CFG_NF(GPP_L_BKLTCTL, NONE, PLTRST, NF1), /* L_BKLTCTL */ + PAD_CFG_NF(GPP_L_VDDEN, NONE, PLTRST, NF1), /* L_VDDEN */ + PAD_CFG_NF(GPP_E14, NONE, PLTRST, NF1), /* HPD_A */ + PAD_CFG_NF(GPP_A18, NONE, PLTRST, NF1), /* HPD_B */ + PAD_CFG_NF(GPP_A19, NONE, PLTRST, NF1), /* HPD_1 */ + PAD_CFG_NF(GPP_E18, NONE, PLTRST, NF1), /* DDP_1_CTRCLK */ + PAD_CFG_NF(GPP_E19, NONE, PLTRST, NF1), /* DDP_1_CTRDATA */ };
const struct pad_config *variant_gpio_table(size_t *num)
-
Caveh Jalali (Code Review) -
Patrick Georgi (Code Review)
-
Shaunak Saha (Code Review)
-
Srinidhi N Kaushik (Code Review)
-
Wonkyu Kim (Code Review)