Change in coreboot[master]: security/intel/txt/romstage.c: Unlock memory when SCLEAN not needed

[Angel Pons (Code Review)]

Attention is currently required from: Michał Żygowski, Patrick Rudolph.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59521 )

Change subject: security/intel/txt/romstage.c: Unlock memory when SCLEAN not needed
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Patch Set 3:

(1 comment)

File src/security/intel/txt/romstage.c:

https://review.coreboot.org/c/coreboot/+/59521/comment/7466bad9_c475c0e5 
PS3, Line 138: 		wrmsr(TXT_UNLOCK_MEMORY_MSR, msr);
> Yes it does, we have a separate discussion in this patch. […]

I simply don't understand why this is needed. The write in sandybridge native raminit code is unconditionally executed. In which scenario is the native raminit write skipped? I'm pretty sure MRC.bin also does the write.