Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/27089 )
Change subject: mb/asus/p5qpl-am: Add p5g41t-m_lx as a variant ......................................................................
Patch Set 8:
(2 comments)
https://review.coreboot.org/#/c/27089/6/src/mainboard/asus/p5qpl-am/acpi/ich... File src/mainboard/asus/p5qpl-am/acpi/ich7_pci_irqs.asl:
https://review.coreboot.org/#/c/27089/6/src/mainboard/asus/p5qpl-am/acpi/ich... PS6, Line 58: /* PCI1 SLOT 2 */
Not sure, I can give you my DSDT if you want.
Fixed thanks to Arthur's explanations.
https://review.coreboot.org/#/c/27089/6/src/mainboard/asus/p5qpl-am/variants... File src/mainboard/asus/p5qpl-am/variants/p5qpl-am/overridetree.cb:
https://review.coreboot.org/#/c/27089/6/src/mainboard/asus/p5qpl-am/variants... PS6, Line 22: device pnp 2e.1 on # Parallel port
Then what does CB:30242 do? (it's what I based this overridetree out of)
Moved the whole superio chip definition to overridetree.
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Angel Pons (Code Review)