hsin-hsiung wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49005 )
Change subject: WIP: soc/mediatek/mt8192: update initial setting of mt6359 ......................................................................
WIP: soc/mediatek/mt8192: update initial setting of mt6359
Disable RG_PH2_off because vcore is unused. Otherwise, the current of vgpu will be abnormal.
BRANCH=none TEST=boot asurada correctly
Signed-off-by: Hsin-Hsiung Wang hsin-hsiung.wang@mediatek.com Change-Id: I48d3729302de9e3343dce79fe6f5ed045d0296a5 --- M src/soc/mediatek/mt8192/mt6359p.c 1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/49005/1
diff --git a/src/soc/mediatek/mt8192/mt6359p.c b/src/soc/mediatek/mt8192/mt6359p.c index a8e93ca..6ad162a 100644 --- a/src/soc/mediatek/mt8192/mt6359p.c +++ b/src/soc/mediatek/mt8192/mt6359p.c @@ -90,6 +90,7 @@ {0x19AE, 0x6E, 0x7E, 0}, {0x19B0, 0x3C00, 0x3C00, 0}, {0x19B4, 0x20FD, 0xFFFF, 0}, + {0x19DE, 0x1, 0x1, 6}, {0x1A08, 0x4200, 0x4680, 0}, {0x1A0A, 0x6E, 0x7E, 0}, {0x1A0C, 0x3C00, 0x3C00, 0},
Hello Hung-Te Lin,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/49005
to look at the new patch set (#2).
Change subject: WIP: soc/mediatek/mt8192: update initial setting of mt6359p ......................................................................
WIP: soc/mediatek/mt8192: update initial setting of mt6359p
Disable RG_PH2_off because vcore is unused. Otherwise, the current of vgpu will be abnormal.
BRANCH=none TEST=boot asurada correctly
Signed-off-by: Hsin-Hsiung Wang hsin-hsiung.wang@mediatek.com Change-Id: I48d3729302de9e3343dce79fe6f5ed045d0296a5 --- M src/soc/mediatek/mt8192/mt6359p.c 1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/49005/2
Hello Hung-Te Lin, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/49005
to look at the new patch set (#3).
Change subject: WIP: soc/mediatek/mt8192: pmic: update initial setting ......................................................................
WIP: soc/mediatek/mt8192: pmic: update initial setting
Disable RG_PH2_off because vcore is unused. Otherwise, the current of vgpu will be abnormal.
BRANCH=none TEST=boot asurada correctly
Signed-off-by: Hsin-Hsiung Wang hsin-hsiung.wang@mediatek.com Change-Id: I48d3729302de9e3343dce79fe6f5ed045d0296a5 --- M src/soc/mediatek/mt8192/mt6359p.c 1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/49005/3
Hello Hung-Te Lin, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/49005
to look at the new patch set (#4).
Change subject: soc/mediatek/mt8192: pmic: update initial setting ......................................................................
soc/mediatek/mt8192: pmic: update initial setting
Disable RG_PH2_off because vcore is unused. Otherwise, the current of vgpu will be abnormal.
BUG=b:172636735 BRANCH=none TEST=boot asurada correctly
Signed-off-by: Hsin-Hsiung Wang hsin-hsiung.wang@mediatek.com Change-Id: I48d3729302de9e3343dce79fe6f5ed045d0296a5 --- M src/soc/mediatek/mt8192/mt6359p.c 1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/49005/4
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49005 )
Change subject: soc/mediatek/mt8192: pmic: update initial setting ......................................................................
Patch Set 4:
(2 comments)
https://review.coreboot.org/c/coreboot/+/49005/4//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/49005/4//COMMIT_MSG@10 PS4, Line 10: Otherwise, the current of vgpu will be abnormal. Can you please specify the normal and abnormal values?
https://review.coreboot.org/c/coreboot/+/49005/4/src/soc/mediatek/mt8192/mt6... File src/soc/mediatek/mt8192/mt6359p.c:
https://review.coreboot.org/c/coreboot/+/49005/4/src/soc/mediatek/mt8192/mt6... PS4, Line 93: {0x19DE, 0x1, 0x1, 6}, Add a comment behind it, what it does?
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49005 )
Change subject: soc/mediatek/mt8192: pmic: update initial setting ......................................................................
Patch Set 6: Code-Review+1
please rebase so we can let buildbot try .
Hello Hung-Te Lin, build bot (Jenkins), Yidi Lin,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/49005
to look at the new patch set (#10).
Change subject: soc/mediatek/mt8192: pmic: update initial setting ......................................................................
soc/mediatek/mt8192: pmic: update initial setting
We found the switch frequency of vgpu is 4~5Mhz with high current case(>3.5A) and 2.5Mhz with low current case(<2.8A). The root cause is that phase config of vcore doesn't disable, so it will affect the switch frequency of vgpu. Add the phase setting into initial setting.
BUG=b:172636735 BRANCH=none TEST=boot asurada correctly
Signed-off-by: Hsin-Hsiung Wang hsin-hsiung.wang@mediatek.com Change-Id: I48d3729302de9e3343dce79fe6f5ed045d0296a5 --- M src/soc/mediatek/mt8192/mt6359p.c 1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/49005/10
Hello Hung-Te Lin, build bot (Jenkins), Yidi Lin,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/49005
to look at the new patch set (#11).
Change subject: soc/mediatek/mt8192: pmic: update initial setting ......................................................................
soc/mediatek/mt8192: pmic: update initial setting
We found the switch frequency of vgpu is 4~5Mhz with high current case(>3.5A) and 2.5Mhz with low current case(<2.8A). The root cause is that phase config of vcore doesn't disable, so it will affect the switch frequency of vgpu. Add the phase setting into initial setting.
BUG=b:172636735 BRANCH=none TEST=boot asurada correctly
Signed-off-by: Hsin-Hsiung Wang hsin-hsiung.wang@mediatek.com Change-Id: I48d3729302de9e3343dce79fe6f5ed045d0296a5 --- M src/soc/mediatek/mt8192/mt6359p.c 1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/49005/11
Yidi Lin has uploaded a new patch set (#12) to the change originally created by hsin-hsiung wang. ( https://review.coreboot.org/c/coreboot/+/49005 )
Change subject: soc/mediatek/mt8192: pmic: update initial setting ......................................................................
soc/mediatek/mt8192: pmic: update initial setting
We found that the switch frequency of vgpu is at 4~5Mhz with high current case (> 3.5A) and is at 2.5Mhz with low current case(< 2.8A). The switch frequency of vgpu should be kept at 2.5Mhz.
The root cause is that phase config of vcore is not disabled, it will affect the switch frequency of vgpu. Corret the phase setting at initialization.
BUG=b:172636735 BRANCH=none TEST=boot asurada correctly
Signed-off-by: Hsin-Hsiung Wang hsin-hsiung.wang@mediatek.com Change-Id: I48d3729302de9e3343dce79fe6f5ed045d0296a5 --- M src/soc/mediatek/mt8192/mt6359p.c 1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/49005/12
Yidi Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49005 )
Change subject: soc/mediatek/mt8192: pmic: update initial setting ......................................................................
Patch Set 12:
(2 comments)
https://review.coreboot.org/c/coreboot/+/49005/4//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/49005/4//COMMIT_MSG@10 PS4, Line 10: Otherwise, the current of vgpu will be abnormal.
Can you please specify the normal and abnormal values?
Done
https://review.coreboot.org/c/coreboot/+/49005/4/src/soc/mediatek/mt8192/mt6... File src/soc/mediatek/mt8192/mt6359p.c:
https://review.coreboot.org/c/coreboot/+/49005/4/src/soc/mediatek/mt8192/mt6... PS4, Line 93: {0x19DE, 0x1, 0x1, 6},
Add a comment behind it, what it does?
Done
Attention is currently required from: Yidi Lin, hsin-hsiung wang. Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49005 )
Change subject: soc/mediatek/mt8192: pmic: update initial setting ......................................................................
Patch Set 15: Code-Review+2
Attention is currently required from: Yidi Lin, hsin-hsiung wang. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49005 )
Change subject: soc/mediatek/mt8192: pmic: update initial setting ......................................................................
Patch Set 18: Code-Review+2
Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/49005 )
Change subject: soc/mediatek/mt8192: pmic: update initial setting ......................................................................
soc/mediatek/mt8192: pmic: update initial setting
We found that the switch frequency of vgpu is at 4~5Mhz with high current case (> 3.5A) and is at 2.5Mhz with low current case(< 2.8A). The switch frequency of vgpu should be kept at 2.5Mhz.
The root cause is that phase config of vcore is not disabled, it will affect the switch frequency of vgpu. Corret the phase setting at initialization.
BUG=b:172636735 BRANCH=none TEST=boot asurada correctly
Signed-off-by: Hsin-Hsiung Wang hsin-hsiung.wang@mediatek.com Change-Id: I48d3729302de9e3343dce79fe6f5ed045d0296a5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49005 Reviewed-by: Yu-Ping Wu yupingso@google.com Reviewed-by: Hung-Te Lin hungte@chromium.org Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/mediatek/mt8192/mt6359p.c 1 file changed, 1 insertion(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Hung-Te Lin: Looks good to me, approved Yu-Ping Wu: Looks good to me, approved
diff --git a/src/soc/mediatek/mt8192/mt6359p.c b/src/soc/mediatek/mt8192/mt6359p.c index a8e93ca..68af6f2 100644 --- a/src/soc/mediatek/mt8192/mt6359p.c +++ b/src/soc/mediatek/mt8192/mt6359p.c @@ -90,6 +90,7 @@ {0x19AE, 0x6E, 0x7E, 0}, {0x19B0, 0x3C00, 0x3C00, 0}, {0x19B4, 0x20FD, 0xFFFF, 0}, + {0x19DE, 0x1, 0x1, 6}, /* RG_VGPUVCORE_PH2_OFF, disable phase 2 */ {0x1A08, 0x4200, 0x4680, 0}, {0x1A0A, 0x6E, 0x7E, 0}, {0x1A0C, 0x3C00, 0x3C00, 0},
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hsin-hsiung wang (Code Review) -
Hung-Te Lin (Code Review)
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Paul Menzel (Code Review)
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Yidi Lin (Code Review)
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Yu-Ping Wu (Code Review)