Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35369 )
Change subject: mb/asrock/h110m: set I/O Range for SuperIO HWM ......................................................................
mb/asrock/h110m: set I/O Range for SuperIO HWM
Change-Id: I30de4f40f8ca87c54faee84053c4bb0f874b2884 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/mainboard/asrock/h110m/devicetree.cb 1 file changed, 3 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/35369/1
diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index 5af5cfc..8ed3476 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -33,6 +33,9 @@ register "gpe0_dw1" = "GPP_D" register "gpe0_dw2" = "GPP_E"
+ # Set @0x200-0x2ff I/O Range for SuperIO HWM + register "gen1_dec" = "0x00fc0201" + # Enable "Intel Speed Shift Technology" register "speed_shift_enable" = "1"
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35369 )
Change subject: mb/asrock/h110m: set I/O Range for SuperIO HWM ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35369/1/src/mainboard/asrock/h110m/... File src/mainboard/asrock/h110m/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/35369/1/src/mainboard/asrock/h110m/... PS1, Line 37: register "gen1_dec" = "0x00fc0201" it starts at 0x0290, can you decode 0x0280 - 0x0300 instead?
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35369
to look at the new patch set (#2).
Change subject: mb/asrock/h110m: set I/O Range for SuperIO HWM ......................................................................
mb/asrock/h110m: set I/O Range for SuperIO HWM
Change-Id: I30de4f40f8ca87c54faee84053c4bb0f874b2884 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/mainboard/asrock/h110m/devicetree.cb 1 file changed, 3 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/35369/2
Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35369 )
Change subject: mb/asrock/h110m: set I/O Range for SuperIO HWM ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35369/1/src/mainboard/asrock/h110m/... File src/mainboard/asrock/h110m/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/35369/1/src/mainboard/asrock/h110m/... PS1, Line 37: register "gen1_dec" = "0x00fc0201"
it starts at 0x0290, can you decode 0x0280 - 0x0300 instead?
Done
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35369 )
Change subject: mb/asrock/h110m: set I/O Range for SuperIO HWM ......................................................................
Patch Set 3: Code-Review+2
Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/35369 )
Change subject: mb/asrock/h110m: set I/O Range for SuperIO HWM ......................................................................
mb/asrock/h110m: set I/O Range for SuperIO HWM
Change-Id: I30de4f40f8ca87c54faee84053c4bb0f874b2884 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/35369 Reviewed-by: Felix Held felix-coreboot@felixheld.de Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/asrock/h110m/devicetree.cb 1 file changed, 3 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved
diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index b4e6a02..eed67b7 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -33,6 +33,9 @@ register "gpe0_dw1" = "GPP_D" register "gpe0_dw2" = "GPP_E"
+ # Set @0x280-0x2ff I/O Range for SuperIO HWM + register "gen1_dec" = "0x007c0281" + # Enable "Intel Speed Shift Technology" register "speed_shift_enable" = "1"
-
Felix Held (Code Review) -
Maxim Polyakov (Code Review)
-
Patrick Rudolph (Code Review)