[S] Change in coreboot[main]: arch/riscv: Add common FDT build

[Matt DeVillier (Code Review)]

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83848?usp=email )

Change subject: arch/riscv: Add common FDT build
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arch/riscv: Add common FDT build

Currently all platforms on RISC-V require a FDT.
The inclusion of the FDT is currently done in the platform Makefiles.
In order to factor out some common code this patch adds the inclusion
in the architecture Makefile. The FDT must be aligned to 8 byte
according to device tree spec. It avoids misaligned access.

Signed-off-by: Maximilian Brune 
Change-Id: I3b304a89646fe84c98e9f199f315bebb156de16c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83848
Tested-by: build bot (Jenkins) 
Reviewed-by: Matt DeVillier 
---
M src/arch/riscv/Kconfig
M src/arch/riscv/Makefile.mk
2 files changed, 38 insertions(+), 0 deletions(-)

Approvals:
  Matt DeVillier: Looks good to me, approved
  build bot (Jenkins): Verified

diff --git a/src/arch/riscv/Kconfig b/src/arch/riscv/Kconfig
index b7fc0ca..8fa7854 100644
--- a/src/arch/riscv/Kconfig
+++ b/src/arch/riscv/Kconfig
@@ -144,4 +144,19 @@
      SOC/Mainboards select this option in case the number of harts is not known at
      build time. In this case the SOC must have a scheme in place to discover all harts.

+config RISCV_DTS
+	bool
+	default n
+	help
+	  This option is selected by mainboards that include a devicetree
+	  source file (not to be confused with the coreboot devicetree.cb files).
+	  The devicetree will be preprocessed and compiled into a FDT (flattened devicetree).
+	  Said FDT will be put into a CBFS file for use in runtime.
+
+config RISCV_DTS_FILE
+	string
+	depends on RISCV_DTS
+	help
+	  Path to the devicetree source file in .dts format.
+
 endif # if ARCH_RISCV
diff --git a/src/arch/riscv/Makefile.mk b/src/arch/riscv/Makefile.mk
index bda392a..3efd895 100644
--- a/src/arch/riscv/Makefile.mk
+++ b/src/arch/riscv/Makefile.mk
@@ -67,6 +67,29 @@
    $(top)/src/lib/memset.c
 all-$(CONFIG_RISCV_USE_ARCH_TIMER) += arch_timer.c

+## FDT (Flattened Devicetree) inclusion
+
+ifeq ($(CONFIG_RISCV_DTS),y)
+
+# at some point dtc may be compiled by our toolchain
+DTC ?= dtc
+CPPFLAGS_dts += -nostdinc -P -x assembler-with-cpp -I src/arch/riscv/include
+
+$(obj)/preprocessed.dts: $(call strip_quotes, $(CONFIG_RISCV_DTS_FILE))
+	$(CPP_riscv) $(CPPFLAGS_dts) -o $@ $<
+
+$(obj)/dtb: $(obj)/preprocessed.dts
+	$(DTC) -I dts -O dtb -o $@ $<
+
+# This may be optimized in the future by letting cbfstool parse our FDT into a unflattened
+# devicetree blob in build time, so that we only need to flatten it in runtime instead of
+# unflatten and flatten it in runtime.
+cbfs-files-y += DTB
+DTB-file := $(obj)/dtb
+DTB-type := raw
+DTB-align := 8 # according to spec device trees needs to be 8 byte aligned
+
+endif # CONFIG_RISCV_DTS

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