Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Arthur Heymans, Patrick Rudolph.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56717 )
Change subject: soc/intel/common: Calculate and configure SF Mask 2
......................................................................
Patch Set 7:
(1 comment)
File src/soc/intel/common/block/cpu/car/cache_as_ram.S:
https://review.coreboot.org/c/coreboot/+/56717/comment/76c0dd06_6777e68c
PS5, Line 543: wrmsr
CPU: ID 906a0, Alderlake Platform, ucode: 00000019 […]
@Tim, I have tried latest ucode as well, no issue seen on few units we have tested this patchtress.
coreboot-4.14-1299-g119097c-dirty Wed Aug 4 18:19:21 UTC 2021 bootblock starting (log level: 8)...
0xc91 hi =0 low = ffe
0x1891 hi =0 low = ffe
0xc92 hi =0 low = 1
0x1892 hi =0 low = 1
0xc85 hi =0 low = 1
0xc87 hi =0 low = c
CPU: Genuine Intel(R) 0000
CPU: ID 906a0, Alderlake Platform, ucode: 0000001c
CPU: AES supported, TXT supported, VT supported
Cache: Level 3: Associativity = 12 Partitions = 1 Line Size = 64 Sets = 16384
Cache: Size=12 MiB
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