Patch merged into coreboot/master: nb/amd/mct_ddr3: Set the NBP0 read latency from P0 trained values

the following patch was just integrated into master:
commit 54accfe0d6a693299c5f79f254c30d9ba68c38fa
Author: Timothy Pearson 
Date:   Mon Mar 21 13:22:37 2016 -0500

nb/amd/mct_ddr3: Set the NBP0 read latency from P0 trained values

During maximum read latency training on Family 15h processors,
    the maximum read latency was incorrectly set from the NBP1
    value instead of the correct NBP0 value.

Modify maximimum read latency training to explicitly operate
    on the NBP0 value, and store the previously calculated NBP1
    value for reference by other portions of the training algorithm.

Change-Id: I5d4a6c2def83df3e23f1a4c598314c31a0172cd7
    Signed-off-by: Timothy Pearson 
    Reviewed-on: https://review.coreboot.org/14150
    Reviewed-by: Martin Roth 
    Tested-by: build bot (Jenkins)
    Tested-by: Raptor Engineering Automated Test Stand

See https://review.coreboot.org/14150 for details.

-gerrit