Werner Zeh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55698 )
Change subject: mb/asus/p5q_se: Add initial support ......................................................................
mb/asus/p5q_se: Add initial support
This motherboard is almost identical to the ASUS P5QL PRO, with the only noticeable difference being that the ASUS P5Q SE has a P45 MCH while the P5QL PRO has a P43 MCH. Few changes were required.
Signed-off-by: Hunter Sell alicelyralain@gmail.com Change-Id: I36612bac16a79f05f3fe57e535e4ba3c73790a86 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55698 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/asus/p5qc/Kconfig M src/mainboard/asus/p5qc/Kconfig.name A src/mainboard/asus/p5qc/variants/p5q_se/devicetree.cb A src/mainboard/asus/p5qc/variants/p5q_se/gpio.c 4 files changed, 267 insertions(+), 2 deletions(-)
Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved
diff --git a/src/mainboard/asus/p5qc/Kconfig b/src/mainboard/asus/p5qc/Kconfig index a0fddfb..defe15e 100644 --- a/src/mainboard/asus/p5qc/Kconfig +++ b/src/mainboard/asus/p5qc/Kconfig @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only
-if BOARD_ASUS_P5QC || BOARD_ASUS_P5Q_PRO || BOARD_ASUS_P5QL_PRO || BOARD_ASUS_P5Q +if BOARD_ASUS_P5QC || BOARD_ASUS_P5Q_PRO || BOARD_ASUS_P5QL_PRO || BOARD_ASUS_P5Q_SE || BOARD_ASUS_P5Q
config BOARD_SPECIFIC_OPTIONS def_bool y @@ -24,6 +24,7 @@ default "p5qc" if BOARD_ASUS_P5QC default "p5q_pro" if BOARD_ASUS_P5Q_PRO default "p5ql_pro" if BOARD_ASUS_P5QL_PRO + default "p5q_se" if BOARD_ASUS_P5Q_SE default "p5q" if BOARD_ASUS_P5Q
config MAINBOARD_PART_NUMBER @@ -31,6 +32,7 @@ default "P5QC" if BOARD_ASUS_P5QC default "P5Q PRO" if BOARD_ASUS_P5Q_PRO default "P5QL PRO" if BOARD_ASUS_P5QL_PRO + default "P5Q SE" if BOARD_ASUS_P5Q_SE default "P5Q" if BOARD_ASUS_P5Q
config DEVICETREE @@ -39,6 +41,7 @@
config GPIO_C string + default "variants/p5q_se/gpio.c" if BOARD_ASUS_P5Q_SE default "variants/p5ql_pro/gpio.c" if BOARD_ASUS_P5QL_PRO default "gpio.c"
@@ -49,7 +52,7 @@
config PAYLOAD_CONFIGFILE string - default "" if PAYLOAD_SEABIOS && BOARD_ASUS_P5QL_PRO + default "" if PAYLOAD_SEABIOS && (BOARD_ASUS_P5QL_PRO || BOARD_ASUS_P5Q_SE) default "$(top)/src/mainboard/$(MAINBOARDDIR)/config_seabios" if PAYLOAD_SEABIOS
endif # BOARD_ASUS_P5Q* diff --git a/src/mainboard/asus/p5qc/Kconfig.name b/src/mainboard/asus/p5qc/Kconfig.name index 22c0cca..07e340c 100644 --- a/src/mainboard/asus/p5qc/Kconfig.name +++ b/src/mainboard/asus/p5qc/Kconfig.name @@ -7,5 +7,8 @@ config BOARD_ASUS_P5QL_PRO bool "P5QL PRO"
+config BOARD_ASUS_P5Q_SE + bool "P5Q SE" + config BOARD_ASUS_P5Q bool "P5Q" diff --git a/src/mainboard/asus/p5qc/variants/p5q_se/devicetree.cb b/src/mainboard/asus/p5qc/variants/p5q_se/devicetree.cb new file mode 100644 index 0000000..01de13f --- /dev/null +++ b/src/mainboard/asus/p5qc/variants/p5q_se/devicetree.cb @@ -0,0 +1,112 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +chip northbridge/intel/x4x # Northbridge + device cpu_cluster 0 on # APIC cluster + chip cpu/intel/socket_LGA775 + device lapic 0 on end + end + chip cpu/intel/model_1067x # CPU + device lapic 0xacac off end + end + end + device domain 0 on # PCI domain + device pci 0.0 on end # Host Bridge + device pci 1.0 on end # PEG + device pci 2.0 off end # Integrated graphics controller + device pci 2.1 off end # Integrated graphics controller 2 + device pci 3.0 off end # ME + device pci 3.1 off end # ME + device pci 3.2 off end # ME + device pci 3.3 off end # ME + device pci 6.0 off end # PEG 2 + chip southbridge/intel/i82801jx # Southbridge + register "gpe0_en" = "0x40" + + register "sata_port_map" = "0x3f" + + # Enable PCIe ports 0,2,3 as slots. + register "pcie_slot_implemented" = "0x31" + + register "gen1_dec" = "0x00000295" + register "gen2_dec" = "0x001c4701" + + device pci 19.0 off end # GBE + device pci 1a.0 on end # USB + device pci 1a.1 on end # USB + device pci 1a.2 on end # USB + device pci 1a.7 on end # USB + device pci 1b.0 on end # Audio + device pci 1c.0 on end # PCIe 1 PCIe x1 Slot #1 + device pci 1c.1 on end # PCIe 2 PCIe x1 Slot #2 + device pci 1c.2 off end # PCIe 3 + device pci 1c.3 off end # PCIe 4 + device pci 1c.4 on end # PCIe 5 Marvell IDE + device pci 1c.5 on end # PCIe 6 Atheros LAN + device pci 1d.0 on end # USB + device pci 1d.1 on end # USB + device pci 1d.2 on end # USB + device pci 1d.7 on end # USB + device pci 1e.0 on end # PCI bridge + device pci 1f.0 on # LPC bridge + chip superio/winbond/w83667hg-a # Super I/O + device pnp 2e.0 on # FDC + # Global registers + irq 0x2a = 0x30 + irq 0x2c = 0x22 + irq 0x2d = 0x00 + io 0x60 = 0x3f0 + irq 0x70 = 0x06 + end + device pnp 2e.1 off end # LPT1 + device pnp 2e.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off end # COM2 + device pnp 2e.5 on # PS/2 keyboard & mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.106 off end # SPI1 + device pnp 2e.107 off end # GPIO6 + device pnp 2e.207 off end # GPIO7 + device pnp 2e.307 on # GPIO8 + irq 0xe4 = 0xfb + irq 0xe5 = 0x82 + end + device pnp 2e.407 off end # GPIO9 + device pnp 2e.8 off end # WDT + device pnp 2e.108 off end # GPIO1 + device pnp 2e.9 off end # GPIO2 + device pnp 2e.109 on end # GPIO3 + device pnp 2e.209 on # GPIO4 + irq 0xf0 = 0xff + irq 0xfe = 0x07 + end + device pnp 2e.309 on end # GPIO5 + device pnp 2e.a on # ACPI + irq 0xe4 = 0x10 # 3VSBSW# enable + irq 0xe5 = 0x02 + irq 0xf2 = 0xfc + end + device pnp 2e.b on # HW Monitor + io 0x60 = 0x290 + irq 0x70 = 0x0 + # IRQ purposefully not assigned to prevent lockups + end + device pnp 2e.c on end # PECI + device pnp 2e.d on end # VID_BUSSEL + device pnp 2e.f on end # GPIO_PP_OD + end + end + device pci 1f.1 off end # PATA/IDE + device pci 1f.2 on end # SATA + device pci 1f.3 on end # SMbus + device pci 1f.4 off end + device pci 1f.5 off end # IDE + device pci 1f.6 on end # Thermal + end + end +end diff --git a/src/mainboard/asus/p5qc/variants/p5q_se/gpio.c b/src/mainboard/asus/p5qc/variants/p5q_se/gpio.c new file mode 100644 index 0000000..53d089b --- /dev/null +++ b/src/mainboard/asus/p5qc/variants/p5q_se/gpio.c @@ -0,0 +1,147 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_GPIO, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_GPIO, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_GPIO, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_GPIO, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio1 = GPIO_DIR_OUTPUT, + .gpio2 = GPIO_DIR_OUTPUT, + .gpio3 = GPIO_DIR_OUTPUT, + .gpio4 = GPIO_DIR_OUTPUT, + .gpio5 = GPIO_DIR_OUTPUT, + .gpio6 = GPIO_DIR_OUTPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio9 = GPIO_DIR_OUTPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_OUTPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_OUTPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_OUTPUT, + .gpio18 = GPIO_DIR_OUTPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio20 = GPIO_DIR_OUTPUT, + .gpio21 = GPIO_DIR_OUTPUT, + .gpio22 = GPIO_DIR_OUTPUT, + .gpio23 = GPIO_DIR_OUTPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_OUTPUT, + .gpio28 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio1 = GPIO_LEVEL_HIGH, + .gpio2 = GPIO_LEVEL_HIGH, + .gpio3 = GPIO_LEVEL_HIGH, + .gpio4 = GPIO_LEVEL_HIGH, + .gpio5 = GPIO_LEVEL_HIGH, + .gpio6 = GPIO_LEVEL_HIGH, + .gpio9 = GPIO_LEVEL_LOW, + .gpio11 = GPIO_LEVEL_HIGH, + .gpio12 = GPIO_LEVEL_LOW, + .gpio14 = GPIO_LEVEL_HIGH, + .gpio17 = GPIO_LEVEL_HIGH, + .gpio18 = GPIO_LEVEL_HIGH, + .gpio20 = GPIO_LEVEL_HIGH, + .gpio21 = GPIO_LEVEL_HIGH, + .gpio22 = GPIO_LEVEL_HIGH, + .gpio23 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_LOW, + .gpio27 = GPIO_LEVEL_HIGH, + .gpio28 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio7 = GPIO_INVERT, + .gpio10 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_GPIO, + .gpio57 = GPIO_MODE_GPIO, + .gpio60 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_OUTPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio36 = GPIO_DIR_OUTPUT, + .gpio37 = GPIO_DIR_OUTPUT, + .gpio38 = GPIO_DIR_OUTPUT, + .gpio39 = GPIO_DIR_OUTPUT, + .gpio48 = GPIO_DIR_OUTPUT, + .gpio49 = GPIO_DIR_OUTPUT, + .gpio56 = GPIO_DIR_OUTPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, + .gpio34 = GPIO_LEVEL_LOW, + .gpio35 = GPIO_LEVEL_LOW, + .gpio36 = GPIO_LEVEL_HIGH, + .gpio37 = GPIO_LEVEL_HIGH, + .gpio38 = GPIO_LEVEL_HIGH, + .gpio39 = GPIO_LEVEL_HIGH, + .gpio48 = GPIO_LEVEL_LOW, + .gpio49 = GPIO_LEVEL_HIGH, + .gpio56 = GPIO_LEVEL_HIGH, + .gpio60 = GPIO_LEVEL_HIGH, +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .invert = &pch_gpio_set1_invert, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + }, +};
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Werner Zeh (Code Review)