Change in coreboot[master]: src/sb/intel/common/spi.c: Adapt and link in romstage

[Arthur Heymans (Code Review)]

Hello build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/25414

to look at the new patch set (#2).

Change subject: src/sb/intel/common/spi.c: Adapt and link in romstage
......................................................................

src/sb/intel/common/spi.c: Adapt and link in romstage

Based on Nicola Corna's work.

This allows for CONFIG_CONSOLE_SPI_FLASH to be used, which writes the
console output to the SPI flash.

TESTED to still work in ramstage on x220 (correctly writes MRC CACHE),
the option CONFIG_CONSOLE_SPI_FLASH compiles for targets using the
common Intel SPI code (untested though).

Change-Id: I4671653c0b07ab5c4bf91128f18f142ce4f893cf
Signed-off-by: Arthur Heymans 
---
M src/southbridge/intel/common/Makefile.inc
M src/southbridge/intel/common/spi.c
2 files changed, 101 insertions(+), 85 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/25414/2