Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39723 )
Change subject: nb/intel/sandybridge: Rewrite table accessors ......................................................................
nb/intel/sandybridge: Rewrite table accessors
That way, sandybridge and ivybridge use the same function signatures.
Tested on Asus P8Z77-V LX2, still boots with i7-2600 and i5-3330.
Change-Id: Idd7c119b2aa291e6396e12fb29effaf3ec73108a Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/northbridge/intel/sandybridge/raminit_ivy.c M src/northbridge/intel/sandybridge/raminit_sandy.c 2 files changed, 113 insertions(+), 75 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/39723/1
diff --git a/src/northbridge/intel/sandybridge/raminit_ivy.c b/src/northbridge/intel/sandybridge/raminit_ivy.c index a714e53..b5bac59 100644 --- a/src/northbridge/intel/sandybridge/raminit_ivy.c +++ b/src/northbridge/intel/sandybridge/raminit_ivy.c @@ -39,167 +39,167 @@ return FRQ; }
-/* Get REFI based on MC frequency, tREFI = 7.8usec */ -static u32 get_REFI(u32 tCK, u8 base_freq) +/* Get REFI based on frequency index, tREFI = 7.8usec */ +static u32 get_REFI(u32 FRQ, u8 base_freq) { if (base_freq == 100) { static const u32 frq_xs_map[] = { /* FRQ: 7, 8, 9, 10, 11, 12, */ 5460, 6240, 7020, 7800, 8580, 9360, }; - return frq_xs_map[get_FRQ(tCK, 100) - 7]; + return frq_xs_map[FRQ - 7];
} else { static const u32 frq_refi_map[] = { /* FRQ: 3, 4, 5, 6, 7, 8, 9, 10, */ 3120, 4160, 5200, 6240, 7280, 8320, 9360, 10400, }; - return frq_refi_map[get_FRQ(tCK, 133) - 3]; + return frq_refi_map[FRQ - 3]; } }
-/* Get XSOffset based on MC frequency, tXS-Offset: tXS = tRFC + 10ns */ -static u8 get_XSOffset(u32 tCK, u8 base_freq) +/* Get XSOffset based on frequency index, tXS-Offset: tXS = tRFC + 10ns */ +static u8 get_XSOffset(u32 FRQ, u8 base_freq) { if (base_freq == 100) { static const u8 frq_xs_map[] = { /* FRQ: 7, 8, 9, 10, 11, 12, */ 7, 8, 9, 10, 11, 12, }; - return frq_xs_map[get_FRQ(tCK, 100) - 7]; + return frq_xs_map[FRQ - 7];
} else { static const u8 frq_xs_map[] = { /* FRQ: 3, 4, 5, 6, 7, 8, 9, 10, */ 4, 6, 7, 8, 10, 11, 12, 14, }; - return frq_xs_map[get_FRQ(tCK, 133) - 3]; + return frq_xs_map[FRQ - 3]; } }
-/* Get MOD based on MC frequency */ -static u8 get_MOD(u32 tCK, u8 base_freq) +/* Get MOD based on frequency index */ +static u8 get_MOD(u32 FRQ, u8 base_freq) { if (base_freq == 100) { static const u8 frq_mod_map[] = { /* FRQ: 7, 8, 9, 10, 11, 12, */ 12, 12, 14, 15, 17, 18, }; - return frq_mod_map[get_FRQ(tCK, 100) - 7]; + return frq_mod_map[FRQ - 7];
} else { static const u8 frq_mod_map[] = { /* FRQ: 3, 4, 5, 6, 7, 8, 9, 10, */ 12, 12, 12, 12, 15, 16, 18, 20, }; - return frq_mod_map[get_FRQ(tCK, 133) - 3]; + return frq_mod_map[FRQ - 3]; } }
-/* Get Write Leveling Output delay based on MC frequency */ -static u8 get_WLO(u32 tCK, u8 base_freq) +/* Get Write Leveling Output delay based on frequency index */ +static u8 get_WLO(u32 FRQ, u8 base_freq) { if (base_freq == 100) { static const u8 frq_wlo_map[] = { /* FRQ: 7, 8, 9, 10, 11, 12, */ 6, 6, 7, 8, 9, 9, }; - return frq_wlo_map[get_FRQ(tCK, 100) - 7]; + return frq_wlo_map[FRQ - 7];
} else { static const u8 frq_wlo_map[] = { /* FRQ: 3, 4, 5, 6, 7, 8, 9, 10, */ 4, 5, 6, 6, 8, 8, 9, 10, }; - return frq_wlo_map[get_FRQ(tCK, 133) - 3]; + return frq_wlo_map[FRQ - 3]; } }
-/* Get CKE based on MC frequency */ -static u8 get_CKE(u32 tCK, u8 base_freq) +/* Get CKE based on frequency index */ +static u8 get_CKE(u32 FRQ, u8 base_freq) { if (base_freq == 100) { static const u8 frq_cke_map[] = { /* FRQ: 7, 8, 9, 10, 11, 12, */ 4, 4, 5, 5, 6, 6, }; - return frq_cke_map[get_FRQ(tCK, 100) - 7]; + return frq_cke_map[FRQ - 7];
} else { static const u8 frq_cke_map[] = { /* FRQ: 3, 4, 5, 6, 7, 8, 9, 10, */ 3, 3, 4, 4, 5, 6, 6, 7, }; - return frq_cke_map[get_FRQ(tCK, 133) - 3]; + return frq_cke_map[FRQ - 3]; } }
-/* Get XPDLL based on MC frequency */ -static u8 get_XPDLL(u32 tCK, u8 base_freq) +/* Get XPDLL based on frequency index */ +static u8 get_XPDLL(u32 FRQ, u8 base_freq) { if (base_freq == 100) { static const u8 frq_xpdll_map[] = { /* FRQ: 7, 8, 9, 10, 11, 12, */ 17, 20, 22, 24, 27, 32, }; - return frq_xpdll_map[get_FRQ(tCK, 100) - 7]; + return frq_xpdll_map[FRQ - 7];
} else { static const u8 frq_xpdll_map[] = { /* FRQ: 3, 4, 5, 6, 7, 8, 9, 10, */ 10, 13, 16, 20, 23, 26, 29, 32, }; - return frq_xpdll_map[get_FRQ(tCK, 133) - 3]; + return frq_xpdll_map[FRQ - 3]; } }
-/* Get XP based on MC frequency */ -static u8 get_XP(u32 tCK, u8 base_freq) +/* Get XP based on frequency index */ +static u8 get_XP(u32 FRQ, u8 base_freq) { if (base_freq == 100) { static const u8 frq_xp_map[] = { /* FRQ: 7, 8, 9, 10, 11, 12, */ 5, 5, 6, 6, 7, 8, }; - return frq_xp_map[get_FRQ(tCK, 100) - 7]; + return frq_xp_map[FRQ - 7]; } else {
static const u8 frq_xp_map[] = { /* FRQ: 3, 4, 5, 6, 7, 8, 9, 10, */ 3, 4, 4, 5, 6, 7, 8, 8 }; - return frq_xp_map[get_FRQ(tCK, 133) - 3]; + return frq_xp_map[FRQ - 3]; } }
-/* Get AONPD based on MC frequency */ -static u8 get_AONPD(u32 tCK, u8 base_freq) +/* Get AONPD based on frequency index */ +static u8 get_AONPD(u32 FRQ, u8 base_freq) { if (base_freq == 100) { static const u8 frq_aonpd_map[] = { /* FRQ: 7, 8, 9, 10, 11, 12, */ 6, 8, 8, 9, 10, 11, }; - return frq_aonpd_map[get_FRQ(tCK, 100) - 7]; + return frq_aonpd_map[FRQ - 7];
} else { static const u8 frq_aonpd_map[] = { /* FRQ: 3, 4, 5, 6, 7, 8, 9, 10, */ 4, 5, 6, 8, 8, 10, 11, 12, }; - return frq_aonpd_map[get_FRQ(tCK, 133) - 3]; + return frq_aonpd_map[FRQ - 3]; } }
-/* Get COMP2 based on MC frequency */ -static u32 get_COMP2(u32 tCK, u8 base_freq) +/* Get COMP2 based on frequency index */ +static u32 get_COMP2(u32 FRQ, u8 base_freq) { if (base_freq == 100) { static const u32 frq_comp2_map[] = { // FRQ: 7, 8, 9, 10, 11, 12, 0x0CA8C264, 0x0C6671E4, 0x0C6671E4, 0x0C446964, 0x0C235924, 0x0C235924, }; - return frq_comp2_map[get_FRQ(tCK, 100) - 7]; + return frq_comp2_map[FRQ - 7];
} else { static const u32 frq_comp2_map[] = { @@ -209,7 +209,7 @@ /* FRQ: 7, 8, 9, 10, */ 0x0C446964, 0x0C235924, 0x0C235924, 0x0C235924, }; - return frq_comp2_map[get_FRQ(tCK, 133) - 3]; + return frq_comp2_map[FRQ - 3]; } }
@@ -457,14 +457,16 @@ ctrl->tRFC = DIV_ROUND_UP(ctrl->tRFC, ctrl->tCK); printk(BIOS_DEBUG, "Selected tRFC : %uT\n", ctrl->tRFC);
- ctrl->tREFI = get_REFI(ctrl->tCK, ctrl->base_freq); - ctrl->tMOD = get_MOD(ctrl->tCK, ctrl->base_freq); - ctrl->tXSOffset = get_XSOffset(ctrl->tCK, ctrl->base_freq); - ctrl->tWLO = get_WLO(ctrl->tCK, ctrl->base_freq); - ctrl->tCKE = get_CKE(ctrl->tCK, ctrl->base_freq); - ctrl->tXPDLL = get_XPDLL(ctrl->tCK, ctrl->base_freq); - ctrl->tXP = get_XP(ctrl->tCK, ctrl->base_freq); - ctrl->tAONPD = get_AONPD(ctrl->tCK, ctrl->base_freq); + const u32 FRQ = get_FRQ(ctrl->tCK, ctrl->base_freq); + + ctrl->tREFI = get_REFI(FRQ, ctrl->base_freq); + ctrl->tMOD = get_MOD(FRQ, ctrl->base_freq); + ctrl->tXSOffset = get_XSOffset(FRQ, ctrl->base_freq); + ctrl->tWLO = get_WLO(FRQ, ctrl->base_freq); + ctrl->tCKE = get_CKE(FRQ, ctrl->base_freq); + ctrl->tXPDLL = get_XPDLL(FRQ, ctrl->base_freq); + ctrl->tXP = get_XP(FRQ, ctrl->base_freq); + ctrl->tAONPD = get_AONPD(FRQ, ctrl->base_freq); }
static void dram_freq(ramctr_timing *ctrl) @@ -526,6 +528,7 @@
static void dram_ioregs(ramctr_timing *ctrl) { + const u32 FRQ = get_FRQ(ctrl->tCK, ctrl->base_freq); u32 reg;
int channel; @@ -553,7 +556,7 @@ printram("done\n");
/* Set COMP2 */ - MCHBAR32(CRCOMPOFST2) = get_COMP2(ctrl->tCK, ctrl->base_freq); + MCHBAR32(CRCOMPOFST2) = get_COMP2(FRQ, ctrl->base_freq); printram("COMP2 done\n");
/* Set COMP1 */ diff --git a/src/northbridge/intel/sandybridge/raminit_sandy.c b/src/northbridge/intel/sandybridge/raminit_sandy.c index 353462d..550fc33 100644 --- a/src/northbridge/intel/sandybridge/raminit_sandy.c +++ b/src/northbridge/intel/sandybridge/raminit_sandy.c @@ -19,9 +19,12 @@ #include "raminit_common.h"
/* Frequency multiplier */ -static u32 get_FRQ(u32 tCK) +static u32 get_FRQ(u32 tCK, u8 base_freq) { - const u32 FRQ = 256000 / (tCK * BASEFREQ); + if (base_freq != BASEFREQ) + die("Wrong base_freq for sandybridge."); + + const u32 FRQ = 256000 / (tCK * base_freq);
if (FRQ > 8) return 8; @@ -32,93 +35,120 @@ }
/* Get REFI based on MC frequency */ -static u32 get_REFI(u32 tCK) +static u32 get_REFI(u32 FRQ, u8 base_freq) { + if (base_freq != BASEFREQ) + die("Wrong base_freq for sandybridge."); + static const u32 frq_refi_map[] = { /* FRQ: 3, 4, 5, 6, 7, 8, */ 3120, 4160, 5200, 6240, 7280, 8320, }; - return frq_refi_map[get_FRQ(tCK) - 3]; + return frq_refi_map[FRQ - 3]; }
/* Get XSOffset based on MC frequency */ -static u8 get_XSOffset(u32 tCK) +static u8 get_XSOffset(u32 FRQ, u8 base_freq) { + if (base_freq != BASEFREQ) + die("Wrong base_freq for sandybridge."); + static const u8 frq_xs_map[] = { /* FRQ: 3, 4, 5, 6, 7, 8, */ 4, 6, 7, 8, 10, 11, }; - return frq_xs_map[get_FRQ(tCK) - 3]; + return frq_xs_map[FRQ - 3]; }
/* Get MOD based on MC frequency */ -static u8 get_MOD(u32 tCK) +static u8 get_MOD(u32 FRQ, u8 base_freq) { + if (base_freq != BASEFREQ) + die("Wrong base_freq for sandybridge."); + static const u8 frq_mod_map[] = { /* FRQ: 3, 4, 5, 6, 7, 8, */ 12, 12, 12, 12, 15, 16, }; - return frq_mod_map[get_FRQ(tCK) - 3]; + return frq_mod_map[FRQ - 3]; }
/* Get Write Leveling Output delay based on MC frequency */ -static u8 get_WLO(u32 tCK) +static u8 get_WLO(u32 FRQ, u8 base_freq) { + if (base_freq != BASEFREQ) + die("Wrong base_freq for sandybridge."); + static const u8 frq_wlo_map[] = { /* FRQ: 3, 4, 5, 6, 7, 8, */ 4, 5, 6, 6, 8, 8, }; - return frq_wlo_map[get_FRQ(tCK) - 3]; + return frq_wlo_map[FRQ - 3]; }
/* Get CKE based on MC frequency */ -static u8 get_CKE(u32 tCK) +static u8 get_CKE(u32 FRQ, u8 base_freq) { + if (base_freq != BASEFREQ) + die("Wrong base_freq for sandybridge."); + static const u8 frq_cke_map[] = { /* FRQ: 3, 4, 5, 6, 7, 8, */ 3, 3, 4, 4, 5, 6, }; - return frq_cke_map[get_FRQ(tCK) - 3]; + return frq_cke_map[FRQ - 3]; }
/* Get XPDLL based on MC frequency */ -static u8 get_XPDLL(u32 tCK) +static u8 get_XPDLL(u32 FRQ, u8 base_freq) { + if (base_freq != BASEFREQ) + die("Wrong base_freq for sandybridge."); + static const u8 frq_xpdll_map[] = { /* FRQ: 3, 4, 5, 6, 7, 8, */ 10, 13, 16, 20, 23, 26, }; - return frq_xpdll_map[get_FRQ(tCK) - 3]; + return frq_xpdll_map[FRQ - 3]; }
/* Get XP based on MC frequency */ -static u8 get_XP(u32 tCK) +static u8 get_XP(u32 FRQ, u8 base_freq) { + if (base_freq != BASEFREQ) + die("Wrong base_freq for sandybridge."); + static const u8 frq_xp_map[] = { /* FRQ: 3, 4, 5, 6, 7, 8, */ 3, 4, 4, 5, 6, 7, }; - return frq_xp_map[get_FRQ(tCK) - 3]; + return frq_xp_map[FRQ - 3]; }
/* Get AONPD based on MC frequency */ -static u8 get_AONPD(u32 tCK) +static u8 get_AONPD(u32 FRQ, u8 base_freq) { + if (base_freq != BASEFREQ) + die("Wrong base_freq for sandybridge."); + static const u8 frq_aonpd_map[] = { /* FRQ: 3, 4, 5, 6, 7, 8, */ 4, 5, 6, 8, 8, 10, }; - return frq_aonpd_map[get_FRQ(tCK) - 3]; + return frq_aonpd_map[FRQ - 3]; }
/* Get COMP2 based on MC frequency */ -static u32 get_COMP2(u32 tCK) +static u32 get_COMP2(u32 FRQ, u8 base_freq) { + if (base_freq != BASEFREQ) + die("Wrong base_freq for sandybridge."); + static const u32 frq_comp2_map[] = { /* FRQ: 3, 4, 5, 6, 7, 8, */ 0x0D6BEDCC, 0x0CE7C34C, 0x0CA57A4C, 0x0C6369CC, 0x0C42514C, 0x0C21410C, }; - return frq_comp2_map[get_FRQ(tCK) - 3]; + return frq_comp2_map[FRQ - 3]; }
static void snb_normalize_tclk(u32 *tclk) @@ -150,6 +180,7 @@ * Normalising tCK before computing clock could potentially * result in a lower selected CAS, which is desired. */ + ctrl->base_freq = BASEFREQ; snb_normalize_tclk(&(ctrl->tCK)); if (!(ctrl->tCK)) die("Couldn't find compatible clock / CAS settings\n"); @@ -284,14 +315,16 @@ ctrl->tRFC = DIV_ROUND_UP(ctrl->tRFC, ctrl->tCK - 1); /* FIXME: Why the -1 ? */ printk(BIOS_DEBUG, "Selected tRFC : %uT\n", ctrl->tRFC);
- ctrl->tREFI = get_REFI(ctrl->tCK); - ctrl->tMOD = get_MOD(ctrl->tCK); - ctrl->tXSOffset = get_XSOffset(ctrl->tCK); - ctrl->tWLO = get_WLO(ctrl->tCK); - ctrl->tCKE = get_CKE(ctrl->tCK); - ctrl->tXPDLL = get_XPDLL(ctrl->tCK); - ctrl->tXP = get_XP(ctrl->tCK); - ctrl->tAONPD = get_AONPD(ctrl->tCK); + const u32 FRQ = get_FRQ(ctrl->tCK, ctrl->base_freq); + + ctrl->tREFI = get_REFI(FRQ, ctrl->base_freq); + ctrl->tMOD = get_MOD(FRQ, ctrl->base_freq); + ctrl->tXSOffset = get_XSOffset(FRQ, ctrl->base_freq); + ctrl->tWLO = get_WLO(FRQ, ctrl->base_freq); + ctrl->tCKE = get_CKE(FRQ, ctrl->base_freq); + ctrl->tXPDLL = get_XPDLL(FRQ, ctrl->base_freq); + ctrl->tXP = get_XP(FRQ, ctrl->base_freq); + ctrl->tAONPD = get_AONPD(FRQ, ctrl->base_freq); }
static void dram_freq(ramctr_timing *ctrl) @@ -311,7 +344,7 @@ find_cas_tck(ctrl);
/* Frequency multiplier */ - const u32 FRQ = get_FRQ(ctrl->tCK); + const u32 FRQ = get_FRQ(ctrl->tCK, ctrl->base_freq);
/* * The PLL will never lock if the required frequency is already set. @@ -350,6 +383,8 @@
static void dram_ioregs(ramctr_timing *ctrl) { + const u32 FRQ = get_FRQ(ctrl->tCK, ctrl->base_freq); + u32 reg;
int channel; @@ -377,7 +412,7 @@ printram("done\n");
/* Set COMP2 */ - MCHBAR32(CRCOMPOFST2) = get_COMP2(ctrl->tCK); + MCHBAR32(CRCOMPOFST2) = get_COMP2(FRQ, ctrl->base_freq); printram("COMP2 done\n");
/* Set COMP1 */
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39723 )
Change subject: nb/intel/sandybridge: Rewrite table accessors ......................................................................
Patch Set 4:
It's ugly, but it's just a stepping stone.
Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39723
to look at the new patch set (#6).
Change subject: nb/intel/sandybridge: Rewrite table accessors ......................................................................
nb/intel/sandybridge: Rewrite table accessors
There is no need to call get_FRQ a dozen times with the same parameters. As SNB will eventually use the same code, only IVB is being refactored.
Tested on Asus P8Z77-V LX2, still boots with i7-2600 and i5-3330.
Change-Id: Idd7c119b2aa291e6396e12fb29effaf3ec73108a Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/northbridge/intel/sandybridge/raminit_ivy.c 1 file changed, 48 insertions(+), 45 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/39723/6
Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39723 )
Change subject: nb/intel/sandybridge: Rewrite table accessors ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39723/6/src/northbridge/intel/sandy... File src/northbridge/intel/sandybridge/raminit_ivy.c:
https://review.coreboot.org/c/coreboot/+/39723/6/src/northbridge/intel/sandy... PS6, Line 437: FRQ we generally have some lower case letter in variables to distinguish them from macros/defines.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39723 )
Change subject: nb/intel/sandybridge: Rewrite table accessors ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39723/6/src/northbridge/intel/sandy... File src/northbridge/intel/sandybridge/raminit_ivy.c:
https://review.coreboot.org/c/coreboot/+/39723/6/src/northbridge/intel/sandy... PS6, Line 437: FRQ
we generally have some lower case letter in variables to distinguish them from macros/defines.
This is to be consistent with line 15 of this file. In any case, it gets replaced by a struct field in a later change
Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39723 )
Change subject: nb/intel/sandybridge: Rewrite table accessors ......................................................................
Patch Set 6: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/39723/6/src/northbridge/intel/sandy... File src/northbridge/intel/sandybridge/raminit_ivy.c:
https://review.coreboot.org/c/coreboot/+/39723/6/src/northbridge/intel/sandy... PS6, Line 437: FRQ
This is to be consistent with line 15 of this file. […]
Ack
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39723 )
Change subject: nb/intel/sandybridge: Rewrite table accessors ......................................................................
nb/intel/sandybridge: Rewrite table accessors
There is no need to call get_FRQ a dozen times with the same parameters. As SNB will eventually use the same code, only IVB is being refactored.
Tested on Asus P8Z77-V LX2, still boots with i7-2600 and i5-3330.
Change-Id: Idd7c119b2aa291e6396e12fb29effaf3ec73108a Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/39723 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Patrick Georgi pgeorgi@google.com --- M src/northbridge/intel/sandybridge/raminit_ivy.c 1 file changed, 48 insertions(+), 45 deletions(-)
Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved
diff --git a/src/northbridge/intel/sandybridge/raminit_ivy.c b/src/northbridge/intel/sandybridge/raminit_ivy.c index 67927ed..fa63656 100644 --- a/src/northbridge/intel/sandybridge/raminit_ivy.c +++ b/src/northbridge/intel/sandybridge/raminit_ivy.c @@ -29,94 +29,94 @@ return FRQ; }
-/* Get REFI based on MC frequency, tREFI = 7.8usec */ -static u32 get_REFI(u32 tCK, u8 base_freq) +/* Get REFI based on frequency index, tREFI = 7.8usec */ +static u32 get_REFI(u32 FRQ, u8 base_freq) { if (base_freq == 100) - return frq_refi_map[1][get_FRQ(tCK, 100) - 7]; + return frq_refi_map[1][FRQ - 7];
else - return frq_refi_map[0][get_FRQ(tCK, 133) - 3]; + return frq_refi_map[0][FRQ - 3]; }
-/* Get XSOffset based on MC frequency, tXS-Offset: tXS = tRFC + 10ns */ -static u8 get_XSOffset(u32 tCK, u8 base_freq) +/* Get XSOffset based on frequency index, tXS-Offset: tXS = tRFC + 10ns */ +static u8 get_XSOffset(u32 FRQ, u8 base_freq) { if (base_freq == 100) - return frq_xs_map[1][get_FRQ(tCK, 100) - 7]; + return frq_xs_map[1][FRQ - 7];
else - return frq_xs_map[0][get_FRQ(tCK, 133) - 3]; + return frq_xs_map[0][FRQ - 3]; }
-/* Get MOD based on MC frequency */ -static u8 get_MOD(u32 tCK, u8 base_freq) +/* Get MOD based on frequency index */ +static u8 get_MOD(u32 FRQ, u8 base_freq) { if (base_freq == 100) - return frq_mod_map[1][get_FRQ(tCK, 100) - 7]; + return frq_mod_map[1][FRQ - 7];
else - return frq_mod_map[0][get_FRQ(tCK, 133) - 3]; + return frq_mod_map[0][FRQ - 3]; }
-/* Get Write Leveling Output delay based on MC frequency */ -static u8 get_WLO(u32 tCK, u8 base_freq) +/* Get Write Leveling Output delay based on frequency index */ +static u8 get_WLO(u32 FRQ, u8 base_freq) { if (base_freq == 100) - return frq_wlo_map[1][get_FRQ(tCK, 100) - 7]; + return frq_wlo_map[1][FRQ - 7];
else - return frq_wlo_map[0][get_FRQ(tCK, 133) - 3]; + return frq_wlo_map[0][FRQ - 3]; }
-/* Get CKE based on MC frequency */ -static u8 get_CKE(u32 tCK, u8 base_freq) +/* Get CKE based on frequency index */ +static u8 get_CKE(u32 FRQ, u8 base_freq) { if (base_freq == 100) - return frq_cke_map[1][get_FRQ(tCK, 100) - 7]; + return frq_cke_map[1][FRQ - 7];
else - return frq_cke_map[0][get_FRQ(tCK, 133) - 3]; + return frq_cke_map[0][FRQ - 3]; }
-/* Get XPDLL based on MC frequency */ -static u8 get_XPDLL(u32 tCK, u8 base_freq) +/* Get XPDLL based on frequency index */ +static u8 get_XPDLL(u32 FRQ, u8 base_freq) { if (base_freq == 100) - return frq_xpdll_map[1][get_FRQ(tCK, 100) - 7]; + return frq_xpdll_map[1][FRQ - 7];
else - return frq_xpdll_map[0][get_FRQ(tCK, 133) - 3]; + return frq_xpdll_map[0][FRQ - 3]; }
-/* Get XP based on MC frequency */ -static u8 get_XP(u32 tCK, u8 base_freq) +/* Get XP based on frequency index */ +static u8 get_XP(u32 FRQ, u8 base_freq) { if (base_freq == 100) - return frq_xp_map[1][get_FRQ(tCK, 100) - 7]; + return frq_xp_map[1][FRQ - 7];
else - return frq_xp_map[0][get_FRQ(tCK, 133) - 3]; + return frq_xp_map[0][FRQ - 3]; }
-/* Get AONPD based on MC frequency */ -static u8 get_AONPD(u32 tCK, u8 base_freq) +/* Get AONPD based on frequency index */ +static u8 get_AONPD(u32 FRQ, u8 base_freq) { if (base_freq == 100) - return frq_aonpd_map[1][get_FRQ(tCK, 100) - 7]; + return frq_aonpd_map[1][FRQ - 7];
else - return frq_aonpd_map[0][get_FRQ(tCK, 133) - 3]; + return frq_aonpd_map[0][FRQ - 3]; }
-/* Get COMP2 based on MC frequency */ -static u32 get_COMP2(u32 tCK, u8 base_freq) +/* Get COMP2 based on frequency index */ +static u32 get_COMP2(u32 FRQ, u8 base_freq) { if (base_freq == 100) - return frq_comp2_map[1][get_FRQ(tCK, 100) - 7]; + return frq_comp2_map[1][FRQ - 7];
else - return frq_comp2_map[0][get_FRQ(tCK, 133) - 3]; + return frq_comp2_map[0][FRQ - 3]; }
static void ivb_normalize_tclk(ramctr_timing *ctrl, bool ref_100mhz_support) @@ -363,14 +363,16 @@ ctrl->tRFC = DIV_ROUND_UP(ctrl->tRFC, ctrl->tCK); printk(BIOS_DEBUG, "Selected tRFC : %uT\n", ctrl->tRFC);
- ctrl->tREFI = get_REFI(ctrl->tCK, ctrl->base_freq); - ctrl->tMOD = get_MOD(ctrl->tCK, ctrl->base_freq); - ctrl->tXSOffset = get_XSOffset(ctrl->tCK, ctrl->base_freq); - ctrl->tWLO = get_WLO(ctrl->tCK, ctrl->base_freq); - ctrl->tCKE = get_CKE(ctrl->tCK, ctrl->base_freq); - ctrl->tXPDLL = get_XPDLL(ctrl->tCK, ctrl->base_freq); - ctrl->tXP = get_XP(ctrl->tCK, ctrl->base_freq); - ctrl->tAONPD = get_AONPD(ctrl->tCK, ctrl->base_freq); + const u32 FRQ = get_FRQ(ctrl->tCK, ctrl->base_freq); + + ctrl->tREFI = get_REFI(FRQ, ctrl->base_freq); + ctrl->tMOD = get_MOD(FRQ, ctrl->base_freq); + ctrl->tXSOffset = get_XSOffset(FRQ, ctrl->base_freq); + ctrl->tWLO = get_WLO(FRQ, ctrl->base_freq); + ctrl->tCKE = get_CKE(FRQ, ctrl->base_freq); + ctrl->tXPDLL = get_XPDLL(FRQ, ctrl->base_freq); + ctrl->tXP = get_XP(FRQ, ctrl->base_freq); + ctrl->tAONPD = get_AONPD(FRQ, ctrl->base_freq); }
static void dram_freq(ramctr_timing *ctrl) @@ -432,6 +434,7 @@
static void dram_ioregs(ramctr_timing *ctrl) { + const u32 FRQ = get_FRQ(ctrl->tCK, ctrl->base_freq); u32 reg;
int channel; @@ -459,7 +462,7 @@ printram("done\n");
/* Set COMP2 */ - MCHBAR32(CRCOMPOFST2) = get_COMP2(ctrl->tCK, ctrl->base_freq); + MCHBAR32(CRCOMPOFST2) = get_COMP2(FRQ, ctrl->base_freq); printram("COMP2 done\n");
/* Set COMP1 */
-
Angel Pons (Code Review) -
Patrick Georgi (Code Review)