Change in coreboot[master]: nb/intel/haswell/memmap.h: Define MMIO window sizes

[Angel Pons (Code Review)]

Attention is currently required from: Nico Huber, Arthur Heymans, Patrick Rudolph.
Hello Nico Huber, Arthur Heymans, Patrick Rudolph,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/55479

to review the following change.

Change subject: nb/intel/haswell/memmap.h: Define MMIO window sizes
......................................................................

nb/intel/haswell/memmap.h: Define MMIO window sizes

Add defines for the sizes of northbridge MMIO windows and use them where
applicable. The macro names have been taken from Broadwell.

Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical.

Change-Id: I845cba8acbd478cd325d2e364138336d985f9c34
Signed-off-by: Angel Pons 
---
M src/northbridge/intel/haswell/acpi/hostbridge.asl
M src/northbridge/intel/haswell/memmap.h
M src/northbridge/intel/haswell/northbridge.c
3 files changed, 20 insertions(+), 10 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/55479/1

diff --git a/src/northbridge/intel/haswell/acpi/hostbridge.asl b/src/northbridge/intel/haswell/acpi/hostbridge.asl
index 80d21d0..5c22ce1 100644
--- a/src/northbridge/intel/haswell/acpi/hostbridge.asl
+++ b/src/northbridge/intel/haswell/acpi/hostbridge.asl
@@ -1,5 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */

+#include <northbridge/intel/haswell/memmap.h>
+
 Name (_HID, EISAID ("PNP0A08"))	// PCIe
 Name (_CID, EISAID ("PNP0A03"))	// PCI

@@ -173,9 +175,9 @@

Name (PDRS, ResourceTemplate () {
    	Memory32Fixed (ReadWrite, CONFIG_FIXED_RCBA_MMIO_BASE, CONFIG_RCBA_LENGTH)
-		Memory32Fixed (ReadWrite, CONFIG_FIXED_MCHBAR_MMIO_BASE, 0x00008000)
-		Memory32Fixed (ReadWrite, CONFIG_FIXED_DMIBAR_MMIO_BASE, 0x00001000)
-		Memory32Fixed (ReadWrite, CONFIG_FIXED_EPBAR_MMIO_BASE,  0x00001000)
+		Memory32Fixed (ReadWrite, CONFIG_FIXED_MCHBAR_MMIO_BASE, MCH_BASE_SIZE)
+		Memory32Fixed (ReadWrite, CONFIG_FIXED_DMIBAR_MMIO_BASE, DMI_BASE_SIZE)
+		Memory32Fixed (ReadWrite, CONFIG_FIXED_EPBAR_MMIO_BASE, EP_BASE_SIZE)
    	Memory32Fixed (ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH)
    	Memory32Fixed (ReadWrite, 0xfed20000, 0x00020000) // TXT
    	Memory32Fixed (ReadWrite, 0xfed40000, 0x00005000) // TPM
diff --git a/src/northbridge/intel/haswell/memmap.h b/src/northbridge/intel/haswell/memmap.h
index 1aa2d67..92beeec 100644
--- a/src/northbridge/intel/haswell/memmap.h
+++ b/src/northbridge/intel/haswell/memmap.h
@@ -3,6 +3,16 @@
 #ifndef NORTHBRIDGE_INTEL_HASWELL_MEMMAP_H
 #define NORTHBRIDGE_INTEL_HASWELL_MEMMAP_H

+#define MCH_BASE_SIZE		0x8000
+
+#define DMI_BASE_SIZE		0x1000
+
+#define EP_BASE_SIZE		0x1000
+
+#define EDRAM_BASE_SIZE		0x4000
+
+#define GDXC_BASE_SIZE		0x1000
+
 #define GFXVT_BASE_ADDRESS	0xfed90000ULL
 #define GFXVT_BASE_SIZE		0x1000

diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c
index fdaac7c..02799d3 100644
--- a/src/northbridge/intel/haswell/northbridge.c
+++ b/src/northbridge/intel/haswell/northbridge.c
@@ -85,15 +85,13 @@
    const char *description;
 };

-#define SIZE_KB(x) ((x) * 1024)
 struct fixed_mmio_descriptor mc_fixed_resources[] = {
-	{ MCHBAR,   SIZE_KB(32), get_bar,           "MCHBAR"   },
-	{ DMIBAR,   SIZE_KB(4),  get_bar,           "DMIBAR"   },
-	{ EPBAR,    SIZE_KB(4),  get_bar,           "EPBAR"    },
-	{ GDXCBAR,  SIZE_KB(4),  get_bar_in_mchbar, "GDXCBAR"  },
-	{ EDRAMBAR, SIZE_KB(16), get_bar_in_mchbar, "EDRAMBAR" },
+	{ MCHBAR,   MCH_BASE_SIZE,   get_bar,           "MCHBAR"   },
+	{ DMIBAR,   DMI_BASE_SIZE,   get_bar,           "DMIBAR"   },
+	{ EPBAR,    EP_BASE_SIZE,    get_bar,           "EPBAR"    },
+	{ GDXCBAR,  GDXC_BASE_SIZE,  get_bar_in_mchbar, "GDXCBAR"  },
+	{ EDRAMBAR, EDRAM_BASE_SIZE, get_bar_in_mchbar, "EDRAMBAR" },
 };
-#undef SIZE_KB

/* Add all known fixed MMIO ranges that hang off the host bridge/memory controller device. */
 static void mc_add_fixed_mmio_resources(struct device *dev)