Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38478 )
Change subject: soc/intel/skylake: Clean up systemagent.asl code ......................................................................
soc/intel/skylake: Clean up systemagent.asl code
This patch performs below operations 1. Remove unused ICH memory reference. 2. Update 64 bit SA DRAM bit fields as per SKL EDS. 3. Move pci_irqs.asl from SA to PCH as applicable. 4. Add _SEG/_UID name variables. 5. Reserve TPM area as applicable.
TEST=Build and boot EVE and Soraka to OS.
Change-Id: I44ce4866a83df40c38b69b07a71db3b81bca3981 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/soc/intel/skylake/acpi/pch.asl M src/soc/intel/skylake/acpi/systemagent.asl 2 files changed, 18 insertions(+), 25 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/38478/1
diff --git a/src/soc/intel/skylake/acpi/pch.asl b/src/soc/intel/skylake/acpi/pch.asl index 0aba2e7..ce1619a 100644 --- a/src/soc/intel/skylake/acpi/pch.asl +++ b/src/soc/intel/skylake/acpi/pch.asl @@ -23,6 +23,9 @@ #include <soc/gpe.h> #include <soc/pcr_ids.h>
+/* PCI IRQ assignment */ +#include "pci_irqs.asl" + /* GPIO Controller */ #include "gpio.asl"
diff --git a/src/soc/intel/skylake/acpi/systemagent.asl b/src/soc/intel/skylake/acpi/systemagent.asl index 89380aa..34922ac 100644 --- a/src/soc/intel/skylake/acpi/systemagent.asl +++ b/src/soc/intel/skylake/acpi/systemagent.asl @@ -17,8 +17,10 @@
#include <soc/iomap.h>
-Name (_HID, EISAID ("PNP0A08")) /* PCIe */ -Name (_CID, EISAID ("PNP0A03")) /* PCI */ +Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) // _HID: Hardware ID +Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) // _CID: Compatible ID +Name (_SEG, Zero) // _SEG: PCI Segment +Name (_UID, Zero) // _UID: Unique ID
Device (MCHC) { @@ -30,26 +32,27 @@ Offset(0x40), /* EPBAR (0:0:0:40) */ EPEN, 1, /* Enable */ , 11, - EPBR, 20, /* EPBAR [31:12] */ + EPBR, 27, /* EPBAR [38:12] */
Offset(0x48), /* MCHBAR (0:0:0:48) */ MHEN, 1, /* Enable */ , 14, - MHBR, 17, /* MCHBAR [31:15] */ + MHBR, 24, /* MCHBAR [38:15] */
Offset(0x60), /* PCIEXBAR (0:0:0:60) */ PXEN, 1, /* Enable */ PXSZ, 2, /* PCI Express Size */ - , 23, - PXBR, 6, /* PCI Express BAR [31:26] */ + , 25, + PXBR, 11, /* PCI Express BAR [38:28] */
Offset(0x68), /* DMIBAR (0:0:0:68) */ DIEN, 1, /* Enable */ , 11, - DIBR, 20, /* DMIBAR [31:12] */ + DIBR, 27, /* DMIBAR [38:12] */
Offset (0x70), /* ME Base Address */ MEBA, 64, + Offset (0xa0), TOM, 64, /* Top of Used Memory */ TUUD, 64, /* Top of Upper Used Memory */ @@ -182,12 +185,12 @@ 0x00000000, PCH_PRESERVED_BASE_ADDRESS, 0xfe7fffff, 0x00000000, PCH_PRESERVED_BASE_SIZE)
- /* TPM Area (0xfed40000-0xfed44fff) */ + /* TPM Area (0xfed40000-0xfed47fff) */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, - 0x00000000, 0xfed40000, 0xfed44fff, 0x00000000, - 0x00005000) -}) + 0x00000000, 0xfed40000, 0xfed47fff, 0x00000000, + 0x00008000) + })
/* Find PCI resource area in MCRS */ CreateDwordField (MCRS, PM01._MIN, PMIN) @@ -244,7 +247,7 @@ /* Get PCIe BAR */ Method (GPCB, 0, Serialized) { - ShiftLeft (_SB.PCI0.MCHC.PXBR, 26, Local0) + ShiftLeft (_SB.PCI0.MCHC.PXBR, 28, Local0) Return (Local0) }
@@ -292,19 +295,9 @@ */ Memory32Fixed (ReadWrite, 0, 0, PCIX)
- /* MISC ICH TTT base address reserved for the - * TxT module use. - */ - Memory32Fixed (ReadWrite, 0xFED20000, 0x20000) - /* VTD engine memory range. */ Memory32Fixed (ReadOnly, VTD_BASE_ADDRESS, VTD_BASE_SIZE)
- /* MISC ICH. Check if the hard code meets the - * real configuration. - */ - Memory32Fixed (ReadWrite, 0xFED45000, 0x4B000, TPMM) - /* FLASH range */ Memory32Fixed (ReadOnly, 0, CONFIG_ROM_SIZE, FIOH)
@@ -336,6 +329,3 @@ Return (BUF0) } } - -/* PCI IRQ assignment */ -#include "pci_irqs.asl"
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38478 )
Change subject: soc/intel/skylake: Clean up systemagent.asl code ......................................................................
Patch Set 1:
(2 comments)
https://review.coreboot.org/c/coreboot/+/38478/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38478/1//COMMIT_MSG@11 PS1, Line 11: 2. Update 64 bit SA DRAM bit fields as per SKL EDS. That’s not a clean-up in my opinion.
https://review.coreboot.org/c/coreboot/+/38478/1//COMMIT_MSG@14 PS1, Line 14: 5. Reserve TPM area as applicable. Please split this commit into smaller pieces. Maybe one for each item.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38478 )
Change subject: soc/intel/skylake: Clean up systemagent.asl code ......................................................................
Patch Set 1:
(2 comments)
https://review.coreboot.org/c/coreboot/+/38478/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38478/1//COMMIT_MSG@11 PS1, Line 11: 2. Update 64 bit SA DRAM bit fields as per SKL EDS.
That’s not a clean-up in my opinion.
i will get back on this
https://review.coreboot.org/c/coreboot/+/38478/1//COMMIT_MSG@14 PS1, Line 14: 5. Reserve TPM area as applicable.
Please split this commit into smaller pieces. Maybe one for each item.
sure let me get back
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38478 )
Change subject: soc/intel/skylake: Clean up systemagent.asl code ......................................................................
Patch Set 1: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/38478/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38478/1//COMMIT_MSG@11 PS1, Line 11: 2. Update 64 bit SA DRAM bit fields as per SKL EDS.
i will get back on this
Well, if it's not a clean-up change, maybe call it "correcting change" instead :P
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38478 )
Change subject: soc/intel/skylake: Clean up systemagent.asl code ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38478/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38478/1//COMMIT_MSG@11 PS1, Line 11: 2. Update 64 bit SA DRAM bit fields as per SKL EDS.
Well, if it's not a clean-up change, maybe call it "correcting change" instead :P
Hi Paul/Angel,
Thanks for your feedback, i have divided this CL into multiple one, kindly help to review https://review.coreboot.org/q/topic:%22SKL_Correcting+Change%22+(status:open...)
Stefan Reinauer has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/38478?usp=email )
Change subject: soc/intel/skylake: Clean up systemagent.asl code ......................................................................
Abandoned
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Angel Pons (Code Review) -
Paul Menzel (Code Review)
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Stefan Reinauer (Code Review)
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Subrata Banik (Code Review)