Change in coreboot[master]: security/intel/txt/romstage.c: Unlock memory when SCLEAN not needed

[Michał Żygowski (Code Review)]

Attention is currently required from: Patrick Rudolph.
Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59521 )

Change subject: security/intel/txt/romstage.c: Unlock memory when SCLEAN not needed
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Patch Set 2:

(1 comment)

Commit Message:

https://review.coreboot.org/c/coreboot/+/59521/comment/59c51990_f4b34c6c 
PS2, Line 10: memory on a TXT enabled platform. Previosuly on Sandybridge raminit the
> this MSR is actually written in init_dram_ddr3(). […]

Since TXT is optional, we would still need to have this fragment just in case the memory controller would be locked. Having it in the TXT driver allows to use it in a controlled manner, i.e. only when TXT is checked to be supported by the chipset and CPU. By the way, this MSR should generate #GP when CPU or chipset is not TXT capable, we do not guard this in src/northbridge/intel/sandybridge/raminit.c. have you experienced such issues?