Change in coreboot[master]: soc/intel/tgl: Disable S0i3.2 & S0i3.3 substates

[build bot (Jenkins) (Code Review)]

Attention is currently required from: Furquan Shaikh, Shreesh Chhabbi.
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49766 )

Change subject: soc/intel/tgl: Disable S0i3.2 & S0i3.3 substates
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Patch Set 6:

(4 comments)

File src/soc/intel/tigerlake/fsp_params.c:

https://review.coreboot.org/c/coreboot/+/49766/comment/79990e0a_cb705aa2 
PS6, Line 65: 		//disable_mask |= LPM_S0i3_0 | LPM_S0i3_1 | 
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https://review.coreboot.org/c/coreboot/+/49766/comment/9f88e12c_75346417 
PS6, Line 72: 	/* If external phy gating is not implemented, 
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https://review.coreboot.org/c/coreboot/+/49766/comment/2dee9185_89f7b51f 
PS6, Line 78: 	if (is_dev_enabled(pcidev_path_on_root(PCH_DEVFN_CNVI_BT)) || 
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https://review.coreboot.org/c/coreboot/+/49766/comment/ae0ba2e9_4cb460d0 
PS6, Line 79: 	is_dev_enabled(pcidev_path_on_root(PCH_DEVFN_CNVI_WIFI)) || 
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