Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Fred Reitberger, Felix Held. Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63732 )
Change subject: soc/amd/sabrina: Modify start address of PSP verstage ......................................................................
soc/amd/sabrina: Modify start address of PSP verstage
PSP verstage can start at address 0 and use 200KB of PSP SRAM for execution. Modify both the PSP SRAM start address and size for use by PSP verstage.
BUG=b:220848544 TEST=Build Skyrim BIOS image with PSP verstage enabled.
Signed-off-by: Karthikeyan Ramasubramanian kramasub@google.com Change-Id: I73e13b82faa0f443570a0c839e7699a79bdae024 --- M src/soc/amd/sabrina/include/soc/psp_verstage_addr.h 1 file changed, 4 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/63732/1
diff --git a/src/soc/amd/sabrina/include/soc/psp_verstage_addr.h b/src/soc/amd/sabrina/include/soc/psp_verstage_addr.h index 6636ea1..b7939d9 100644 --- a/src/soc/amd/sabrina/include/soc/psp_verstage_addr.h +++ b/src/soc/amd/sabrina/include/soc/psp_verstage_addr.h @@ -6,12 +6,12 @@ #define AMD_SABRINA_PSP_VERSTAGE_ADDR_H
/* - * Start of available space is 0x36000 and this is where the + * Start of available space is 0x0 and this is where the * header for the user app (verstage) must be mapped. - * Size is 0x14000 bytes + * Size is 208KB */ -#define PSP_SRAM_START 0x26000 -#define PSP_SRAM_SIZE (148K) +#define PSP_SRAM_START 0x0 +#define PSP_SRAM_SIZE (208K) #define VERSTAGE_START PSP_SRAM_START
/*