Change in ...coreboot[master]: [WIP] Documentation: How to run coreboot on PC Engines apu1
Piotr Kleinschmidt has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32907
Change subject: [WIP] Documentation: How to run coreboot on PC Engines apu1 ......................................................................
[WIP] Documentation: How to run coreboot on PC Engines apu1
There were no documentation about running coreboot on apu1 platform, so now it describes how to do this.
Signed-off-by: Piotr Kleinschmidt piotr.kleinschmidt@3mdeb.com Change-Id: If79693e893c4afe52bf1c9aa8017ac6f650a96e4 --- A Documentation/mainboard/pcengines/apu1.md A Documentation/mainboard/pcengines/apu1c1_flash.jpg 2 files changed, 63 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/32907/1
diff --git a/Documentation/mainboard/pcengines/apu1.md b/Documentation/mainboard/pcengines/apu1.md new file mode 100644 index 0000000..20259a6 --- /dev/null +++ b/Documentation/mainboard/pcengines/apu1.md @@ -0,0 +1,63 @@ +# PC Engines apu1 + +This page describes how to run coreboot on PC Engines apu1 platform. + +## Technology + +| | | +| -----------|:-------------------------------------------------------| +| CPU | AMD G series T40E APU | +| CPU core | 1 GHz dual core (Bobcat core) with 64 bit support | +| | 32K data + 32K instruction + 512KB L2 cache per core | +| DRAM | 2 or 4 GB DDR3-1066 DRAM | +| Boot | From SD card, USB, m-SATA | +| Power | 6 to 12W of 12V power | +| Firmware | coreboot with support for iPXE and USB boot | + +## Flashing coreboot + +| Type | Value | +|---------------------|:-----------| +| Socketed flash | no | +| Model | MX25L1606E | +| Size | 2 MiB | +| Package | SOP-8 | +| Write protection | no | +| Dual BIOS feature | no | +| Internal flashing | yes | + +### Internal programming + +The SPI flash can be accessed using [flashrom]. It is important to execute +command with a `-c <chipname>` argument: + +`flashrom -p internal -c MX25L1606E -w coreboot.rom ` + +### External programming + +**IMPORTANT**: When programming SPI flash, first you need to enter apu1 in S5 +(Soft-off) power state. More details about that state is available in ACPI +Specification documentation. + +The external access to flash chip is available through standard SOP-8 clip or +SOP-8 header which is next to the flash chip on the board. Notice that not all +boards have a header soldered down originally. Hence, there could be an empty +slot with 8 eyelets, so you can solder down a header on your own. The SPI flash +chip and SPI header are marked in the picture below. + +There is no restrictions as to programmer device. However, [flashrom] is +strongly recommended. The example command to program SPI flash with a linux_spi +is: + +`flashrom -w coreboot.rom -p linux_spi:dev=/dev/spidev1.0,spispeed=16000 -c +"MX25L1606E"` + + +**apu1 platform with marked in SPI header and SPI flash chip** +![][apu1c1_flash] + +[apu1c1_flash]: apu1c1_flash.jpg + + +[flashrom]: https://flashrom.org/Flashrom +[here]: https://www.coreboot.org/Binary_situation diff --git a/Documentation/mainboard/pcengines/apu1c1_flash.jpg b/Documentation/mainboard/pcengines/apu1c1_flash.jpg new file mode 100644 index 0000000..069e976 --- /dev/null +++ b/Documentation/mainboard/pcengines/apu1c1_flash.jpg Binary files differ
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32907 )
Change subject: [WIP] Documentation: How to run coreboot on PC Engines apu1 ......................................................................
Patch Set 1:
(14 comments)
https://review.coreboot.org/#/c/32907/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/32907/1//COMMIT_MSG@7 PS1, Line 7: [WIP] You can tag this WIP in Gerrit, so you do not need to amend the commit message.
https://review.coreboot.org/#/c/32907/1//COMMIT_MSG@7 PS1, Line 7: apu1 APU1
https://review.coreboot.org/#/c/32907/1//COMMIT_MSG@8 PS1, Line 8: : There were no documentation about running coreboot on apu1 platform, so now it describes how to do this. Please wrap the line after 75/72 characters.
https://review.coreboot.org/#/c/32907/1//COMMIT_MSG@9 PS1, Line 9: were is
https://review.coreboot.org/#/c/32907/1//COMMIT_MSG@11 PS1, Line 11: Signed-off-by: Piotr Kleinschmidt piotr.kleinschmidt@3mdeb.com Please move it below the Change-Id line.
https://review.coreboot.org/#/c/32907/1/Documentation/mainboard/pcengines/ap... File Documentation/mainboard/pcengines/apu1.md:
https://review.coreboot.org/#/c/32907/1/Documentation/mainboard/pcengines/ap... PS1, Line 1: apu1 APU1
https://review.coreboot.org/#/c/32907/1/Documentation/mainboard/pcengines/ap... PS1, Line 31: [flashrom] Does this work? Shouldn’t it be `[flashrom][]`?
https://review.coreboot.org/#/c/32907/1/Documentation/mainboard/pcengines/ap... PS1, Line 34: `flashrom -p internal -c MX25L1606E -w coreboot.rom ` Please remove the `…` and indent it with four spaces.
https://review.coreboot.org/#/c/32907/1/Documentation/mainboard/pcengines/ap... PS1, Line 39: ACPI : Specification documentation Add a link?
https://review.coreboot.org/#/c/32907/1/Documentation/mainboard/pcengines/ap... PS1, Line 43: which is Can be removed.
https://review.coreboot.org/#/c/32907/1/Documentation/mainboard/pcengines/ap... PS1, Line 48: to programmer device to *the* …
https://review.coreboot.org/#/c/32907/1/Documentation/mainboard/pcengines/ap... PS1, Line 49: a linux_spi a linux_spi *device*?
https://review.coreboot.org/#/c/32907/1/Documentation/mainboard/pcengines/ap... PS1, Line 52: `flashrom -w coreboot.rom -p linux_spi:dev=/dev/spidev1.0,spispeed=16000 -c : "MX25L1606E"` Indent this please instead of using backticks.
https://review.coreboot.org/#/c/32907/1/Documentation/mainboard/pcengines/ap... PS1, Line 63: [here]: https://www.coreboot.org/Binary_situation Where is this used?
Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32907 )
Change subject: [WIP] Documentation: How to run coreboot on PC Engines apu1 ......................................................................
Patch Set 1:
(4 comments)
You may also add a link to the open schematics on PC Engines site. It would look great
https://review.coreboot.org/#/c/32907/1/Documentation/mainboard/pcengines/ap... File Documentation/mainboard/pcengines/apu1.md:
https://review.coreboot.org/#/c/32907/1/Documentation/mainboard/pcengines/ap... PS1, Line 13: | Boot | From SD card, USB, m-SATA | mSATA, SATA
https://review.coreboot.org/#/c/32907/1/Documentation/mainboard/pcengines/ap... PS1, Line 25: | Write protection | no | available with jumper on #WP pin?
https://review.coreboot.org/#/c/32907/1/Documentation/mainboard/pcengines/ap... PS1, Line 34: `flashrom -p internal -c MX25L1606E -w coreboot.rom `
Please remove the `…` and indent it with four spaces.
should also be "MX25L1606E", flashrom expects the chip to be passed in quotes ""
https://review.coreboot.org/#/c/32907/1/Documentation/mainboard/pcengines/ap... PS1, Line 39: ACPI : Specification documentation
Add a link?
Add information that S5 can be forced by shorting power button pin on J2 header.
Piotr Kleinschmidt has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32907 )
Change subject: Documentation: How to run coreboot on PC Engines APU1 ......................................................................
Patch Set 3:
(21 comments)
This change is ready for review.
https://review.coreboot.org/#/c/32907/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/32907/1//COMMIT_MSG@7 PS1, Line 7: apu1
APU1
Done
https://review.coreboot.org/#/c/32907/1//COMMIT_MSG@7 PS1, Line 7: [WIP]
You can tag this WIP in Gerrit, so you do not need to amend the commit message.
Done
https://review.coreboot.org/#/c/32907/1//COMMIT_MSG@8 PS1, Line 8: : There were no documentation about running coreboot on apu1 platform, so now it describes how to do this.
Please wrap the line after 75/72 characters.
Done
https://review.coreboot.org/#/c/32907/1//COMMIT_MSG@9 PS1, Line 9: were
is
Done
https://review.coreboot.org/#/c/32907/1//COMMIT_MSG@11 PS1, Line 11: Signed-off-by: Piotr Kleinschmidt piotr.kleinschmidt@3mdeb.com
Please move it below the Change-Id line.
Done
https://review.coreboot.org/#/c/32907/1/Documentation/mainboard/pcengines/ap... File Documentation/mainboard/pcengines/apu1.md:
https://review.coreboot.org/#/c/32907/1/Documentation/mainboard/pcengines/ap... PS1, Line 1: apu1
APU1
Done
https://review.coreboot.org/#/c/32907/1/Documentation/mainboard/pcengines/ap... PS1, Line 13: | Boot | From SD card, USB, m-SATA |
mSATA, SATA
Done
https://review.coreboot.org/#/c/32907/1/Documentation/mainboard/pcengines/ap... PS1, Line 25: | Write protection | no |
available with jumper on #WP pin?
Done
https://review.coreboot.org/#/c/32907/1/Documentation/mainboard/pcengines/ap... PS1, Line 31: [flashrom]
Does this work? Shouldn’t it be `[flashrom][]`?
According to other documents it should work fine.
https://review.coreboot.org/#/c/32907/1/Documentation/mainboard/pcengines/ap... PS1, Line 34: `flashrom -p internal -c MX25L1606E -w coreboot.rom `
should also be "MX25L1606E", flashrom expects the chip to be passed in quotes ""
Done
https://review.coreboot.org/#/c/32907/1/Documentation/mainboard/pcengines/ap... PS1, Line 39: ACPI : Specification documentation
Add information that S5 can be forced by shorting power button pin on J2 header.
I deleted reference to that documentation and only gave information how to force that state
https://review.coreboot.org/#/c/32907/1/Documentation/mainboard/pcengines/ap... PS1, Line 43: which is
Can be removed.
Done
https://review.coreboot.org/#/c/32907/1/Documentation/mainboard/pcengines/ap... PS1, Line 48: to programmer device
to *the* …
Done
https://review.coreboot.org/#/c/32907/1/Documentation/mainboard/pcengines/ap... PS1, Line 49: a linux_spi
a linux_spi *device*?
It's not actually linux_spi device, so now I described it more precisely.
https://review.coreboot.org/#/c/32907/1/Documentation/mainboard/pcengines/ap... PS1, Line 52: `flashrom -w coreboot.rom -p linux_spi:dev=/dev/spidev1.0,spispeed=16000 -c : "MX25L1606E"`
Indent this please instead of using backticks.
Done
https://review.coreboot.org/#/c/32907/1/Documentation/mainboard/pcengines/ap... PS1, Line 63: [here]: https://www.coreboot.org/Binary_situation
Where is this used?
I deleted it, it was unnecessary.
https://review.coreboot.org/#/c/32907/2/Documentation/mainboard/pcengines/ap... File Documentation/mainboard/pcengines/apu1.md:
https://review.coreboot.org/#/c/32907/2/Documentation/mainboard/pcengines/ap... PS2, Line 1: # PC Engines APU1
reference file from index. […]
Added reference to index.md
https://review.coreboot.org/#/c/32907/2/Documentation/mainboard/pcengines/ap... PS2, Line 7: | | |
use supported tables: […]
Done
https://review.coreboot.org/#/c/32907/2/Documentation/mainboard/pcengines/ap... PS2, Line 27: r
EC or Super IO?
Added information about Super IO
https://review.coreboot.org/#/c/32907/2/Documentation/mainboard/pcengines/ap... PS2, Line 43: SOP-8 header next to the flash chip on the board. Notice that not all boards
pin header […]
Added pin layout as picture at the end of the document
https://review.coreboot.org/#/c/32907/2/Documentation/mainboard/pcengines/ap... PS2, Line 48: There is no restrictions as to the programmer device. However, [flashrom] is
no need for that, already covered by https://doc.coreboot.org/flash_tutorial/index.html […]
Done
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32907
to look at the new patch set (#4).
Change subject: Documentation: How to run coreboot on PC Engines APU1 ......................................................................
Documentation: How to run coreboot on PC Engines APU1
There is no documentation about running coreboot on apu1 platform, so now it describes how to do this.
Change-Id: If79693e893c4afe52bf1c9aa8017ac6f650a96e4 Signed-off-by: Piotr Kleinschmidt piotr.kleinschmidt@3mdeb.com --- M Documentation/mainboard/index.md A Documentation/mainboard/pcengines/apu1.md A Documentation/mainboard/pcengines/apu1c1.jpg A Documentation/mainboard/pcengines/spi_header.jpg 4 files changed, 99 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/32907/4
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32907 )
Change subject: Documentation: How to run coreboot on PC Engines APU1 ......................................................................
Patch Set 4: Code-Review+1
(1 comment)
https://review.coreboot.org/#/c/32907/4/Documentation/mainboard/pcengines/ap... File Documentation/mainboard/pcengines/apu1.md:
https://review.coreboot.org/#/c/32907/4/Documentation/mainboard/pcengines/ap... PS4, Line 76: **apu1 platform with marked in SPI header and SPI flash chip** There might be the same confusion about SPI_DI and SPI_DO signal directions that got fixed for apu2 document.
Hello Kyösti Mälkki, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32907
to look at the new patch set (#5).
Change subject: Documentation: How to run coreboot on PC Engines APU1 ......................................................................
Documentation: How to run coreboot on PC Engines APU1
There is no documentation about running coreboot on apu1 platform, so now it describes how to do this.
Change-Id: If79693e893c4afe52bf1c9aa8017ac6f650a96e4 Signed-off-by: Piotr Kleinschmidt piotr.kleinschmidt@3mdeb.com --- M Documentation/mainboard/index.md A Documentation/mainboard/pcengines/apu1.md A Documentation/mainboard/pcengines/apu1_spi.jpg A Documentation/mainboard/pcengines/apu1c1.jpg 4 files changed, 101 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/32907/5
Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32907 )
Change subject: Documentation: How to run coreboot on PC Engines APU1 ......................................................................
Patch Set 5:
Please apply the same fixes for the commit message as Angel Pons stated in APU2 documentation patch
Hello Kyösti Mälkki, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32907
to look at the new patch set (#6).
Change subject: Documentation: Add PC Engines apu1 ......................................................................
Documentation: Add PC Engines apu1
Describe how to run coreboot on the PC Engines apu1 mainboard.
Change-Id: If79693e893c4afe52bf1c9aa8017ac6f650a96e4 Signed-off-by: Piotr Kleinschmidt piotr.kleinschmidt@3mdeb.com --- M Documentation/mainboard/index.md A Documentation/mainboard/pcengines/apu1.md A Documentation/mainboard/pcengines/apu1_spi.jpg A Documentation/mainboard/pcengines/apu1c1.jpg 4 files changed, 101 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/32907/6
Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32907 )
Change subject: Documentation: Add PC Engines apu1 ......................................................................
Patch Set 6: Code-Review+2
There is some unrelated build failure for Google Rammus (using EDK?). IMO irrelevant, but still confusing.
Hello Kyösti Mälkki, build bot (Jenkins), Michał Żygowski,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32907
to look at the new patch set (#7).
Change subject: Documentation: Add PC Engines apu1 ......................................................................
Documentation: Add PC Engines apu1
Describe how to run coreboot on the PC Engines apu1 mainboard.
Change-Id: If79693e893c4afe52bf1c9aa8017ac6f650a96e4 Signed-off-by: Piotr Kleinschmidt piotr.kleinschmidt@3mdeb.com --- M Documentation/mainboard/index.md A Documentation/mainboard/pcengines/apu1.md A Documentation/mainboard/pcengines/apu1_spi.jpg A Documentation/mainboard/pcengines/apu1c1.jpg 4 files changed, 101 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/32907/7
Hello Kyösti Mälkki, build bot (Jenkins), Michał Żygowski,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32907
to look at the new patch set (#8).
Change subject: Documentation: Add PC Engines apu1 ......................................................................
Documentation: Add PC Engines apu1
Describe how to run coreboot on the PC Engines apu1 mainboard.
Change-Id: If79693e893c4afe52bf1c9aa8017ac6f650a96e4 Signed-off-by: Piotr Kleinschmidt piotr.kleinschmidt@3mdeb.com --- M Documentation/mainboard/index.md A Documentation/mainboard/pcengines/apu1.md A Documentation/mainboard/pcengines/apu1_spi.jpg A Documentation/mainboard/pcengines/apu1c1.jpg 4 files changed, 101 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/32907/8
Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32907 )
Change subject: Documentation: Add PC Engines apu1 ......................................................................
Patch Set 8: Code-Review+2
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32907 )
Change subject: Documentation: Add PC Engines apu1 ......................................................................
Patch Set 8: Code-Review+1
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32907 )
Change subject: Documentation: Add PC Engines apu1 ......................................................................
Patch Set 8: Code-Review+2
Kyösti Mälkki has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/32907 )
Change subject: Documentation: Add PC Engines apu1 ......................................................................
Documentation: Add PC Engines apu1
Describe how to run coreboot on the PC Engines apu1 mainboard.
Change-Id: If79693e893c4afe52bf1c9aa8017ac6f650a96e4 Signed-off-by: Piotr Kleinschmidt piotr.kleinschmidt@3mdeb.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/32907 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Michał Żygowski michal.zygowski@3mdeb.com Reviewed-by: Paul Menzel paulepanter@users.sourceforge.net Reviewed-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M Documentation/mainboard/index.md A Documentation/mainboard/pcengines/apu1.md A Documentation/mainboard/pcengines/apu1_spi.jpg A Documentation/mainboard/pcengines/apu1c1.jpg 4 files changed, 101 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Kyösti Mälkki: Looks good to me, approved Paul Menzel: Looks good to me, but someone else must approve Michał Żygowski: Looks good to me, approved
diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 03af2c3..205964f 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -90,6 +90,10 @@
- [RK9 Flash Header](roda/rk9/flash_header.md)
+## PC Engines + +- [APU1](pcengines/apu1.md) + ## SiFive
- [SiFive HiFive Unleashed](sifive/hifive-unleashed.md) diff --git a/Documentation/mainboard/pcengines/apu1.md b/Documentation/mainboard/pcengines/apu1.md new file mode 100644 index 0000000..ccadd63 --- /dev/null +++ b/Documentation/mainboard/pcengines/apu1.md @@ -0,0 +1,97 @@ +# PC Engines APU1 + +This page describes how to run coreboot on PC Engines APU1 platform. + +## Technology + +```eval_rst ++------------+--------------------------------------------------------+ +| CPU | AMD G series T40E APU | ++------------+--------------------------------------------------------+ +| CPU core | 1 GHz dual core (Bobcat core) with 64 bit support | +| | 32K data + 32K instruction + 512KB L2 cache per core | ++------------+--------------------------------------------------------+ +| DRAM | 2 or 4 GB DDR3-1066 DRAM | ++------------+--------------------------------------------------------+ +| Boot | From SD card, USB, mSATA, SATA | ++------------+--------------------------------------------------------+ +| Power | 6 to 12W of 12V power | ++------------+--------------------------------------------------------+ +| Firmware | coreboot with support for iPXE and USB boot | ++------------+--------------------------------------------------------+ +``` + +## Flashing coreboot + +```eval_rst ++---------------------+--------------------------+ +| Type | Value | ++=====================+==========================+ +| Socketed flash | no | ++---------------------+--------------------------+ +| Model | MX25L1606E | ++---------------------+--------------------------+ +| Size | 2 MiB | ++---------------------+--------------------------+ +| Package | SOP-8 | ++---------------------+--------------------------+ +| Write protection | jumper on WP# pin | ++---------------------+--------------------------+ +| Dual BIOS feature | no | ++---------------------+--------------------------+ +| Internal flashing | yes | ++---------------------+--------------------------+ +``` + +### Internal programming + +The SPI flash can be accessed using [flashrom]. It is important to execute +command with a `-c <chipname>` argument: + + flashrom -p internal -c "MX25L1606E" -w coreboot.rom + +### External programming + +**IMPORTANT**: When programming SPI flash, first you need to enter apu1 in S5 +(Soft-off) power state. S5 state can be forced by shorting power button pin on +J2 header. + +The external access to flash chip is available through standard SOP-8 clip or +SOP-8 header next to the flash chip on the board. Notice that not all boards +have a header soldered down originally. Hence, there could be an empty slot with +8 eyelets, so you can solder down a header on your own. The SPI flash chip and +SPI header are marked in the picture below. Also there is SPI header pin layout +included. Notice, that signatures at the schematic can be ambiguous: +- J12 SPIDI = U35 SO = MISO +- J12 SPIDO = U35 SI = MOSI + +There is no restrictions as to the programmer device. It is only recommended to +flash firmware without supplying power. External programming can be performed, +for example using OrangePi and Armbian. You can exploit linux_spi driver which +provide communication with SPI devices. Example command to program SPI flash +with OrangePi using linux_spi: + + flashrom -w coreboot.rom -p linux_spi:dev=/dev/spidev1.0,spispeed=16000 -c + "MX25L1606E" + + +**apu1 platform with marked in SPI header and SPI flash chip** + +![][apu1c1_flash] + +**SPI header pin layout** + +![][spi_header] + + +### Schematics + +PC Engines APU platform schematics are available for free on PC Engines official +site. Depending on the configuration: +[apu1c](https://www.pcengines.ch/schema/apu1c.pdf) and +[apu1d](https://www.pcengines.ch/schema/apu1d.pdf). + + +[apu1c1_flash]: apu1c1.jpg +[spi_header]: apu1_spi.jpg +[flashrom]: https://flashrom.org/Flashrom diff --git a/Documentation/mainboard/pcengines/apu1_spi.jpg b/Documentation/mainboard/pcengines/apu1_spi.jpg new file mode 100644 index 0000000..0746733 --- /dev/null +++ b/Documentation/mainboard/pcengines/apu1_spi.jpg Binary files differ diff --git a/Documentation/mainboard/pcengines/apu1c1.jpg b/Documentation/mainboard/pcengines/apu1c1.jpg new file mode 100644 index 0000000..7ecb41a --- /dev/null +++ b/Documentation/mainboard/pcengines/apu1c1.jpg Binary files differ
-
Kyösti Mälkki (Code Review) -
Michał Żygowski (Code Review)
-
Paul Menzel (Code Review)
-
Piotr Kleinschmidt (Code Review)