[XS] Change in coreboot[master]: soc/intel/xeon_sp/spr: Add chip config to enable x2apic

[Naresh Solanki (Code Review)]

Naresh Solanki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75581?usp=email )

Change subject: soc/intel/xeon_sp/spr: Add chip config to enable x2apic
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soc/intel/xeon_sp/spr: Add chip config to enable x2apic

Add chip config to enable x2apic from mainboard devicetree.

TEST=Build for sbp1.

Signed-off-by: Naresh Solanki 
Change-Id: I81e9f473d0400173afd25278845be5ff34fd7e04
---
M src/soc/intel/xeon_sp/spr/chip.h
M src/soc/intel/xeon_sp/spr/romstage.c
2 files changed, 2 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/75581/1

diff --git a/src/soc/intel/xeon_sp/spr/chip.h b/src/soc/intel/xeon_sp/spr/chip.h
index 28af550..5144372 100644
--- a/src/soc/intel/xeon_sp/spr/chip.h
+++ b/src/soc/intel/xeon_sp/spr/chip.h
@@ -46,6 +46,7 @@
    uint32_t pstate_req_ratio;

uint8_t vtd_support;
+	uint8_t x2apic;

/* Generic IO decode ranges */
    uint32_t gen1_dec;
diff --git a/src/soc/intel/xeon_sp/spr/romstage.c b/src/soc/intel/xeon_sp/spr/romstage.c
index 8f4e98e..8893bf6 100644
--- a/src/soc/intel/xeon_sp/spr/romstage.c
+++ b/src/soc/intel/xeon_sp/spr/romstage.c
@@ -164,7 +164,7 @@
     * coreboot currently can only switch from XAPIC to X2APIC,
     * so always select XAPIC mode here.
     */
-	m_cfg->X2apic = 0;
+	m_cfg->X2apic = config->x2apic;

m_cfg->serialDebugMsgLvl = 0x3;