Change in coreboot[master]: soc/intel/jasperlake: Add CdClock frequency config

[Subrata Banik (Code Review)]

Attention is currently required from: Nico Huber, Jamie Chen, Henry Sun, Tim Wawrzynczak, Paul Menzel, Ren Kuo, Simon Yang, Kane Chen, Patrick Rudolph.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60009 )

Change subject: soc/intel/jasperlake: Add CdClock frequency config
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Patch Set 17:

(1 comment)

File src/soc/intel/jasperlake/fsp_params.c:

https://review.coreboot.org/c/coreboot/+/60009/comment/edd55f96_ce15e17a 
PS17, Line 212: 	params->CdClock = config->cd_clock ? config->cd_clock - 1 : 0xff;
> So is the comment in `src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspsUpd.h` wrong? […]

I guess there are 2 problems

1. Default value what FSP assign to this UPD is 0xFF which is auto but help text says its '0'.

2. These entire UPD values are '0' based instead '1', meaning
0: 172.8 Mhz,
1: 180 Mhz,
2: 190 Mhz, 
...
etc.

Is that correct understanding @Karthik?

I remember reporting this problem to Intel FSP team earlier and its been fixed from TGL/ADL. I don't see the same issue in ADL

https://github.com/coreboot/coreboot/blob/master/src/vendorcode/intel/fsp/fs...