Change in coreboot[master]: soc/amd/common/include/spi: fix SPI_FIFO_LAST_BYTE define

[Felix Held (Code Review)]

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60116 )

Change subject: soc/amd/common/include/spi: fix SPI_FIFO_LAST_BYTE define
......................................................................

soc/amd/common/include/spi: fix SPI_FIFO_LAST_BYTE define

The last byte of the SPI FIFO SPI_FIFO_LAST_BYTE is at offset 0xc6 of
the SPI controller's MMIO region for Stoneyridge and Picasso. Both
SPI_FIFO_LAST_BYTE and SPI_FIFO_DEPTH had an off-by-one error that ended
up cancelling out each other, so the resulting value for SPI_FIFO_DEPTH
isn't changed.

TEST=Timeless build results in identical image for Mandolin.

Signed-off-by: Felix Held 
Change-Id: I1676be902ccf57e2e9f69d81251b4315866a0628
---
M src/soc/amd/common/block/include/amdblocks/spi.h
1 file changed, 2 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/60116/1

diff --git a/src/soc/amd/common/block/include/amdblocks/spi.h b/src/soc/amd/common/block/include/amdblocks/spi.h
index 5c3bd0e..4efed68 100644
--- a/src/soc/amd/common/block/include/amdblocks/spi.h
+++ b/src/soc/amd/common/block/include/amdblocks/spi.h
@@ -71,8 +71,8 @@
 #define   SPI_RD4DW_EN_HOST		BIT(15)

#define SPI_FIFO			0x80
-#define SPI_FIFO_LAST_BYTE		0xc7
-#define SPI_FIFO_DEPTH			(SPI_FIFO_LAST_BYTE - SPI_FIFO)
+#define SPI_FIFO_LAST_BYTE		0xc6
+#define SPI_FIFO_DEPTH			(SPI_FIFO_LAST_BYTE - SPI_FIFO + 1)

struct spi_config {
    /*