Change in coreboot[master]: soc/intel/jsl: Add CdClock config

[Simon Yang (Code Review)]

Attention is currently required from: Jamie Chen, Henry Sun, Paul Menzel, Kane Chen, Patrick Rudolph, Karthik Ramasubramanian.
Simon Yang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60009 )

Change subject: soc/intel/jsl: Add CdClock config
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Patch Set 9:

(1 comment)

Commit Message:

https://review.coreboot.org/c/coreboot/+/60009/comment/2a32ba58_effdfbdb 
PS7, Line 10:
> 0xff is the default value of CdClock inside of FSP.

Done