Attention is currently required from: Patrick Rudolph, Christian Walter. Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58368 )
Change subject: mb/prodrive/hermes: Map PCIe clocks to root ports ......................................................................
mb/prodrive/hermes: Map PCIe clocks to root ports
Map each PCIe clock source to the corresponding root port.
Change-Id: I0515877a36d42fb8858a0f0b3c0af1199a18d9af Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/prodrive/hermes/devicetree.cb 1 file changed, 14 insertions(+), 14 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/58368/1
diff --git a/src/mainboard/prodrive/hermes/devicetree.cb b/src/mainboard/prodrive/hermes/devicetree.cb index cd99839..e4bcf7b 100644 --- a/src/mainboard/prodrive/hermes/devicetree.cb +++ b/src/mainboard/prodrive/hermes/devicetree.cb @@ -27,20 +27,20 @@ register "PchHdaDspEnable" = "0" register "PchHdaAudioLinkHda" = "1"
- register "PcieClkSrcUsage[0]" = "PCIE_CLK_FREE" # PCIe Slot1 - register "PcieClkSrcUsage[1]" = "PCIE_CLK_FREE" # PCIe Slot2 - register "PcieClkSrcUsage[2]" = "PCIE_CLK_FREE" # PCIe Slot4 - register "PcieClkSrcUsage[3]" = "PCIE_CLK_FREE" # PCIe Slot6 - register "PcieClkSrcUsage[4]" = "PCIE_CLK_FREE" # RP9 M2 Slot M x4 - register "PcieClkSrcUsage[5]" = "PCIE_CLK_FREE" # RP16 M2 Slot E x1 - register "PcieClkSrcUsage[6]" = "PCIE_CLK_FREE" # BMC - register "PcieClkSrcUsage[7]" = "PCIE_CLK_FREE" # PHY 3 - register "PcieClkSrcUsage[8]" = "PCIE_CLK_FREE" # PCIe Slot3 - register "PcieClkSrcUsage[9]" = "PCIE_CLK_FREE" # PHY 4 - register "PcieClkSrcUsage[10]" = "PCIE_CLK_FREE" # PHY 2 - register "PcieClkSrcUsage[11]" = "PCIE_CLK_FREE" # PHY 1 - register "PcieClkSrcUsage[12]" = "PCIE_CLK_FREE" # PHY 0 - register "PcieClkSrcUsage[13]" = "PCIE_CLK_FREE" # PB + register "PcieClkSrcUsage[0]" = "20" # PCIe Slot1 + register "PcieClkSrcUsage[1]" = "0x40" # PCIe Slot2 + register "PcieClkSrcUsage[2]" = "0x42" # PCIe Slot4 + register "PcieClkSrcUsage[3]" = "0x41" # PCIe Slot6 + register "PcieClkSrcUsage[4]" = "8" # RP9 M2 Slot M x4 + register "PcieClkSrcUsage[5]" = "15" # RP16 M2 Slot E x1 + register "PcieClkSrcUsage[6]" = "14" # BMC + register "PcieClkSrcUsage[7]" = "4" # PHY 3 + register "PcieClkSrcUsage[8]" = "PCIE_CLK_RP0" # PCIe Slot3 + register "PcieClkSrcUsage[9]" = "5" # PHY 4 + register "PcieClkSrcUsage[10]" = "6" # PHY 2 + register "PcieClkSrcUsage[11]" = "7" # PHY 1 + register "PcieClkSrcUsage[12]" = "13" # PHY 0 + register "PcieClkSrcUsage[13]" = "0x42" # PB register "PcieClkSrcUsage[14]" = "PCIE_CLK_NOTUSED" register "PcieClkSrcUsage[15]" = "PCIE_CLK_NOTUSED"