Change in coreboot[master]: soc/amd/picasso/soc_util: add comment on the silicon and soc types
Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42838 )
Change subject: soc/amd/picasso/soc_util: add comment on the silicon and soc types ......................................................................
soc/amd/picasso/soc_util: add comment on the silicon and soc types
Change-Id: I71704ab292edf8bd343370e6b72c47a8f3aceffd Signed-off-by: Felix Held felix-coreboot@felixheld.de --- M src/soc/amd/picasso/soc_util.c 1 file changed, 8 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/42838/1
diff --git a/src/soc/amd/picasso/soc_util.c b/src/soc/amd/picasso/soc_util.c index 8a1f8ef..887a71b 100644 --- a/src/soc/amd/picasso/soc_util.c +++ b/src/soc/amd/picasso/soc_util.c @@ -9,6 +9,14 @@ #include <soc/soc_util.h> #include <types.h>
+/* + * The Zen/Zen+ based APUs can be RV (sometimes called RV1), PCO or RV2 silicon. RV2 has less + * PCIe, USB3 and Displayport connectivity than RV(1) or PCO. A Picasso SoC is always PCO + * silicon, a Dali SoC can either be RV2 or fused-down PCO silicon that has the same + * connectivity as the RV2 one and Pollock is always RV2 silicon. Picasso and Dali are in a FP5 + * package while Pollock is in the smaller FT5 package. + */ + #define SOCKET_TYPE_SHIFT 28 #define SOCKET_TYPSE_MASK (0xf << SOCKET_TYPE_SHIFT)
Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42838 )
Change subject: soc/amd/picasso/soc_util: add comment on the silicon and soc types ......................................................................
Patch Set 1: Code-Review+2
Rob Barnes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42838 )
Change subject: soc/amd/picasso/soc_util: add comment on the silicon and soc types ......................................................................
Patch Set 1: Code-Review+1
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42838 )
Change subject: soc/amd/picasso/soc_util: add comment on the silicon and soc types ......................................................................
Patch Set 3: Code-Review+2
Thank you!
Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Angel Pons, Rob Barnes,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42838
to look at the new patch set (#4).
Change subject: soc/amd/picasso/soc_util: add comment on the silicon and soc types ......................................................................
soc/amd/picasso/soc_util: add comment on the silicon and soc types
Change-Id: I71704ab292edf8bd343370e6b72c47a8f3aceffd Signed-off-by: Felix Held felix-coreboot@felixheld.de --- M src/soc/amd/picasso/soc_util.c 1 file changed, 8 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/42838/4
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42838 )
Change subject: soc/amd/picasso/soc_util: add comment on the silicon and soc types ......................................................................
Patch Set 4: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/42838/4/src/soc/amd/picasso/soc_uti... File src/soc/amd/picasso/soc_util.c:
https://review.coreboot.org/c/coreboot/+/42838/4/src/soc/amd/picasso/soc_uti... PS4, Line 14: Displayport DisplayPort
Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Paul Menzel, Angel Pons, Rob Barnes,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42838
to look at the new patch set (#5).
Change subject: soc/amd/picasso/soc_util: add comment on the silicon and soc types ......................................................................
soc/amd/picasso/soc_util: add comment on the silicon and soc types
Change-Id: I71704ab292edf8bd343370e6b72c47a8f3aceffd Signed-off-by: Felix Held felix-coreboot@felixheld.de --- M src/soc/amd/picasso/soc_util.c 1 file changed, 8 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/42838/5
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42838 )
Change subject: soc/amd/picasso/soc_util: add comment on the silicon and soc types ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42838/4/src/soc/amd/picasso/soc_uti... File src/soc/amd/picasso/soc_util.c:
https://review.coreboot.org/c/coreboot/+/42838/4/src/soc/amd/picasso/soc_uti... PS4, Line 14: Displayport
DisplayPort
Done
Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42838 )
Change subject: soc/amd/picasso/soc_util: add comment on the silicon and soc types ......................................................................
Patch Set 5: Code-Review+2
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42838 )
Change subject: soc/amd/picasso/soc_util: add comment on the silicon and soc types ......................................................................
Patch Set 5: Code-Review+2
Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/42838 )
Change subject: soc/amd/picasso/soc_util: add comment on the silicon and soc types ......................................................................
soc/amd/picasso/soc_util: add comment on the silicon and soc types
Change-Id: I71704ab292edf8bd343370e6b72c47a8f3aceffd Signed-off-by: Felix Held felix-coreboot@felixheld.de Reviewed-on: https://review.coreboot.org/c/coreboot/+/42838 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Raul Rangel rrangel@chromium.org Reviewed-by: Angel Pons th3fanbus@gmail.com --- M src/soc/amd/picasso/soc_util.c 1 file changed, 8 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved Angel Pons: Looks good to me, approved
diff --git a/src/soc/amd/picasso/soc_util.c b/src/soc/amd/picasso/soc_util.c index 64a97a0..1212920 100644 --- a/src/soc/amd/picasso/soc_util.c +++ b/src/soc/amd/picasso/soc_util.c @@ -9,6 +9,14 @@ #include <soc/soc_util.h> #include <types.h>
+/* + * The Zen/Zen+ based APUs can be RV (sometimes called RV1), PCO or RV2 silicon. RV2 has less + * PCIe, USB3 and DisplayPort connectivity than RV(1) or PCO. A Picasso SoC is always PCO + * silicon, a Dali SoC can either be RV2 or fused-down PCO silicon that has the same + * connectivity as the RV2 one and Pollock is always RV2 silicon. Picasso and Dali are in a FP5 + * package while Pollock is in the smaller FT5 package. + */ + #define SOCKET_TYPE_SHIFT 28 #define SOCKET_TYPSE_MASK (0xf << SOCKET_TYPE_SHIFT)
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Angel Pons (Code Review) -
Felix Held (Code Review)
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Paul Menzel (Code Review)
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Raul Rangel (Code Review)
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Rob Barnes (Code Review)