Change in coreboot[master]: nb/intel/haswell/haswell.h: Do not include `pch.h`

[Angel Pons (Code Review)]

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49944 )

Change subject: nb/intel/haswell/haswell.h: Do not include `pch.h`
......................................................................

nb/intel/haswell/haswell.h: Do not include `pch.h`

Avoid indirect header inclusion, include `pch.h` where necessary.

Change-Id: I6b72976a28ffaad68bcf558c8a13b5c221070522
Signed-off-by: Angel Pons 
---
M src/northbridge/intel/haswell/gma.c
M src/northbridge/intel/haswell/haswell.h
M src/northbridge/intel/haswell/northbridge.c
M src/southbridge/intel/lynxpoint/acpi/lpc.asl
4 files changed, 4 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/49944/1

diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c
index 21053ec..3746fe3 100644
--- a/src/northbridge/intel/haswell/gma.c
+++ b/src/northbridge/intel/haswell/gma.c
@@ -15,6 +15,7 @@
 #include <drivers/intel/gma/libgfxinit.h>
 #include <cpu/intel/haswell/haswell.h>
 #include <drivers/intel/gma/opregion.h>
+#include <southbridge/intel/lynxpoint/pch.h>
 #include <string.h>
 #include <types.h>

diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h
index edca2b6..d28c7d4 100644
--- a/src/northbridge/intel/haswell/haswell.h
+++ b/src/northbridge/intel/haswell/haswell.h
@@ -10,8 +10,6 @@

#include "memmap.h"

-#include <southbridge/intel/lynxpoint/pch.h>
-
 /* Everything below this line is ignored in the DSDT */
 #ifndef __ACPI__

diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c
index 2d19ccd..d253380 100644
--- a/src/northbridge/intel/haswell/northbridge.c
+++ b/src/northbridge/intel/haswell/northbridge.c
@@ -13,6 +13,7 @@
 #include <device/pci_ops.h>
 #include <boot/tables.h>
 #include <security/intel/txt/txt_register.h>
+#include <southbridge/intel/lynxpoint/pch.h>

#include "chip.h"
 #include "haswell.h"
diff --git a/src/southbridge/intel/lynxpoint/acpi/lpc.asl b/src/southbridge/intel/lynxpoint/acpi/lpc.asl
index a823b70..2e230ea 100644
--- a/src/southbridge/intel/lynxpoint/acpi/lpc.asl
+++ b/src/southbridge/intel/lynxpoint/acpi/lpc.asl
@@ -2,6 +2,8 @@

// Intel LPC Bus Device  - 0:1f.0

+#include <southbridge/intel/lynxpoint/pch.h>
+
 Device (LPCB)
 {
    Name (_ADR, 0x001f0000)