Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35772 )
Change subject: nb/intel/nehalem: Move PCH init to sb/intel/ibexpeak ......................................................................
nb/intel/nehalem: Move PCH init to sb/intel/ibexpeak
This change does the following: - Move PCH init code from the common romstage to sb code, this allows for easier reuse in bootblock - Provide a common minimal LPC io decode setup, mainboards can override this in the mainboard_lpc_init if required - Set up LPC gen io decode up in romstage based on devicetree settings - Get rid of unneeded setup of spi_read configuration in BIOS_CNTL as this is already done in the bootblock.
Change-Id: I3f448ad1fdc445c4c1fedbc8497e1025af111412 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/mainboard/lenovo/x201/romstage.c M src/mainboard/packardbell/ms2290/romstage.c M src/northbridge/intel/nehalem/romstage.c M src/southbridge/intel/ibexpeak/Makefile.inc A src/southbridge/intel/ibexpeak/early_pch.c M src/southbridge/intel/ibexpeak/lpc.c M src/southbridge/intel/ibexpeak/pch.h 7 files changed, 99 insertions(+), 84 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/35772/1
diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index 1440c19..81752e8 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -26,28 +26,6 @@
void mainboard_lpc_init(void) { - /* EC Decode Range Port60/64, Port62/66 */ - /* Enable EC, PS/2 Keyboard/Mouse */ - pci_write_config16(PCH_LPC_DEV, LPC_EN, - CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN | - COMA_LPC_EN | GAMEL_LPC_EN); - - pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601); - pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1); - pci_write_config32(PCH_LPC_DEV, LPC_GEN3_DEC, 0x1c1681); - pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, (0x68 & ~3) | 0x00040001); - - pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10); - - pci_write_config32(PCH_LPC_DEV, 0xd0, 0x0); - pci_write_config32(PCH_LPC_DEV, 0xdc, 0x8); - - pci_write_config8(PCH_LPC_DEV, GEN_PMCON_3, - (pci_read_config8(PCH_LPC_DEV, GEN_PMCON_3) & ~2) | 1); - - pci_write_config32(PCH_LPC_DEV, ETR3, - pci_read_config32(PCH_LPC_DEV, ETR3) & ~ETR3_CF9GR); - /* Enable USB Power. We need to do it early for usbdebug to work. */ ec_set_bit(0x3b, 4); } diff --git a/src/mainboard/packardbell/ms2290/romstage.c b/src/mainboard/packardbell/ms2290/romstage.c index b25676b..61e14f2 100644 --- a/src/mainboard/packardbell/ms2290/romstage.c +++ b/src/mainboard/packardbell/ms2290/romstage.c @@ -24,23 +24,6 @@
void mainboard_lpc_init(void) { - /* Enable EC, PS/2 Keyboard/Mouse */ - pci_write_config16(PCH_LPC_DEV, LPC_EN, - CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN | - COMA_LPC_EN); - - pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, (0x68 & ~3) | 0x00040001); - - pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10); - - pci_write_config32(PCH_LPC_DEV, 0xd0, 0x0); - pci_write_config32(PCH_LPC_DEV, 0xdc, 0x8); - - pci_write_config8(PCH_LPC_DEV, GEN_PMCON_3, - (pci_read_config8(PCH_LPC_DEV, GEN_PMCON_3) & ~2) | 1); - - pci_write_config32(PCH_LPC_DEV, ETR3, - pci_read_config32(PCH_LPC_DEV, ETR3) & ~ETR3_CF9GR); }
/* Seems copied from Lenovo Thinkpad x201, might be wrong */ diff --git a/src/northbridge/intel/nehalem/romstage.c b/src/northbridge/intel/nehalem/romstage.c index 7d00e79..c465a99 100644 --- a/src/northbridge/intel/nehalem/romstage.c +++ b/src/northbridge/intel/nehalem/romstage.c @@ -30,8 +30,6 @@ #include <northbridge/intel/nehalem/raminit.h> #include <southbridge/intel/ibexpeak/pch.h> #include <southbridge/intel/ibexpeak/me.h> -#include <southbridge/intel/common/pmclib.h> -#include <southbridge/intel/common/gpio.h>
/* Platform has no romstage entry point under mainboard directory, * so this one is named with prefix mainboard. @@ -47,30 +45,7 @@ /* TODO, make this configurable */ nehalem_early_initialization(NEHALEM_MOBILE);
- /* mainboard_lpc_init */ - mainboard_lpc_init(); - - /* Enable GPIOs */ - pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1); - pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10); - - setup_pch_gpios(&mainboard_gpio_map); - - /* TODO, make this configurable */ - pch_setup_cir(NEHALEM_MOBILE); - - southbridge_configure_default_intmap(); - - /* Must set BIT0 (hiders performance counters PCI), - BIT5-12 are to disable UHCI devices that are not present in - end user devices anyway. */ - RCBA32(FD) = (1 << 5) | (1 << 6) | (1 << 7) | (1 << 8) | (1 << 9) - | (1 << 10) | (1 << 11) | (1 << 12) | (1 << 28) | 1; - - /* Set reserved bit to 1 */ - RCBA32(FD2) = 1; - - early_usb_init(mainboard_usb_ports); + early_pch_init();
/* Initialize console device(s) */ console_init(); diff --git a/src/southbridge/intel/ibexpeak/Makefile.inc b/src/southbridge/intel/ibexpeak/Makefile.inc index 566461d..ed4e696 100644 --- a/src/southbridge/intel/ibexpeak/Makefile.inc +++ b/src/southbridge/intel/ibexpeak/Makefile.inc @@ -37,6 +37,7 @@
smm-y += smihandler.c me.c ../bd82x6x/me_8.x.c ../bd82x6x/pch.c
+romstage-y += early_pch.c romstage-y += early_smbus.c romstage-y +=../bd82x6x/early_me.c romstage-y +=../bd82x6x/me_status.c diff --git a/src/southbridge/intel/ibexpeak/early_pch.c b/src/southbridge/intel/ibexpeak/early_pch.c new file mode 100644 index 0000000..05f8a8f --- /dev/null +++ b/src/southbridge/intel/ibexpeak/early_pch.c @@ -0,0 +1,94 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 Sven Schnelle svens@stackframe.org + * Copyright (C) 2013 Vladimir Serbinenko phcoder@gmail.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <device/pci_ops.h> +#include <northbridge/intel/nehalem/nehalem.h> +#include <southbridge/intel/ibexpeak/pch.h> +#include <southbridge/intel/common/gpio.h> + +#include "chip.h" + +static void early_lpc_init(void) +{ + const struct device *dev = pcidev_on_root(0x1f, 0); + const struct southbridge_intel_ibexpeak_config *config = NULL; + + /* Add some default decode ranges: + - 0x2e/2f, 0x4e/0x4f + - EC/Mouse/KBC 60/64, 62/66 + - 0x3f8 COMA + If more are needed, update in mainboard_lpc_init hook + */ + pci_write_config16(PCH_LPC_DEV, LPC_EN, + CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN | + COMA_LPC_EN); + pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10); + + /* Clear PWR_FLR */ + pci_write_config8(PCH_LPC_DEV, GEN_PMCON_3, + (pci_read_config8(PCH_LPC_DEV, GEN_PMCON_3) & ~2) | 1); + + pci_write_config32(PCH_LPC_DEV, ETR3, + pci_read_config32(PCH_LPC_DEV, ETR3) & ~ETR3_CF9GR); + + /* Set up generic decode ranges */ + if (!dev) + return; + if (dev->chip_info) + config = dev->chip_info; + if (!config) + return; + + pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, config->gen1_dec); + pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, config->gen2_dec); + pci_write_config32(PCH_LPC_DEV, LPC_GEN3_DEC, config->gen3_dec); + pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, config->gen4_dec); +} + +static void early_gpio_init(void) +{ + pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1); + pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10); + + setup_pch_gpios(&mainboard_gpio_map); +} + +static void pch_default_disable(void) +{ + /* Must set BIT0 (hiders performance counters PCI), + BIT5-12 are to disable UHCI devices that are not present in + end user devices anyway. */ + RCBA32(FD) = (1 << 5) | (1 << 6) | (1 << 7) | (1 << 8) | (1 << 9) + | (1 << 10) | (1 << 11) | (1 << 12) | (1 << 28) | 1; + + /* Set reserved bit to 1 */ + RCBA32(FD2) = 1; +} + +void early_pch_init(void) +{ + early_lpc_init(); + mainboard_lpc_init(); + early_gpio_init(); + /* TODO, make this configurable */ + pch_setup_cir(NEHALEM_MOBILE); + southbridge_configure_default_intmap(); + pch_default_disable(); + early_usb_init(mainboard_usb_ports); +} diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index 0d007ad..dceba9a 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -465,18 +465,6 @@ RCBA32_OR(0x21a8, 0x3); }
-static void pch_decode_init(struct device *dev) -{ - config_t *config = dev->chip_info; - - printk(BIOS_DEBUG, "pch_decode_init\n"); - - pci_write_config32(dev, LPC_GEN1_DEC, config->gen1_dec); - pci_write_config32(dev, LPC_GEN2_DEC, config->gen2_dec); - pci_write_config32(dev, LPC_GEN3_DEC, config->gen3_dec); - pci_write_config32(dev, LPC_GEN4_DEC, config->gen4_dec); -} - static void lpc_init(struct device *dev) { printk(BIOS_DEBUG, "pch: lpc_init\n"); @@ -593,12 +581,6 @@ } }
-static void pch_lpc_enable_resources(struct device *dev) -{ - pch_decode_init(dev); - return pci_dev_enable_resources(dev); -} - static void pch_lpc_enable(struct device *dev) { /* Enable PCH Display Port */ @@ -800,7 +782,7 @@ static struct device_operations device_ops = { .read_resources = pch_lpc_read_resources, .set_resources = pci_dev_set_resources, - .enable_resources = pch_lpc_enable_resources, + .enable_resources = pci_dev_enable_resources, .acpi_inject_dsdt_generator = southbridge_inject_dsdt, .acpi_fill_ssdt_generator = southbridge_fill_ssdt, .acpi_name = lpc_acpi_name, diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h index 0254325..421205f 100644 --- a/src/southbridge/intel/ibexpeak/pch.h +++ b/src/southbridge/intel/ibexpeak/pch.h @@ -65,6 +65,8 @@ int smbus_block_write(unsigned device, unsigned cmd, u8 bytes, const u8 *buf); #endif
+void early_pch_init(void); + void early_thermal_init(void); void southbridge_configure_default_intmap(void); void pch_setup_cir(int chipset_type);
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35772 )
Change subject: nb/intel/nehalem: Move PCH init to sb/intel/ibexpeak ......................................................................
Patch Set 1: Code-Review+1
Hello Alexander Couzens, Patrick Rudolph, Paul Menzel, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35772
to look at the new patch set (#3).
Change subject: nb/intel/nehalem: Move PCH init to sb/intel/ibexpeak ......................................................................
nb/intel/nehalem: Move PCH init to sb/intel/ibexpeak
This change does the following: - Move PCH init code from the common romstage to sb code, this allows for easier reuse in bootblock - Provide a common minimal LPC io decode setup, mainboards can override this in the mainboard_lpc_init if required - Set up LPC gen io decode up in romstage based on devicetree settings - Get rid of unneeded setup of spi_read configuration in BIOS_CNTL as this is already done in the bootblock.
Change-Id: I3f448ad1fdc445c4c1fedbc8497e1025af111412 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/mainboard/lenovo/x201/romstage.c M src/mainboard/packardbell/ms2290/romstage.c M src/northbridge/intel/nehalem/romstage.c M src/southbridge/intel/ibexpeak/Makefile.inc A src/southbridge/intel/ibexpeak/early_pch.c M src/southbridge/intel/ibexpeak/lpc.c M src/southbridge/intel/ibexpeak/pch.h 7 files changed, 99 insertions(+), 84 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/35772/3
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35772 )
Change subject: nb/intel/nehalem: Move PCH init to sb/intel/ibexpeak ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35772/6/src/mainboard/packardbell/m... File src/mainboard/packardbell/ms2290/romstage.c:
https://review.coreboot.org/c/coreboot/+/35772/6/src/mainboard/packardbell/m... PS6, Line 32: pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, (0x68 & ~3) | 0x00040001); are lpc gen dec present in devicetree already? Would be great if you could state that in the commit message
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35772 )
Change subject: nb/intel/nehalem: Move PCH init to sb/intel/ibexpeak ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35772/6/src/mainboard/packardbell/m... File src/mainboard/packardbell/ms2290/romstage.c:
https://review.coreboot.org/c/coreboot/+/35772/6/src/mainboard/packardbell/m... PS6, Line 32: pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, (0x68 & ~3) | 0x00040001);
are lpc gen dec present in devicetree already? Would be great if you could state that in the commit message
There was already ramstage code to do that based on the devicetree. I'll update the commit message.
Hello Alexander Couzens, Patrick Rudolph, Paul Menzel, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35772
to look at the new patch set (#7).
Change subject: nb/intel/nehalem: Move PCH init to sb/intel/ibexpeak ......................................................................
nb/intel/nehalem: Move PCH init to sb/intel/ibexpeak
This change does the following: - Move PCH init code from the common romstage to sb code, this allows for easier reuse in bootblock - Provide a common minimal LPC io decode setup, mainboards can override this in the mainboard_lpc_init if required - Set up LPC generic IO decode up in romstage based on devicetree settings - Remove the ramstage LPC generic IO decode from ramstage as this is now done in romstage.c - Get rid of unneeded setup of spi_read configuration in BIOS_CNTL as this is already done in the bootblock.
Change-Id: I3f448ad1fdc445c4c1fedbc8497e1025af111412 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/mainboard/lenovo/x201/romstage.c M src/mainboard/packardbell/ms2290/romstage.c M src/northbridge/intel/nehalem/romstage.c M src/southbridge/intel/ibexpeak/Makefile.inc A src/southbridge/intel/ibexpeak/early_pch.c M src/southbridge/intel/ibexpeak/lpc.c M src/southbridge/intel/ibexpeak/pch.h 7 files changed, 99 insertions(+), 84 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/35772/7
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35772 )
Change subject: nb/intel/nehalem: Move PCH init to sb/intel/ibexpeak ......................................................................
Patch Set 7: Code-Review+1
Hello Alexander Couzens, Patrick Rudolph, Angel Pons, Paul Menzel, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35772
to look at the new patch set (#8).
Change subject: nb/intel/nehalem: Move PCH init to sb/intel/ibexpeak ......................................................................
nb/intel/nehalem: Move PCH init to sb/intel/ibexpeak
This change does the following: - Move PCH init code from the common romstage to sb code, this allows for easier reuse in bootblock - Provide a common minimal LPC io decode setup, mainboards can override this in the mainboard_lpc_init if required - Set up LPC generic IO decode up in romstage based on devicetree settings - Remove the ramstage LPC generic IO decode from ramstage as this is now done in romstage.c - Get rid of unneeded setup of spi_read configuration in BIOS_CNTL as this is already done in the bootblock.
Change-Id: I3f448ad1fdc445c4c1fedbc8497e1025af111412 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/mainboard/lenovo/x201/romstage.c M src/mainboard/packardbell/ms2290/romstage.c M src/northbridge/intel/nehalem/romstage.c M src/southbridge/intel/ibexpeak/Makefile.inc A src/southbridge/intel/ibexpeak/early_pch.c M src/southbridge/intel/ibexpeak/lpc.c M src/southbridge/intel/ibexpeak/pch.h 7 files changed, 98 insertions(+), 83 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/35772/8
Hello Alexander Couzens, Patrick Rudolph, Angel Pons, Paul Menzel, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35772
to look at the new patch set (#9).
Change subject: nb/intel/nehalem: Move PCH init to sb/intel/ibexpeak ......................................................................
nb/intel/nehalem: Move PCH init to sb/intel/ibexpeak
This change does the following: - Move PCH init code from the common romstage to sb code, this allows for easier reuse in bootblock - Provide a common minimal LPC io decode setup, mainboards can override this in the mainboard_lpc_init if required - Set up LPC generic IO decode up in romstage based on devicetree settings - Remove the ramstage LPC generic IO decode from ramstage as this is now done in romstage.c - Get rid of unneeded setup of spi_read configuration in BIOS_CNTL as this is already done in the bootblock.
Change-Id: I3f448ad1fdc445c4c1fedbc8497e1025af111412 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/mainboard/lenovo/x201/romstage.c M src/mainboard/packardbell/ms2290/romstage.c M src/northbridge/intel/nehalem/romstage.c M src/southbridge/intel/ibexpeak/Makefile.inc A src/southbridge/intel/ibexpeak/early_pch.c M src/southbridge/intel/ibexpeak/lpc.c M src/southbridge/intel/ibexpeak/pch.h 7 files changed, 98 insertions(+), 83 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/35772/9
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35772 )
Change subject: nb/intel/nehalem: Move PCH init to sb/intel/ibexpeak ......................................................................
Patch Set 9:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35772/6/src/mainboard/packardbell/m... File src/mainboard/packardbell/ms2290/romstage.c:
https://review.coreboot.org/c/coreboot/+/35772/6/src/mainboard/packardbell/m... PS6, Line 32: pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, (0x68 & ~3) | 0x00040001);
are lpc gen dec present in devicetree already? Would be great if you could state that in the commi […]
Done
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35772 )
Change subject: nb/intel/nehalem: Move PCH init to sb/intel/ibexpeak ......................................................................
Patch Set 9: Code-Review+2