Change in coreboot[master]: [WIP]Cezanne FSP wrapper: Sync with PI 1.0.0.5

[Bao Zheng (Code Review)]

Attention is currently required from: Zheng Bao.
Hello Zheng Bao,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/59687

to review the following change.

Change subject: [WIP]Cezanne FSP wrapper: Sync with PI 1.0.0.5
......................................................................

[WIP]Cezanne FSP wrapper: Sync with PI 1.0.0.5

New PI 1.0.0.5 has more data in hob of DMI. The coreboot also need to change.

BUG=b:204732649

Need to wait new FSP binary.

Change-Id: Id95c37a0d7027d75afddf9d7528ff41ae3a347f5
Signed-off-by: Zheng Bao 
---
M src/vendorcode/amd/fsp/cezanne/dmi_info.h
1 file changed, 3 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/59687/1

diff --git a/src/vendorcode/amd/fsp/cezanne/dmi_info.h b/src/vendorcode/amd/fsp/cezanne/dmi_info.h
index 304f387..d2c26fa 100644
--- a/src/vendorcode/amd/fsp/cezanne/dmi_info.h
+++ b/src/vendorcode/amd/fsp/cezanne/dmi_info.h
@@ -227,6 +227,9 @@
   OUT UINT64                    VolatileSize;           ///< Size of the Volatile portion of the memory device in Bytes, if any.
   OUT UINT64                    CacheSize;              ///< Size of the Cache portion of the memory device in Bytes, if any.
   OUT UINT64                    LogicalSize;            ///< Size of the Logical memory device in Bytes.
+  // SMBIOS 3.3
+  OUT UINT32                    ExtendedSpeed;          ///< Extended Speed
+  OUT UINT32                    ExtendedConfiguredMemorySpeed; ///< Extended Configured memory speed
 } __packed TYPE17_DMI_INFO;

/// Collection of pointers to the DMI records