Change in coreboot[master]: sb/amd/{agesa,pi}/hudson: enable support for AMD common ACPIMMIO blocks
Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37177 )
Change subject: sb/amd/{agesa,pi}/hudson: enable support for AMD common ACPIMMIO blocks ......................................................................
sb/amd/{agesa,pi}/hudson: enable support for AMD common ACPIMMIO blocks
Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Change-Id: Idd014f1ba85efff0c98a0c5ab60d775ac93cbc60 --- M src/mainboard/pcengines/apu2/mainboard.c M src/southbridge/amd/agesa/hudson/Kconfig M src/southbridge/amd/agesa/hudson/Makefile.inc M src/southbridge/amd/agesa/hudson/hudson.c M src/southbridge/amd/agesa/hudson/hudson.h A src/southbridge/amd/agesa/hudson/include/soc/iomap.h M src/southbridge/amd/agesa/hudson/lpc.c M src/southbridge/amd/agesa/hudson/smbus.c M src/southbridge/amd/agesa/hudson/smbus.h M src/southbridge/amd/agesa/hudson/smi.c M src/southbridge/amd/agesa/hudson/smi.h M src/southbridge/amd/pi/hudson/Kconfig M src/southbridge/amd/pi/hudson/Makefile.inc M src/southbridge/amd/pi/hudson/hudson.c M src/southbridge/amd/pi/hudson/hudson.h A src/southbridge/amd/pi/hudson/include/soc/iomap.h M src/southbridge/amd/pi/hudson/lpc.c M src/southbridge/amd/pi/hudson/smbus.c M src/southbridge/amd/pi/hudson/smbus.h M src/southbridge/amd/pi/hudson/smi.c M src/southbridge/amd/pi/hudson/smi.h 21 files changed, 162 insertions(+), 101 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/37177/1
diff --git a/src/mainboard/pcengines/apu2/mainboard.c b/src/mainboard/pcengines/apu2/mainboard.c index 682120b..d46361c 100644 --- a/src/mainboard/pcengines/apu2/mainboard.c +++ b/src/mainboard/pcengines/apu2/mainboard.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */
+#include <amdblocks/acpimmio.h> #include <device/mmio.h> #include <device/pci_ops.h> #include <console/console.h> diff --git a/src/southbridge/amd/agesa/hudson/Kconfig b/src/southbridge/amd/agesa/hudson/Kconfig index 394a196..93db1a9 100644 --- a/src/southbridge/amd/agesa/hudson/Kconfig +++ b/src/southbridge/amd/agesa/hudson/Kconfig @@ -27,6 +27,9 @@ select HAVE_USBDEBUG_OPTIONS select HAVE_CF9_RESET select HAVE_CF9_RESET_PREPARE + select SOC_AMD_COMMON + select SOC_AMD_COMMON_BLOCK + select SOC_AMD_COMMON_BLOCK_ACPIMMIO
config BOOTBLOCK_SOUTHBRIDGE_INIT string diff --git a/src/southbridge/amd/agesa/hudson/Makefile.inc b/src/southbridge/amd/agesa/hudson/Makefile.inc index 5cb3755..d392069 100644 --- a/src/southbridge/amd/agesa/hudson/Makefile.inc +++ b/src/southbridge/amd/agesa/hudson/Makefile.inc @@ -1,6 +1,7 @@
CPPFLAGS_x86_32 += -I$(src)/southbridge/amd/agesa/hudson CPPFLAGS_x86_64 += -I$(src)/southbridge/amd/agesa/hudson +CPPFLAGS_common += -I$(src)/southbridge/amd/agesa/hudson/include
romstage-y += smbus.c smbus_spd.c ramstage-y += hudson.c diff --git a/src/southbridge/amd/agesa/hudson/hudson.c b/src/southbridge/amd/agesa/hudson/hudson.c index 4c06e87..d586d33 100644 --- a/src/southbridge/amd/agesa/hudson/hudson.c +++ b/src/southbridge/amd/agesa/hudson/hudson.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */
+#include <amdblocks/acpimmio.h> #include <console/console.h> #include <device/mmio.h> #include <device/device.h> @@ -25,31 +26,6 @@ #include "smbus.h" #include "smi.h"
-/* Offsets from ACPI_MMIO_BASE - * This is defined by AGESA, but we don't include AGESA headers to avoid - * polluting the namespace. - */ -#define PM_MMIO_BASE 0xfed80300 - -void pm_write8(u8 reg, u8 value) -{ - write8((void *)((uintptr_t)PM_MMIO_BASE + reg), value); -} - -u8 pm_read8(u8 reg) -{ - return read8((void *)((uintptr_t)PM_MMIO_BASE + reg)); -} - -void pm_write16(u8 reg, u16 value) -{ - write16((void *)((uintptr_t)PM_MMIO_BASE + reg), value); -} - -u16 pm_read16(u16 reg) -{ - return read16((void *)((uintptr_t)PM_MMIO_BASE + reg)); -}
#define PM_REG_USB_ENABLE 0xef
diff --git a/src/southbridge/amd/agesa/hudson/hudson.h b/src/southbridge/amd/agesa/hudson/hudson.h index 21a2129..18303fc 100644 --- a/src/southbridge/amd/agesa/hudson/hudson.h +++ b/src/southbridge/amd/agesa/hudson/hudson.h @@ -61,11 +61,6 @@ return (CONFIG_HUDSON_SATA_MODE == 0) || (CONFIG_HUDSON_SATA_MODE == 3); }
-void pm_write8(u8 reg, u8 value); -u8 pm_read8(u8 reg); -void pm_write16(u8 reg, u16 value); -u16 pm_read16(u16 reg); - void hudson_lpc_port80(void); void hudson_pci_port80(void); void hudson_clk_output_48Mhz(void); diff --git a/src/southbridge/amd/agesa/hudson/include/soc/iomap.h b/src/southbridge/amd/agesa/hudson/include/soc/iomap.h new file mode 100644 index 0000000..f21a2db --- /dev/null +++ b/src/southbridge/amd/agesa/hudson/include/soc/iomap.h @@ -0,0 +1,72 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Raptor Engineering, LLC + * Copyright 2017 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __AMD_AGESA_HUDSON_IOMAP_H__ +#define __AMD_AGESA_HUDSON_IOMAP_H__ + +/* + * AcpiMmio blocks are at fixed offsets from FED8_0000h and enabled in PMx04[1]. + * All ranges not specified as supported below may, or may not, be listed in + * any documentation but should be considered reserved through FED8_1FFFh. + */ +#include <amdblocks/acpimmio_map.h> +#define SUPPORTS_ACPIMMIO_SMI_BASE 1 /* 0xfed80100 */ +#define SUPPORTS_ACPIMMIO_PMIO_BASE 1 /* 0xfed80300 */ +#define SUPPORTS_ACPIMMIO_BIOSRAM_BASE 1 /* 0xfed80500 */ +#define SUPPORTS_ACPIMMIO_ACPI_BASE 1 /* 0xfed80800 */ +#define SUPPORTS_ACPIMMIO_ASF_BASE 1 /* 0xfed80900 */ +#define SUPPORTS_ACPIMMIO_SMBUS_BASE 1 /* 0xfed80a00 */ +#define SUPPORTS_ACPIMMIO_IOMUX_BASE 1 /* 0xfed80d00 */ +#define SUPPORTS_ACPIMMIO_MISC_BASE 1 /* 0xfed80e00 */ +#define SUPPORTS_ACPIMMIO_GPIO0_BASE 1 /* 0xfed81500 */ +#define SUPPORTS_ACPIMMIO_GPIO1_BASE 1 /* 0xfed81800 */ +#define SUPPORTS_ACPIMMIO_GPIO2_BASE 1 /* 0xfed81700 */ +#define SUPPORTS_ACPIMMIO_XHCIPM_BASE 1 /* 0xfed81c00 */ +#define SUPPORTS_ACPIMMIO_AOAC_BASE 1 /* 0xfed81e00 */ + +#define ALINK_AHB_ADDRESS 0xfedc0000 + +/* I2C fixed address */ +#define I2C_BASE_ADDRESS 0xfedc2000 +#define I2C_DEVICE_SIZE 0x00001000 +#define I2C_DEVICE_COUNT 4 + +#if CONFIG(HPET_ADDRESS_OVERRIDE) +#error HPET address override is not allowed and must be fixed at 0xfed00000 +#endif +#define HPET_BASE_ADDRESS 0xfed00000 + +#define APU_UART0_BASE 0xfedc6000 +#define APU_UART1_BASE 0xfedc8000 + +#define FLASH_BASE_ADDR ((0xffffffff - CONFIG_ROM_SIZE) + 1) + +/* I/O Ranges */ +#define SMB_BASE_ADDR 0xb00 +#define PM2_INDEX 0xcd0 +#define PM2_DATA 0xcd1 +#define BIOSRAM_INDEX 0xcd4 +#define BIOSRAM_DATA 0xcd5 +#define AB_INDX 0xcd8 +#define AB_DATA (AB_INDX+4) +#define SYS_RESET 0xcf9 + +/* BiosRam Ranges at 0xfed80500 or I/O 0xcd4/0xcd5 */ +#define BIOSRAM_CBMEM_TOP 0xf0 /* 4 bytes */ +#define BIOSRAM_UMA_SIZE 0xf4 /* 4 bytes */ +#define BIOSRAM_UMA_BASE 0xf8 /* 8 bytes */ + +#endif /* __AMD_AGESA_HUDSON_IOMAP_H__ */ diff --git a/src/southbridge/amd/agesa/hudson/lpc.c b/src/southbridge/amd/agesa/hudson/lpc.c index eed1aec..9c65d04 100644 --- a/src/southbridge/amd/agesa/hudson/lpc.c +++ b/src/southbridge/amd/agesa/hudson/lpc.c @@ -14,6 +14,7 @@ * GNU General Public License for more details. */
+#include <amdblocks/acpimmio.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> diff --git a/src/southbridge/amd/agesa/hudson/smbus.c b/src/southbridge/amd/agesa/hudson/smbus.c index 783c324..1a9043e 100644 --- a/src/southbridge/amd/agesa/hudson/smbus.c +++ b/src/southbridge/amd/agesa/hudson/smbus.c @@ -16,6 +16,7 @@ #ifndef _HUDSON_SMBUS_C_ #define _HUDSON_SMBUS_C_
+#include <amdblocks/acpimmio.h> #include <arch/io.h> #include <stdint.h> #include "smbus.h" diff --git a/src/southbridge/amd/agesa/hudson/smbus.h b/src/southbridge/amd/agesa/hudson/smbus.h index 7bf29ad..401091b 100644 --- a/src/southbridge/amd/agesa/hudson/smbus.h +++ b/src/southbridge/amd/agesa/hudson/smbus.h @@ -39,9 +39,6 @@ #define RC_INDXC 1 #define RC_INDXP 3
-#define AB_INDX 0xCD8 -#define AB_DATA (AB_INDX+4) - /* Between 1-10 seconds, We should never timeout normally * Longer than this is just painful when a timeout condition occurs. */ diff --git a/src/southbridge/amd/agesa/hudson/smi.c b/src/southbridge/amd/agesa/hudson/smi.c index f8196b4..7f76cd5 100644 --- a/src/southbridge/amd/agesa/hudson/smi.c +++ b/src/southbridge/amd/agesa/hudson/smi.c @@ -18,6 +18,7 @@ * Utilities for SMM setup */
+#include <amdblocks/acpimmio.h> #include <console/console.h> #include <cpu/x86/smm.h>
diff --git a/src/southbridge/amd/agesa/hudson/smi.h b/src/southbridge/amd/agesa/hudson/smi.h index 5e0c09a..b1156a8 100644 --- a/src/southbridge/amd/agesa/hudson/smi.h +++ b/src/southbridge/amd/agesa/hudson/smi.h @@ -47,26 +47,6 @@ SMI_LVL_HIGH = 1, };
-static inline uint32_t smi_read32(uint8_t offset) -{ - return read32((void *)((uintptr_t)SMI_BASE + offset)); -} - -static inline void smi_write32(uint8_t offset, uint32_t value) -{ - write32((void *)((uintptr_t)SMI_BASE + offset), value); -} - -static inline uint16_t smi_read16(uint8_t offset) -{ - return read16((void *)((uintptr_t)SMI_BASE + offset)); -} - -static inline void smi_write16(uint8_t offset, uint16_t value) -{ - write16((void *)((uintptr_t)SMI_BASE + offset), value); -} - void hudson_configure_gevent_smi(uint8_t gevent, uint8_t mode, uint8_t level); void hudson_disable_gevent_smi(uint8_t gevent); void hudson_enable_acpi_cmd_smi(void); diff --git a/src/southbridge/amd/pi/hudson/Kconfig b/src/southbridge/amd/pi/hudson/Kconfig index c636df8..01f3937 100644 --- a/src/southbridge/amd/pi/hudson/Kconfig +++ b/src/southbridge/amd/pi/hudson/Kconfig @@ -30,6 +30,9 @@ select HAVE_USBDEBUG_OPTIONS select HAVE_CF9_RESET select HAVE_CF9_RESET_PREPARE + select SOC_AMD_COMMON + select SOC_AMD_COMMON_BLOCK + select SOC_AMD_COMMON_BLOCK_ACPIMMIO
config BOOTBLOCK_SOUTHBRIDGE_INIT string diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc index 0eccadb..562b312 100644 --- a/src/southbridge/amd/pi/hudson/Makefile.inc +++ b/src/southbridge/amd/pi/hudson/Makefile.inc @@ -63,6 +63,8 @@ smm-y += smihandler.c smm-y += smi_util.c
+CPPFLAGS_common += -I$(src)/southbridge/amd/pi/hudson/include + # ROMSIG At ROMBASE + 0x20000: # +-----------+---------------+----------------+------------+ # |0x55AA55AA |EC ROM Address |GEC ROM Address |USB3 ROM | diff --git a/src/southbridge/amd/pi/hudson/hudson.c b/src/southbridge/amd/pi/hudson/hudson.c index a331c57..51c37a1 100644 --- a/src/southbridge/amd/pi/hudson/hudson.c +++ b/src/southbridge/amd/pi/hudson/hudson.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */
+#include <amdblocks/acpimmio.h> #include <console/console.h> #include <arch/io.h> #include <device/mmio.h> @@ -36,26 +37,6 @@ return (int)tmp; }
-void pm_write8(u8 reg, u8 value) -{ - write8((void *)(PM_MMIO_BASE + reg), value); -} - -u8 pm_read8(u8 reg) -{ - return read8((void *)(PM_MMIO_BASE + reg)); -} - -void pm_write16(u8 reg, u16 value) -{ - write16((void *)(PM_MMIO_BASE + reg), value); -} - -u16 pm_read16(u16 reg) -{ - return read16((void *)(PM_MMIO_BASE + reg)); -} - void hudson_enable(struct device *dev) { printk(BIOS_DEBUG, "hudson_enable()\n"); diff --git a/src/southbridge/amd/pi/hudson/hudson.h b/src/southbridge/amd/pi/hudson/hudson.h index 9511a6a..b24629f 100644 --- a/src/southbridge/amd/pi/hudson/hudson.h +++ b/src/southbridge/amd/pi/hudson/hudson.h @@ -169,11 +169,6 @@ return (CONFIG_HUDSON_SATA_MODE == 0) || (CONFIG_HUDSON_SATA_MODE == 3); }
-void pm_write8(u8 reg, u8 value); -u8 pm_read8(u8 reg); -void pm_write16(u8 reg, u16 value); -u16 pm_read16(u16 reg); - void hudson_lpc_port80(void); void hudson_lpc_decode(void); void hudson_pci_port80(void); diff --git a/src/southbridge/amd/pi/hudson/include/soc/iomap.h b/src/southbridge/amd/pi/hudson/include/soc/iomap.h new file mode 100644 index 0000000..0a32429 --- /dev/null +++ b/src/southbridge/amd/pi/hudson/include/soc/iomap.h @@ -0,0 +1,72 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Raptor Engineering, LLC + * Copyright 2017 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __AMD_PI_HUDSON_IOMAP_H__ +#define __AMD_PI_HUDSON_IOMAP_H__ + +/* + * AcpiMmio blocks are at fixed offsets from FED8_0000h and enabled in PMx04[1]. + * All ranges not specified as supported below may, or may not, be listed in + * any documentation but should be considered reserved through FED8_1FFFh. + */ +#include <amdblocks/acpimmio_map.h> +#define SUPPORTS_ACPIMMIO_SMI_BASE 1 /* 0xfed80100 */ +#define SUPPORTS_ACPIMMIO_PMIO_BASE 1 /* 0xfed80300 */ +#define SUPPORTS_ACPIMMIO_BIOSRAM_BASE 1 /* 0xfed80500 */ +#define SUPPORTS_ACPIMMIO_ACPI_BASE 1 /* 0xfed80800 */ +#define SUPPORTS_ACPIMMIO_ASF_BASE 1 /* 0xfed80900 */ +#define SUPPORTS_ACPIMMIO_SMBUS_BASE 1 /* 0xfed80a00 */ +#define SUPPORTS_ACPIMMIO_IOMUX_BASE 1 /* 0xfed80d00 */ +#define SUPPORTS_ACPIMMIO_MISC_BASE 1 /* 0xfed80e00 */ +#define SUPPORTS_ACPIMMIO_GPIO0_BASE 1 /* 0xfed81500 */ +#define SUPPORTS_ACPIMMIO_GPIO1_BASE 1 /* 0xfed81800 */ +#define SUPPORTS_ACPIMMIO_GPIO2_BASE 1 /* 0xfed81700 */ +#define SUPPORTS_ACPIMMIO_XHCIPM_BASE 1 /* 0xfed81c00 */ +#define SUPPORTS_ACPIMMIO_AOAC_BASE 1 /* 0xfed81e00 */ + +#define ALINK_AHB_ADDRESS 0xfedc0000 + +/* I2C fixed address */ +#define I2C_BASE_ADDRESS 0xfedc2000 +#define I2C_DEVICE_SIZE 0x00001000 +#define I2C_DEVICE_COUNT 4 + +#if CONFIG(HPET_ADDRESS_OVERRIDE) +#error HPET address override is not allowed and must be fixed at 0xfed00000 +#endif +#define HPET_BASE_ADDRESS 0xfed00000 + +#define APU_UART0_BASE 0xfedc6000 +#define APU_UART1_BASE 0xfedc8000 + +#define FLASH_BASE_ADDR ((0xffffffff - CONFIG_ROM_SIZE) + 1) + +/* I/O Ranges */ +#define SMB_BASE_ADDR 0xb00 +#define PM2_INDEX 0xcd0 +#define PM2_DATA 0xcd1 +#define BIOSRAM_INDEX 0xcd4 +#define BIOSRAM_DATA 0xcd5 +#define AB_INDX 0xcd8 +#define AB_DATA (AB_INDX+4) +#define SYS_RESET 0xcf9 + +/* BiosRam Ranges at 0xfed80500 or I/O 0xcd4/0xcd5 */ +#define BIOSRAM_CBMEM_TOP 0xf0 /* 4 bytes */ +#define BIOSRAM_UMA_SIZE 0xf4 /* 4 bytes */ +#define BIOSRAM_UMA_BASE 0xf8 /* 8 bytes */ + +#endif /* __AMD_PI_HUDSON_IOMAP_H__ */ diff --git a/src/southbridge/amd/pi/hudson/lpc.c b/src/southbridge/amd/pi/hudson/lpc.c index e65fd83..6c3561f 100644 --- a/src/southbridge/amd/pi/hudson/lpc.c +++ b/src/southbridge/amd/pi/hudson/lpc.c @@ -14,6 +14,7 @@ * GNU General Public License for more details. */
+#include <amdblocks/acpimmio.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> diff --git a/src/southbridge/amd/pi/hudson/smbus.c b/src/southbridge/amd/pi/hudson/smbus.c index 783c324..aee7ce3 100644 --- a/src/southbridge/amd/pi/hudson/smbus.c +++ b/src/southbridge/amd/pi/hudson/smbus.c @@ -17,6 +17,7 @@ #define _HUDSON_SMBUS_C_
#include <arch/io.h> +#include <amdblocks/acpimmio.h> #include <stdint.h> #include "smbus.h"
diff --git a/src/southbridge/amd/pi/hudson/smbus.h b/src/southbridge/amd/pi/hudson/smbus.h index ac197a3..d3c0f24 100644 --- a/src/southbridge/amd/pi/hudson/smbus.h +++ b/src/southbridge/amd/pi/hudson/smbus.h @@ -39,9 +39,6 @@ #define RC_INDXC 1 #define RC_INDXP 3
-#define AB_INDX 0xCD8 -#define AB_DATA (AB_INDX+4) - /* Between 1-10 seconds, We should never timeout normally * Longer than this is just painful when a timeout condition occurs. */ diff --git a/src/southbridge/amd/pi/hudson/smi.c b/src/southbridge/amd/pi/hudson/smi.c index f8196b4..7f76cd5 100644 --- a/src/southbridge/amd/pi/hudson/smi.c +++ b/src/southbridge/amd/pi/hudson/smi.c @@ -18,6 +18,7 @@ * Utilities for SMM setup */
+#include <amdblocks/acpimmio.h> #include <console/console.h> #include <cpu/x86/smm.h>
diff --git a/src/southbridge/amd/pi/hudson/smi.h b/src/southbridge/amd/pi/hudson/smi.h index 684dca5..4faee15 100644 --- a/src/southbridge/amd/pi/hudson/smi.h +++ b/src/southbridge/amd/pi/hudson/smi.h @@ -47,26 +47,6 @@ SMI_LVL_HIGH = 1, };
-static inline uint32_t smi_read32(uint8_t offset) -{ - return read32((void *)(SMI_BASE + offset)); -} - -static inline void smi_write32(uint8_t offset, uint32_t value) -{ - write32((void *)(SMI_BASE + offset), value); -} - -static inline uint16_t smi_read16(uint8_t offset) -{ - return read16((void *)(SMI_BASE + offset)); -} - -static inline void smi_write16(uint8_t offset, uint16_t value) -{ - write16((void *)(SMI_BASE + offset), value); -} - void hudson_configure_gevent_smi(uint8_t gevent, uint8_t mode, uint8_t level); void hudson_disable_gevent_smi(uint8_t gevent); void hudson_enable_acpi_cmd_smi(void);
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37177 )
Change subject: sb/amd/{agesa,pi}/hudson: enable support for AMD common ACPIMMIO blocks ......................................................................
Patch Set 1:
Michal, I update CB:18526 (and its parent) before a new push of this one.
Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37177 )
Change subject: sb/amd/{agesa,pi}/hudson: enable support for AMD common ACPIMMIO blocks ......................................................................
Patch Set 1:
Patch Set 1:
Michal, I update CB:18526 (and its parent) before a new push of this one.
Sure, I will wait with rebase until C_ENVIRONMENT_BOOTBLOCK symbol gets removed to not double the rebasing work.
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37177 )
Change subject: sb/amd/{agesa,pi}/hudson: enable support for AMD common ACPIMMIO blocks ......................................................................
Patch Set 1:
(4 comments)
We want to coordinate this with AMD/SilverBack/Google such that soc/amd/common and SOC_AMD_COMMON are usable without copy-pasting headers under southbridge/hudson .
https://review.coreboot.org/c/coreboot/+/37177/1/src/southbridge/amd/agesa/h... File src/southbridge/amd/agesa/hudson/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/37177/1/src/southbridge/amd/agesa/h... PS1, Line 4: CPPFLAGS_common += -I$(src)/southbridge/amd/agesa/hudson/include Lets not introduce include/ there.
https://review.coreboot.org/c/coreboot/+/37177/1/src/southbridge/amd/agesa/h... File src/southbridge/amd/agesa/hudson/include/soc/iomap.h:
https://review.coreboot.org/c/coreboot/+/37177/1/src/southbridge/amd/agesa/h... PS1, Line 5: * Copyright 2017 Google Inc. I guess this is copy from somewhere?
https://review.coreboot.org/c/coreboot/+/37177/1/src/southbridge/amd/agesa/h... PS1, Line 25: #include <amdblocks/acpimmio_map.h> Why?
https://review.coreboot.org/c/coreboot/+/37177/1/src/southbridge/amd/pi/huds... File src/southbridge/amd/pi/hudson/include/soc/iomap.h:
https://review.coreboot.org/c/coreboot/+/37177/1/src/southbridge/amd/pi/huds... PS1, Line 25: #include <amdblocks/acpimmio_map.h> Why ?
Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37177 )
Change subject: sb/amd/{agesa,pi}/hudson: enable support for AMD common ACPIMMIO blocks ......................................................................
Patch Set 1:
Patch Set 1:
(4 comments)
We want to coordinate this with AMD/SilverBack/Google such that soc/amd/common and SOC_AMD_COMMON are usable without copy-pasting headers under southbridge/hudson .
Ohh I see. Could let me know first how I should proceed with this. From your other comments I understood to reuse as much as possible form stoney SoC and work on BIOSRAM for binaryPI.
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37177 )
Change subject: sb/amd/{agesa,pi}/hudson: enable support for AMD common ACPIMMIO blocks ......................................................................
Patch Set 1:
Patch Set 1:
Patch Set 1:
(4 comments)
We want to coordinate this with AMD/SilverBack/Google such that soc/amd/common and SOC_AMD_COMMON are usable without copy-pasting headers under southbridge/hudson .
Ohh I see. Could let me know first how I should proceed with this. From your other comments I understood to reuse as much as possible form stoney SoC and work on BIOSRAM for binaryPI.
If there is a concept in soc/amd/stoneyridge or soc/amd/common that would work for binaryPI and AGESA we should use it. The approach with SOC_AMD_COMMON looks good, we just got to get co-operation and assume Silverback wants to have some ownership of amd/stoneyridge.
I am not so happy how amdblock/acpmmio.h and soc/iomap.h play together, and the guards in acpimmio/mmio_util.c. Preferably common code would not include per-platform headerfiles.
As for BIOSRAM, continue with it for APU2 bootblock.
Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37177 )
Change subject: sb/amd/{agesa,pi}/hudson: enable support for AMD common ACPIMMIO blocks ......................................................................
Patch Set 1:
Patch Set 1:
Patch Set 1:
Patch Set 1:
(4 comments)
We want to coordinate this with AMD/SilverBack/Google such that soc/amd/common and SOC_AMD_COMMON are usable without copy-pasting headers under southbridge/hudson .
Ohh I see. Could let me know first how I should proceed with this. From your other comments I understood to reuse as much as possible form stoney SoC and work on BIOSRAM for binaryPI.
If there is a concept in soc/amd/stoneyridge or soc/amd/common that would work for binaryPI and AGESA we should use it. The approach with SOC_AMD_COMMON looks good, we just got to get co-operation and assume Silverback wants to have some ownership of amd/stoneyridge.
I am not so happy how amdblock/acpmmio.h and soc/iomap.h play together, and the guards in acpimmio/mmio_util.c. Preferably common code would not include per-platform headerfiles.
As for BIOSRAM, continue with it for APU2 bootblock.
Understood. Will push a fixed patch now, just to make Jenkins happy and let's work on that later on.
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37177 )
Change subject: sb/amd/{agesa,pi}/hudson: enable support for AMD common ACPIMMIO blocks ......................................................................
Patch Set 1:
Patch Set 1:
Patch Set 1:
Patch Set 1:
Patch Set 1:
(4 comments)
We want to coordinate this with AMD/SilverBack/Google such that soc/amd/common and SOC_AMD_COMMON are usable without copy-pasting headers under southbridge/hudson .
Ohh I see. Could let me know first how I should proceed with this. From your other comments I understood to reuse as much as possible form stoney SoC and work on BIOSRAM for binaryPI.
If there is a concept in soc/amd/stoneyridge or soc/amd/common that would work for binaryPI and AGESA we should use it. The approach with SOC_AMD_COMMON looks good, we just got to get co-operation and assume Silverback wants to have some ownership of amd/stoneyridge.
I am not so happy how amdblock/acpmmio.h and soc/iomap.h play together, and the guards in acpimmio/mmio_util.c. Preferably common code would not include per-platform headerfiles.
As for BIOSRAM, continue with it for APU2 bootblock.
Understood. Will push a fixed patch now, just to make Jenkins happy and let's work on that later on.
C_ENV_BB just got merged, wait 15 minutes and we have this rebased.
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37177 )
Change subject: sb/amd/{agesa,pi}/hudson: enable support for AMD common ACPIMMIO blocks ......................................................................
Patch Set 1:
C_ENV_BB just got merged, wait 15 minutes and we have this rebased.
Rebase done. CB:18526 patchset #10
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37177 )
Change subject: sb/amd/{agesa,pi}/hudson: enable support for AMD common ACPIMMIO blocks ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/37177/1/src/mainboard/pcengines/apu... File src/mainboard/pcengines/apu2/mainboard.c:
https://review.coreboot.org/c/coreboot/+/37177/1/src/mainboard/pcengines/apu... PS1, Line 16: #include <amdblocks/acpimmio.h> Why is the header added with no other code? Can the mainboard code be factored out into a separate commit?
Hello Kyösti Mälkki, Piotr Król, Marshall Dawson, Richard Spiegel, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/37177
to look at the new patch set (#2).
Change subject: sb/amd/{agesa,pi}/hudson: enable support for AMD common ACPIMMIO blocks ......................................................................
sb/amd/{agesa,pi}/hudson: enable support for AMD common ACPIMMIO blocks
Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Change-Id: Idd014f1ba85efff0c98a0c5ab60d775ac93cbc60 --- M src/mainboard/pcengines/apu2/mainboard.c M src/southbridge/amd/agesa/hudson/Kconfig M src/southbridge/amd/agesa/hudson/Makefile.inc M src/southbridge/amd/agesa/hudson/hudson.c M src/southbridge/amd/agesa/hudson/hudson.h A src/southbridge/amd/agesa/hudson/include/soc/iomap.h M src/southbridge/amd/agesa/hudson/lpc.c M src/southbridge/amd/agesa/hudson/smbus.c M src/southbridge/amd/agesa/hudson/smbus.h M src/southbridge/amd/agesa/hudson/smi.c M src/southbridge/amd/agesa/hudson/smi.h M src/southbridge/amd/agesa/hudson/smi_util.c M src/southbridge/amd/agesa/hudson/smihandler.c M src/southbridge/amd/pi/hudson/Kconfig M src/southbridge/amd/pi/hudson/Makefile.inc M src/southbridge/amd/pi/hudson/hudson.c M src/southbridge/amd/pi/hudson/hudson.h A src/southbridge/amd/pi/hudson/include/soc/iomap.h M src/southbridge/amd/pi/hudson/lpc.c M src/southbridge/amd/pi/hudson/smbus.c M src/southbridge/amd/pi/hudson/smbus.h M src/southbridge/amd/pi/hudson/smi.c M src/southbridge/amd/pi/hudson/smi.h M src/southbridge/amd/pi/hudson/smi_util.c M src/southbridge/amd/pi/hudson/smihandler.c 25 files changed, 170 insertions(+), 105 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/37177/2
Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37177 )
Change subject: sb/amd/{agesa,pi}/hudson: enable support for AMD common ACPIMMIO blocks ......................................................................
Patch Set 3:
This change is ready for review.
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37177 )
Change subject: sb/amd/{agesa,pi}/hudson: enable support for AMD common ACPIMMIO blocks ......................................................................
Patch Set 3:
(2 comments)
https://review.coreboot.org/c/coreboot/+/37177/3/src/southbridge/amd/agesa/h... File src/southbridge/amd/agesa/hudson/smbus.c:
https://review.coreboot.org/c/coreboot/+/37177/3/src/southbridge/amd/agesa/h... PS3, Line 19: #include <amdblocks/acpimmio.h> not needed?
https://review.coreboot.org/c/coreboot/+/37177/3/src/southbridge/amd/pi/huds... File src/southbridge/amd/pi/hudson/smbus.c:
https://review.coreboot.org/c/coreboot/+/37177/3/src/southbridge/amd/pi/huds... PS3, Line 19: #include <amdblocks/acpimmio.h> Not needed?
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37177 )
Change subject: sb/amd/{agesa,pi}/hudson: enable support for AMD common ACPIMMIO blocks ......................................................................
Patch Set 3:
Once I complete review round, rebase on CB:37210, you can ignore CB:37211 and CB:37324 for now.
Hello Kyösti Mälkki, Piotr Król, Marshall Dawson, Richard Spiegel, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/37177
to look at the new patch set (#4).
Change subject: sb/amd/{agesa,pi}/hudson: enable support for AMD common ACPIMMIO blocks ......................................................................
sb/amd/{agesa,pi}/hudson: enable support for AMD common ACPIMMIO blocks
Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Change-Id: Idd014f1ba85efff0c98a0c5ab60d775ac93cbc60 --- M src/mainboard/pcengines/apu2/mainboard.c M src/southbridge/amd/agesa/hudson/Kconfig M src/southbridge/amd/agesa/hudson/hudson.c M src/southbridge/amd/agesa/hudson/hudson.h M src/southbridge/amd/agesa/hudson/lpc.c M src/southbridge/amd/agesa/hudson/smi.c M src/southbridge/amd/agesa/hudson/smi.h M src/southbridge/amd/agesa/hudson/smi_util.c M src/southbridge/amd/agesa/hudson/smihandler.c M src/southbridge/amd/pi/hudson/Kconfig M src/southbridge/amd/pi/hudson/hudson.c M src/southbridge/amd/pi/hudson/hudson.h M src/southbridge/amd/pi/hudson/lpc.c M src/southbridge/amd/pi/hudson/smi.c M src/southbridge/amd/pi/hudson/smi.h M src/southbridge/amd/pi/hudson/smi_util.c M src/southbridge/amd/pi/hudson/smihandler.c 17 files changed, 21 insertions(+), 99 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/37177/4
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37177 )
Change subject: sb/amd/{agesa,pi}/hudson: enable support for AMD common ACPIMMIO blocks ......................................................................
Patch Set 4:
(7 comments)
https://review.coreboot.org/c/coreboot/+/37177/1/src/mainboard/pcengines/apu... File src/mainboard/pcengines/apu2/mainboard.c:
https://review.coreboot.org/c/coreboot/+/37177/1/src/mainboard/pcengines/apu... PS1, Line 16: #include <amdblocks/acpimmio.h>
Why is the header added with no other code? Can the mainboard code be factored out into a separate c […]
Prototypes from one of the headers below was moved into this file.
https://review.coreboot.org/c/coreboot/+/37177/1/src/southbridge/amd/agesa/h... File src/southbridge/amd/agesa/hudson/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/37177/1/src/southbridge/amd/agesa/h... PS1, Line 4: CPPFLAGS_common += -I$(src)/southbridge/amd/agesa/hudson/include
Lets not introduce include/ there.
Done
https://review.coreboot.org/c/coreboot/+/37177/1/src/southbridge/amd/agesa/h... File src/southbridge/amd/agesa/hudson/include/soc/iomap.h:
https://review.coreboot.org/c/coreboot/+/37177/1/src/southbridge/amd/agesa/h... PS1, Line 5: * Copyright 2017 Google Inc.
I guess this is copy from somewhere?
Done
https://review.coreboot.org/c/coreboot/+/37177/1/src/southbridge/amd/agesa/h... PS1, Line 25: #include <amdblocks/acpimmio_map.h>
Why?
Done
https://review.coreboot.org/c/coreboot/+/37177/3/src/southbridge/amd/agesa/h... File src/southbridge/amd/agesa/hudson/smbus.c:
https://review.coreboot.org/c/coreboot/+/37177/3/src/southbridge/amd/agesa/h... PS3, Line 19: #include <amdblocks/acpimmio.h>
not needed?
Done
https://review.coreboot.org/c/coreboot/+/37177/1/src/southbridge/amd/pi/huds... File src/southbridge/amd/pi/hudson/include/soc/iomap.h:
https://review.coreboot.org/c/coreboot/+/37177/1/src/southbridge/amd/pi/huds... PS1, Line 25: #include <amdblocks/acpimmio_map.h>
Why ?
Done
https://review.coreboot.org/c/coreboot/+/37177/3/src/southbridge/amd/pi/huds... File src/southbridge/amd/pi/hudson/smbus.c:
https://review.coreboot.org/c/coreboot/+/37177/3/src/southbridge/amd/pi/huds... PS3, Line 19: #include <amdblocks/acpimmio.h>
Not needed?
Done
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37177 )
Change subject: sb/amd/{agesa,pi}/hudson: enable support for AMD common ACPIMMIO blocks ......................................................................
Patch Set 4: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/37177 )
Change subject: sb/amd/{agesa,pi}/hudson: enable support for AMD common ACPIMMIO blocks ......................................................................
sb/amd/{agesa,pi}/hudson: enable support for AMD common ACPIMMIO blocks
Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Change-Id: Idd014f1ba85efff0c98a0c5ab60d775ac93cbc60 Reviewed-on: https://review.coreboot.org/c/coreboot/+/37177 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/mainboard/pcengines/apu2/mainboard.c M src/southbridge/amd/agesa/hudson/Kconfig M src/southbridge/amd/agesa/hudson/hudson.c M src/southbridge/amd/agesa/hudson/hudson.h M src/southbridge/amd/agesa/hudson/lpc.c M src/southbridge/amd/agesa/hudson/smi.c M src/southbridge/amd/agesa/hudson/smi.h M src/southbridge/amd/agesa/hudson/smi_util.c M src/southbridge/amd/agesa/hudson/smihandler.c M src/southbridge/amd/pi/hudson/Kconfig M src/southbridge/amd/pi/hudson/hudson.c M src/southbridge/amd/pi/hudson/hudson.h M src/southbridge/amd/pi/hudson/lpc.c M src/southbridge/amd/pi/hudson/smi.c M src/southbridge/amd/pi/hudson/smi.h M src/southbridge/amd/pi/hudson/smi_util.c M src/southbridge/amd/pi/hudson/smihandler.c 17 files changed, 21 insertions(+), 99 deletions(-)
Approvals: build bot (Jenkins): Verified Kyösti Mälkki: Looks good to me, approved
diff --git a/src/mainboard/pcengines/apu2/mainboard.c b/src/mainboard/pcengines/apu2/mainboard.c index 682120b..d46361c 100644 --- a/src/mainboard/pcengines/apu2/mainboard.c +++ b/src/mainboard/pcengines/apu2/mainboard.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */
+#include <amdblocks/acpimmio.h> #include <device/mmio.h> #include <device/pci_ops.h> #include <console/console.h> diff --git a/src/southbridge/amd/agesa/hudson/Kconfig b/src/southbridge/amd/agesa/hudson/Kconfig index 394a196..93db1a9 100644 --- a/src/southbridge/amd/agesa/hudson/Kconfig +++ b/src/southbridge/amd/agesa/hudson/Kconfig @@ -27,6 +27,9 @@ select HAVE_USBDEBUG_OPTIONS select HAVE_CF9_RESET select HAVE_CF9_RESET_PREPARE + select SOC_AMD_COMMON + select SOC_AMD_COMMON_BLOCK + select SOC_AMD_COMMON_BLOCK_ACPIMMIO
config BOOTBLOCK_SOUTHBRIDGE_INIT string diff --git a/src/southbridge/amd/agesa/hudson/hudson.c b/src/southbridge/amd/agesa/hudson/hudson.c index 4c06e87..d586d33 100644 --- a/src/southbridge/amd/agesa/hudson/hudson.c +++ b/src/southbridge/amd/agesa/hudson/hudson.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */
+#include <amdblocks/acpimmio.h> #include <console/console.h> #include <device/mmio.h> #include <device/device.h> @@ -25,31 +26,6 @@ #include "smbus.h" #include "smi.h"
-/* Offsets from ACPI_MMIO_BASE - * This is defined by AGESA, but we don't include AGESA headers to avoid - * polluting the namespace. - */ -#define PM_MMIO_BASE 0xfed80300 - -void pm_write8(u8 reg, u8 value) -{ - write8((void *)((uintptr_t)PM_MMIO_BASE + reg), value); -} - -u8 pm_read8(u8 reg) -{ - return read8((void *)((uintptr_t)PM_MMIO_BASE + reg)); -} - -void pm_write16(u8 reg, u16 value) -{ - write16((void *)((uintptr_t)PM_MMIO_BASE + reg), value); -} - -u16 pm_read16(u16 reg) -{ - return read16((void *)((uintptr_t)PM_MMIO_BASE + reg)); -}
#define PM_REG_USB_ENABLE 0xef
diff --git a/src/southbridge/amd/agesa/hudson/hudson.h b/src/southbridge/amd/agesa/hudson/hudson.h index 21a2129..18303fc 100644 --- a/src/southbridge/amd/agesa/hudson/hudson.h +++ b/src/southbridge/amd/agesa/hudson/hudson.h @@ -61,11 +61,6 @@ return (CONFIG_HUDSON_SATA_MODE == 0) || (CONFIG_HUDSON_SATA_MODE == 3); }
-void pm_write8(u8 reg, u8 value); -u8 pm_read8(u8 reg); -void pm_write16(u8 reg, u16 value); -u16 pm_read16(u16 reg); - void hudson_lpc_port80(void); void hudson_pci_port80(void); void hudson_clk_output_48Mhz(void); diff --git a/src/southbridge/amd/agesa/hudson/lpc.c b/src/southbridge/amd/agesa/hudson/lpc.c index eed1aec..9c65d04 100644 --- a/src/southbridge/amd/agesa/hudson/lpc.c +++ b/src/southbridge/amd/agesa/hudson/lpc.c @@ -14,6 +14,7 @@ * GNU General Public License for more details. */
+#include <amdblocks/acpimmio.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> diff --git a/src/southbridge/amd/agesa/hudson/smi.c b/src/southbridge/amd/agesa/hudson/smi.c index f8196b4..7f76cd5 100644 --- a/src/southbridge/amd/agesa/hudson/smi.c +++ b/src/southbridge/amd/agesa/hudson/smi.c @@ -18,6 +18,7 @@ * Utilities for SMM setup */
+#include <amdblocks/acpimmio.h> #include <console/console.h> #include <cpu/x86/smm.h>
diff --git a/src/southbridge/amd/agesa/hudson/smi.h b/src/southbridge/amd/agesa/hudson/smi.h index 5e0c09a..b1156a8 100644 --- a/src/southbridge/amd/agesa/hudson/smi.h +++ b/src/southbridge/amd/agesa/hudson/smi.h @@ -47,26 +47,6 @@ SMI_LVL_HIGH = 1, };
-static inline uint32_t smi_read32(uint8_t offset) -{ - return read32((void *)((uintptr_t)SMI_BASE + offset)); -} - -static inline void smi_write32(uint8_t offset, uint32_t value) -{ - write32((void *)((uintptr_t)SMI_BASE + offset), value); -} - -static inline uint16_t smi_read16(uint8_t offset) -{ - return read16((void *)((uintptr_t)SMI_BASE + offset)); -} - -static inline void smi_write16(uint8_t offset, uint16_t value) -{ - write16((void *)((uintptr_t)SMI_BASE + offset), value); -} - void hudson_configure_gevent_smi(uint8_t gevent, uint8_t mode, uint8_t level); void hudson_disable_gevent_smi(uint8_t gevent); void hudson_enable_acpi_cmd_smi(void); diff --git a/src/southbridge/amd/agesa/hudson/smi_util.c b/src/southbridge/amd/agesa/hudson/smi_util.c index 63bce7b..8032954 100644 --- a/src/southbridge/amd/agesa/hudson/smi_util.c +++ b/src/southbridge/amd/agesa/hudson/smi_util.c @@ -18,10 +18,11 @@ * SMM utilities used in both SMM and normal mode */
-#include "smi.h" - +#include <amdblocks/acpimmio.h> #include <console/console.h>
+#include "smi.h" + #define HUDSON_SMI_ACPI_COMMAND 75
static void configure_smi(uint8_t smi_num, uint8_t mode) diff --git a/src/southbridge/amd/agesa/hudson/smihandler.c b/src/southbridge/amd/agesa/hudson/smihandler.c index 6ecb746..1b60f18 100644 --- a/src/southbridge/amd/agesa/hudson/smihandler.c +++ b/src/southbridge/amd/agesa/hudson/smihandler.c @@ -18,6 +18,7 @@ * SMI handler for Hudson southbridges */
+#include <amdblocks/acpimmio.h> #include <arch/io.h> #include <cpu/x86/smm.h>
diff --git a/src/southbridge/amd/pi/hudson/Kconfig b/src/southbridge/amd/pi/hudson/Kconfig index c636df8..01f3937 100644 --- a/src/southbridge/amd/pi/hudson/Kconfig +++ b/src/southbridge/amd/pi/hudson/Kconfig @@ -30,6 +30,9 @@ select HAVE_USBDEBUG_OPTIONS select HAVE_CF9_RESET select HAVE_CF9_RESET_PREPARE + select SOC_AMD_COMMON + select SOC_AMD_COMMON_BLOCK + select SOC_AMD_COMMON_BLOCK_ACPIMMIO
config BOOTBLOCK_SOUTHBRIDGE_INIT string diff --git a/src/southbridge/amd/pi/hudson/hudson.c b/src/southbridge/amd/pi/hudson/hudson.c index a331c57..51c37a1 100644 --- a/src/southbridge/amd/pi/hudson/hudson.c +++ b/src/southbridge/amd/pi/hudson/hudson.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */
+#include <amdblocks/acpimmio.h> #include <console/console.h> #include <arch/io.h> #include <device/mmio.h> @@ -36,26 +37,6 @@ return (int)tmp; }
-void pm_write8(u8 reg, u8 value) -{ - write8((void *)(PM_MMIO_BASE + reg), value); -} - -u8 pm_read8(u8 reg) -{ - return read8((void *)(PM_MMIO_BASE + reg)); -} - -void pm_write16(u8 reg, u16 value) -{ - write16((void *)(PM_MMIO_BASE + reg), value); -} - -u16 pm_read16(u16 reg) -{ - return read16((void *)(PM_MMIO_BASE + reg)); -} - void hudson_enable(struct device *dev) { printk(BIOS_DEBUG, "hudson_enable()\n"); diff --git a/src/southbridge/amd/pi/hudson/hudson.h b/src/southbridge/amd/pi/hudson/hudson.h index 9511a6a..b24629f 100644 --- a/src/southbridge/amd/pi/hudson/hudson.h +++ b/src/southbridge/amd/pi/hudson/hudson.h @@ -169,11 +169,6 @@ return (CONFIG_HUDSON_SATA_MODE == 0) || (CONFIG_HUDSON_SATA_MODE == 3); }
-void pm_write8(u8 reg, u8 value); -u8 pm_read8(u8 reg); -void pm_write16(u8 reg, u16 value); -u16 pm_read16(u16 reg); - void hudson_lpc_port80(void); void hudson_lpc_decode(void); void hudson_pci_port80(void); diff --git a/src/southbridge/amd/pi/hudson/lpc.c b/src/southbridge/amd/pi/hudson/lpc.c index e65fd83..6c3561f 100644 --- a/src/southbridge/amd/pi/hudson/lpc.c +++ b/src/southbridge/amd/pi/hudson/lpc.c @@ -14,6 +14,7 @@ * GNU General Public License for more details. */
+#include <amdblocks/acpimmio.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> diff --git a/src/southbridge/amd/pi/hudson/smi.c b/src/southbridge/amd/pi/hudson/smi.c index f8196b4..7f76cd5 100644 --- a/src/southbridge/amd/pi/hudson/smi.c +++ b/src/southbridge/amd/pi/hudson/smi.c @@ -18,6 +18,7 @@ * Utilities for SMM setup */
+#include <amdblocks/acpimmio.h> #include <console/console.h> #include <cpu/x86/smm.h>
diff --git a/src/southbridge/amd/pi/hudson/smi.h b/src/southbridge/amd/pi/hudson/smi.h index 684dca5..4faee15 100644 --- a/src/southbridge/amd/pi/hudson/smi.h +++ b/src/southbridge/amd/pi/hudson/smi.h @@ -47,26 +47,6 @@ SMI_LVL_HIGH = 1, };
-static inline uint32_t smi_read32(uint8_t offset) -{ - return read32((void *)(SMI_BASE + offset)); -} - -static inline void smi_write32(uint8_t offset, uint32_t value) -{ - write32((void *)(SMI_BASE + offset), value); -} - -static inline uint16_t smi_read16(uint8_t offset) -{ - return read16((void *)(SMI_BASE + offset)); -} - -static inline void smi_write16(uint8_t offset, uint16_t value) -{ - write16((void *)(SMI_BASE + offset), value); -} - void hudson_configure_gevent_smi(uint8_t gevent, uint8_t mode, uint8_t level); void hudson_disable_gevent_smi(uint8_t gevent); void hudson_enable_acpi_cmd_smi(void); diff --git a/src/southbridge/amd/pi/hudson/smi_util.c b/src/southbridge/amd/pi/hudson/smi_util.c index 63bce7b..8032954 100644 --- a/src/southbridge/amd/pi/hudson/smi_util.c +++ b/src/southbridge/amd/pi/hudson/smi_util.c @@ -18,10 +18,11 @@ * SMM utilities used in both SMM and normal mode */
-#include "smi.h" - +#include <amdblocks/acpimmio.h> #include <console/console.h>
+#include "smi.h" + #define HUDSON_SMI_ACPI_COMMAND 75
static void configure_smi(uint8_t smi_num, uint8_t mode) diff --git a/src/southbridge/amd/pi/hudson/smihandler.c b/src/southbridge/amd/pi/hudson/smihandler.c index 6ecb746..1b60f18 100644 --- a/src/southbridge/amd/pi/hudson/smihandler.c +++ b/src/southbridge/amd/pi/hudson/smihandler.c @@ -18,6 +18,7 @@ * SMI handler for Hudson southbridges */
+#include <amdblocks/acpimmio.h> #include <arch/io.h> #include <cpu/x86/smm.h>
-
Kyösti Mälkki (Code Review) -
Michał Żygowski (Code Review)
-
Patrick Georgi (Code Review)
-
Paul Menzel (Code Review)