Change in coreboot[master]: soc: common: clock: Add support for common clock driver

[Paul Menzel (Code Review)]

Attention is currently required from: Shelley Chen, Ravi kumar, mturney mturney, Julius Werner.
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56588 )

Change subject: soc: common: clock: Add support for common clock driver
......................................................................

Patch Set 2:

(13 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/56588/comment/8db6fa29_731fe34c 
PS2, Line 7: Add support for common clock driver
> Add common clock driver

https://review.coreboot.org/c/coreboot/+/56588/comment/e4c819be_2d59872e 
PS2, Line 10: root clock generator(RCG)
Please add a space before the (.

https://review.coreboot.org/c/coreboot/+/56588/comment/a3604f2a_29526a2d 
PS2, Line 14: Zonda/Agera
Please clarify what these names mean.

https://review.coreboot.org/c/coreboot/+/56588/comment/165e1520_816045f4 
PS2, Line 19: SC7180 clock driver is also refactored to use the common clock
            : driver APIs.
How did you verify it works the same? (Is there some test or log message?)

https://review.coreboot.org/c/coreboot/+/56588/comment/d4183891_3fbb4997 
PS2, Line 21: 
Please mention the datasheet name and revision.

File src/soc/qualcomm/common/clock.c:

https://review.coreboot.org/c/coreboot/+/56588/comment/fe22492d_515f8d28 
PS2, Line 20: 	/* Set clock vote bit */
The comment is not needed, as the code line is self-explaining.

https://review.coreboot.org/c/coreboot/+/56588/comment/3593a1f9_6bd0b52c 
PS2, Line 25: 		return CB_ERR;
If console works, can an error be logged?

https://review.coreboot.org/c/coreboot/+/56588/comment/9b057d9a_4b98e852 
PS2, Line 84: idx
Can a native type be used?

https://review.coreboot.org/c/coreboot/+/56588/comment/0b7ee097_a826787e 
PS2, Line 100: RCG*/
Missing space.

https://review.coreboot.org/c/coreboot/+/56588/comment/7aef6726_0b0d1ec4 
PS2, Line 111: idx
unsigned int?

https://review.coreboot.org/c/coreboot/+/56588/comment/c89e0ec6_e99882d4 
PS2, Line 183: 		udelay(10);
Why the delay? Please add a comment.

https://review.coreboot.org/c/coreboot/+/56588/comment/f3129d0a_274122e8 
PS2, Line 188: 			printk(BIOS_ERR, "ERROR: PLL did not lock!\n");
Please not the consequence in the message. Is some default clock used? Will the system still work?

https://review.coreboot.org/c/coreboot/+/56588/comment/98b627ab_f252472a 
PS2, Line 199: 	udelay(5);
Why the delay? Please add a comment.