Change in coreboot[master]: riscv: update misaligned memory access exception handling

[build bot (Jenkins) (Code Review)]

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27972 )

Change subject: riscv: update misaligned memory access exception handling
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Patch Set 10:

(1 comment)

https://review.coreboot.org/#/c/27972/10/src/arch/riscv/misaligend.c
File src/arch/riscv/misaligend.c:

https://review.coreboot.org/#/c/27972/10/src/arch/riscv/misaligend.c@251
PS10, Line 251: }
adding a line without newline at end of file