Damien Zammit (damien@zamaudio.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17625
-gerrit
commit f0e87f2ce42cc2dd6ac4ca69d3e148d3dab43ee6 Author: Damien Zammit damien@zamaudio.com Date: Mon Nov 28 00:29:10 2016 +1100
[WIP] amdfam10: Major include ".c" cleanup
Previously, all romstages for this northbridge family would compile via 1 single C file with everything included into the romstage.c file (!)
This patch separates the build into separate .o modules and links them accordingly.
Currently compiles and links KFSN4-DRE mainboard rom
DDR3 has not been fixed yet (ie only DDR2 is done so far).
UNTESTED ON HW.
Change-Id: Id0f9849578fd0f8b1eab83aed910902c27354426 Signed-off-by: Damien Zammit damien@zamaudio.com --- src/cpu/amd/car/disable_cache_as_ram.c | 1 + src/cpu/amd/car/post_cache_as_ram.c | 2 + src/cpu/amd/dualcore/dualcore.c | 1 - src/cpu/amd/family_10h-family_15h/Makefile.inc | 4 + src/cpu/amd/family_10h-family_15h/fidvid.c | 10 +- src/cpu/amd/family_10h-family_15h/init_cpus.c | 38 +-- src/cpu/amd/family_10h-family_15h/init_cpus.h | 85 +++++ .../amd/family_10h-family_15h/model_10xxx_init.c | 15 - src/cpu/amd/quadcore/quadcore.c | 11 +- src/mainboard/asus/kfsn4-dre/romstage.c | 32 +- src/northbridge/amd/amdfam10/Makefile.inc | 92 ++++++ src/northbridge/amd/amdfam10/amdfam10.h | 43 ++- src/northbridge/amd/amdfam10/amdfam10_util.c | 4 +- src/northbridge/amd/amdfam10/debug.c | 63 ++-- src/northbridge/amd/amdfam10/debug.h | 50 +++ src/northbridge/amd/amdfam10/early_ht.c | 6 +- src/northbridge/amd/amdfam10/early_ht.h | 17 + src/northbridge/amd/amdfam10/inline_helper.c | 16 + src/northbridge/amd/amdfam10/link_control.c | 15 - src/northbridge/amd/amdfam10/northbridge.c | 15 - src/northbridge/amd/amdfam10/pci.c | 13 +- src/northbridge/amd/amdfam10/pci.h | 26 ++ src/northbridge/amd/amdfam10/raminit.h | 29 +- src/northbridge/amd/amdfam10/raminit_amdmct.c | 144 +------- .../amd/amdfam10/raminit_sysinfo_in_ram.c | 13 +- src/northbridge/amd/amdfam10/reset_test.c | 11 +- src/northbridge/amd/amdfam10/setup_resource_map.c | 10 +- src/northbridge/amd/amdht/comlib.h | 12 +- src/northbridge/amd/amdht/h3ffeat.h | 2 + src/northbridge/amd/amdht/h3finit.c | 11 - src/northbridge/amd/amdht/h3finit.h | 2 + src/northbridge/amd/amdht/h3ncmn.c | 19 +- src/northbridge/amd/amdht/h3ncmn.h | 30 +- src/northbridge/amd/amdht/ht_wrapper.c | 44 +-- src/northbridge/amd/amdht/ht_wrapper.h | 6 + src/northbridge/amd/amdmct/mct/mct_d.c | 23 +- src/northbridge/amd/amdmct/mct/mct_d.h | 47 ++- src/northbridge/amd/amdmct/mct/mct_d_gcc.c | 351 ++++++++++++++++++++ src/northbridge/amd/amdmct/mct/mct_d_gcc.h | 366 ++------------------- src/northbridge/amd/amdmct/mct/mctardk3.c | 2 + src/northbridge/amd/amdmct/mct/mctchi_d.c | 2 +- src/northbridge/amd/amdmct/mct/mctcsi_d.c | 1 + src/northbridge/amd/amdmct/mct/mctdqs_d.c | 24 +- src/northbridge/amd/amdmct/mct/mcthdi.c | 1 + src/northbridge/amd/amdmct/mct/mctndi_d.c | 2 +- src/northbridge/amd/amdmct/mct/mctpro_d.c | 15 +- src/northbridge/amd/amdmct/mct/mctsrc.c | 8 +- src/northbridge/amd/amdmct/mct/mctsrc1p.c | 1 + src/northbridge/amd/amdmct/mct/mcttmrl.c | 1 + src/northbridge/amd/amdmct/wrappers/mcti.h | 76 ++++- src/northbridge/amd/amdmct/wrappers/mcti_d.c | 77 ++--- 51 files changed, 1065 insertions(+), 824 deletions(-)
diff --git a/src/cpu/amd/car/disable_cache_as_ram.c b/src/cpu/amd/car/disable_cache_as_ram.c index 1eb3dd7..bab464e 100644 --- a/src/cpu/amd/car/disable_cache_as_ram.c +++ b/src/cpu/amd/car/disable_cache_as_ram.c @@ -19,6 +19,7 @@ */
#include <cpu/x86/cache.h> +#include <cpu/x86/msr.h>
static inline __attribute__((always_inline)) uint32_t amd_fam1x_cpu_family(void) { diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c index 296adc9..257d486 100644 --- a/src/cpu/amd/car/post_cache_as_ram.c +++ b/src/cpu/amd/car/post_cache_as_ram.c @@ -17,11 +17,13 @@ * GNU General Public License for more details. */ #include <string.h> +#include <console/console.h> #include <arch/stages.h> #include <arch/early_variables.h> #include <cpu/x86/mtrr.h> #include <cpu/amd/mtrr.h> #include <cpu/amd/car.h> +#include <cpu/amd/msr.h> #include <arch/acpi.h> #include <romstage_handoff.h> #include "cbmem.h" diff --git a/src/cpu/amd/dualcore/dualcore.c b/src/cpu/amd/dualcore/dualcore.c index 79e9162..b53a6c4 100644 --- a/src/cpu/amd/dualcore/dualcore.c +++ b/src/cpu/amd/dualcore/dualcore.c @@ -60,5 +60,4 @@ static inline void start_other_cores(void) real_start_other_core(nodeid); } } - } diff --git a/src/cpu/amd/family_10h-family_15h/Makefile.inc b/src/cpu/amd/family_10h-family_15h/Makefile.inc index f10f732..75a1232 100644 --- a/src/cpu/amd/family_10h-family_15h/Makefile.inc +++ b/src/cpu/amd/family_10h-family_15h/Makefile.inc @@ -1,4 +1,8 @@ romstage-y += ../../x86/mtrr/earlymtrr.c + +##### +romstage-y += init_cpus.c + ramstage-y += model_10xxx_init.c ramstage-y += processor_name.c
diff --git a/src/cpu/amd/family_10h-family_15h/fidvid.c b/src/cpu/amd/family_10h-family_15h/fidvid.c index 0e51a0c..8fe708c 100644 --- a/src/cpu/amd/family_10h-family_15h/fidvid.c +++ b/src/cpu/amd/family_10h-family_15h/fidvid.c @@ -89,8 +89,7 @@ b.- prep_fid_change(...)
*/
-#if CONFIG_SET_FIDVID - +#include <inttypes.h> #include <northbridge/amd/amdht/AsPsDefs.h>
static inline void print_debug_fv(const char *str, u32 val) @@ -601,7 +600,7 @@ static void config_acpi_pwr_state_ctrl_regs(pci_devfn_t dev, uint64_t cpuRev, } }
-static void prep_fid_change(void) +void prep_fid_change(void) { u32 dword; u32 nodes; @@ -981,7 +980,7 @@ static void finalPstateChange(void) set_pstate(0); }
-static void init_fidvid_stage2(u32 apicid, u32 nodeid) +void init_fidvid_stage2(u32 apicid, u32 nodeid) { msr_t msr; pci_devfn_t dev; @@ -1052,7 +1051,7 @@ static void store_ap_apicid(unsigned ap_apicid, void *gp) #endif
-static int init_fidvid_bsp(u32 bsp_apicid, u32 nodes) +int init_fidvid_bsp(u32 bsp_apicid, u32 nodes) { #if CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST struct ap_apicid_st ap_apicidx; @@ -1098,4 +1097,3 @@ static int init_fidvid_bsp(u32 bsp_apicid, u32 nodes)
return 0; // No FID/VID changes. Don't reset } -#endif diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c index 3c13e36..7e3a3b2 100644 --- a/src/cpu/amd/family_10h-family_15h/init_cpus.c +++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c @@ -14,32 +14,8 @@ * GNU General Public License for more details. */
+#include "init_cpus.h" #include "cpu/amd/car/post_cache_as_ram.c" -#include "defaults.h" -#include <stdlib.h> -#include <cpu/x86/lapic.h> -#include <cpu/x86/mtrr.h> -#include <northbridge/amd/amdfam10/amdfam10.h> -#include <northbridge/amd/amdht/AsPsDefs.h> -#include <northbridge/amd/amdht/porting.h> - -#include <northbridge/amd/amdfam10/raminit_amdmct.c> -#include <reset.h> - -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SB700) -#include <southbridge/amd/sb700/sb700.h> -#endif - -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SB800) -#include <southbridge/amd/sb800/sb800.h> -#endif - -#if IS_ENABLED(CONFIG_SET_FIDVID) -static void prep_fid_change(void); -static void init_fidvid_stage2(u32 apicid, u32 nodeid); -#endif - -void cpuSetAMDMSR(uint8_t node_id);
#if CONFIG_PCI_IO_CFG_EXT static void set_EnableCf8ExtCfg(void) @@ -58,8 +34,6 @@ static void set_EnableCf8ExtCfg(void) { } // #define DEBUG_HT_SETUP 1 // #define FAM10_AP_NODE_SEQUENTIAL_START 1
-typedef void (*process_ap_t) (u32 apicid, void *gp); - uint32_t get_boot_apic_id(uint8_t node, uint32_t core) { uint32_t ap_apicid;
@@ -369,7 +343,7 @@ static void STOP_CAR_AND_CPU(uint8_t skip_sharedc_config, uint32_t apicid) stop_this_cpu(); }
-static u32 init_cpus(u32 cpu_init_detectedx, struct sys_info *sysinfo) +u32 init_cpus(u32 cpu_init_detectedx, struct sys_info *sysinfo) { uint32_t bsp_apicid = 0; uint32_t apicid; @@ -637,7 +611,7 @@ static void setup_remote_node(u8 node) #endif /* CONFIG_MAX_PHYSICAL_CPUS > 1 */
//it is running on core0 of node0 -static void start_other_cores(uint32_t bsp_apicid) +void start_other_cores(uint32_t bsp_apicid) { u32 nodes; u32 nodeid; @@ -1855,7 +1829,7 @@ static void cpuInitializeMCA(void) * Do any additional post HT init * */ -static void finalize_node_setup(struct sys_info *sysinfo) +void finalize_node_setup(struct sys_info *sysinfo) { u8 i; u8 nodes = get_nodes(); @@ -1886,4 +1860,6 @@ static void finalize_node_setup(struct sys_info *sysinfo) #endif }
-#include "fidvid.c" +#if CONFIG_SET_FIDVID +# include "fidvid.c" +#endif diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.h b/src/cpu/amd/family_10h-family_15h/init_cpus.h new file mode 100644 index 0000000..5905f95 --- /dev/null +++ b/src/cpu/amd/family_10h-family_15h/init_cpus.h @@ -0,0 +1,85 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Damien Zammit damien@zamaudio.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef INIT_CPUS_H +#define INIT_CPUS_H + +#include <stdlib.h> +#include <console/console.h> +#include <arch/cpu.h> +#include <cpu/x86/lapic.h> +#include <cpu/x86/mtrr.h> +#include <cpu/amd/msr.h> +#include <cpu/amd/multicore.h> + +#if CONFIG_HAVE_OPTION_TABLE +#include "option_table.h" +#endif +#include <pc80/mc146818rtc.h> + +#include <northbridge/amd/amdfam10/raminit.h> +#include <northbridge/amd/amdht/ht_wrapper.h> +#include <northbridge/amd/amdht/AsPsDefs.h> +#include <northbridge/amd/amdht/porting.h> +#include <northbridge/amd/amdht/h3ncmn.h> +#include <reset.h> +#include "defaults.h" + +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SB700) +#include <southbridge/amd/sb700/sb700.h> +#endif + +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SB800) +#include <southbridge/amd/sb800/sb800.h> +#endif + +/* +#if IS_ENABLED(CONFIG_SET_FIDVID) +static void prep_fid_change(void); +static void init_fidvid_stage2(u32 apicid, u32 nodeid); +#endif +*/ + +#define NODE_HT(x) NODE_PCI(x,0) +#define NODE_MP(x) NODE_PCI(x,1) +#define NODE_MC(x) NODE_PCI(x,3) +#define NODE_LC(x) NODE_PCI(x,4) + +void cpuSetAMDMSR(uint8_t node_id); + +// #define DEBUG_HT_SETUP 1 +// #define FAM10_AP_NODE_SEQUENTIAL_START 1 + +typedef void (*process_ap_t) (u32 apicid, void *gp); + +uint32_t get_boot_apic_id(uint8_t node, uint32_t core); +u32 init_cpus(u32 cpu_init_detectedx, struct sys_info *sysinfo); +inline uint8_t set_apicid_cpuid_lo(void); +void real_start_other_core(uint32_t nodeid, uint32_t cores); +void finalize_node_setup(struct sys_info *sysinfo); +uint32_t wait_cpu_state(uint32_t apicid, uint32_t state, uint32_t state2); +void start_other_cores(uint32_t bsp_apicid); +u32 get_core_num_in_bsp(u32 nodeid); + +void update_microcode(u32 cpu_deviceid); + +/* fidvid.c */ +void init_fidvid_stage2(u32 apicid, u32 nodeid); +void prep_fid_change(void); +int init_fidvid_bsp(u32 bsp_apicid, u32 nodes); + +/* defined in romstage.c */ +unsigned int get_sbdn(unsigned bus); +#endif diff --git a/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c b/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c index f8e6a27..b002b62 100644 --- a/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c +++ b/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c @@ -35,21 +35,6 @@
#define MCI_STATUS 0x401
-static inline uint8_t is_fam15h(void) -{ - uint8_t fam15h = 0; - uint32_t family; - - family = cpuid_eax(0x80000001); - family = ((family & 0xf00000) >> 16) | ((family & 0xf00) >> 8); - - if (family >= 0x6f) - /* Family 15h or later */ - fam15h = 1; - - return fam15h; -} - static inline uint8_t is_gt_rev_d(void) { uint8_t fam15h = 0; diff --git a/src/cpu/amd/quadcore/quadcore.c b/src/cpu/amd/quadcore/quadcore.c index 3ca7f3e..2f0822e 100644 --- a/src/cpu/amd/quadcore/quadcore.c +++ b/src/cpu/amd/quadcore/quadcore.c @@ -16,18 +16,13 @@
#include <console/console.h> #include <pc80/mc146818rtc.h> -#include <northbridge/amd/amdht/ht_wrapper.c> #if CONFIG_HAVE_OPTION_TABLE #include "option_table.h" #endif
#include "cpu/amd/quadcore/quadcore_id.c"
-/* get_boot_apic_id and wait_cpu_state located in init_cpus.c */ -uint32_t get_boot_apic_id(uint8_t node, uint32_t core); -uint32_t wait_cpu_state(uint32_t apicid, uint32_t state, uint32_t state2); - -static u32 get_core_num_in_bsp(u32 nodeid) +u32 get_core_num_in_bsp(u32 nodeid) { u32 dword; if (is_fam15h()) { @@ -46,7 +41,7 @@ static u32 get_core_num_in_bsp(u32 nodeid) return dword; }
-static u8 set_apicid_cpuid_lo(void) +u8 set_apicid_cpuid_lo(void) { // set the NB_CFG[54]=1; why the OS will be happy with that ??? msr_t msr; @@ -57,7 +52,7 @@ static u8 set_apicid_cpuid_lo(void) return 1; }
-static void real_start_other_core(uint32_t nodeid, uint32_t cores) +void real_start_other_core(uint32_t nodeid, uint32_t cores) { ssize_t i; uint32_t dword; diff --git a/src/mainboard/asus/kfsn4-dre/romstage.c b/src/mainboard/asus/kfsn4-dre/romstage.c index c7fa429..c3c56c2 100644 --- a/src/mainboard/asus/kfsn4-dre/romstage.c +++ b/src/mainboard/asus/kfsn4-dre/romstage.c @@ -20,8 +20,6 @@ #define FAM10_SCAN_PCI_BUS 0 #define FAM10_ALLOCATE_IO_RANGE 1
-unsigned int get_sbdn(unsigned bus); - #include <stdint.h> #include <string.h> #include <reset.h> @@ -34,32 +32,34 @@ unsigned int get_sbdn(unsigned bus); #include <timestamp.h> #include <lib.h> #include <spd.h> +#include <cbmem.h> #include <cpu/amd/model_10xxx_rev.h> +#include <cpu/amd/car.h> #include "southbridge/nvidia/ck804/early_smbus.h" -#include <northbridge/amd/amdfam10/raminit.h> -#include <northbridge/amd/amdfam10/amdfam10.h> #include <delay.h> #include <cpu/x86/lapic.h> -#include "northbridge/amd/amdfam10/reset_test.c" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627thg/w83627thg.h> #include <cpu/x86/bist.h> -// #include "northbridge/amd/amdk8/incoherent_ht.c" -#include "northbridge/amd/amdfam10/debug.c" -#include "northbridge/amd/amdfam10/setup_resource_map.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1)
-static void activate_spd_rom(const struct mem_controller *ctrl); +/* Global allocation of sysinfo_car */ +#include <arch/early_variables.h> +struct sys_info sysinfo_car CAR_GLOBAL; + +/* Forward declaration for activate_spd_rom */ +struct mem_controller; +void activate_spd_rom(const struct mem_controller *ctrl);
-static inline int spd_read_byte(unsigned device, unsigned address) +inline int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); }
-#include <northbridge/amd/amdfam10/amdfam10.h> -#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" -#include "northbridge/amd/amdfam10/pci.c" +#include <northbridge/amd/amdfam10/raminit.h> +#include <cpu/amd/family_10h-family_15h/init_cpus.h> + #include "resourcemap.c" #include "cpu/amd/quadcore/quadcore.c"
@@ -68,10 +68,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include <southbridge/nvidia/ck804/early_setup_ss.h> #include "southbridge/nvidia/ck804/early_setup_car.c" -#include <cpu/amd/microcode.h> - -#include "cpu/amd/family_10h-family_15h/init_cpus.c" -#include "northbridge/amd/amdfam10/early_ht.c"
#define GPIO3_DEV PNP_DEV(0x2e, W83627THG_GPIO3)
@@ -182,7 +178,7 @@ static const uint8_t spd_addr[] = { RC01, DIMM0, DIMM2, DIMM4, DIMM6, DIMM1, DIMM3, DIMM5, DIMM7, };
-static void activate_spd_rom(const struct mem_controller *ctrl) { +void activate_spd_rom(const struct mem_controller *ctrl) { printk(BIOS_DEBUG, "activate_spd_rom() for node %02x\n", ctrl->node_id); if (ctrl->node_id == 0) { printk(BIOS_DEBUG, "enable_spd_node0()\n"); diff --git a/src/northbridge/amd/amdfam10/Makefile.inc b/src/northbridge/amd/amdfam10/Makefile.inc index c2b015b..96348a6 100644 --- a/src/northbridge/amd/amdfam10/Makefile.inc +++ b/src/northbridge/amd/amdfam10/Makefile.inc @@ -1,5 +1,97 @@ ifeq ($(CONFIG_NORTHBRIDGE_AMD_AMDFAM10),y)
+romstage-y += ../amdht/h3finit.c +romstage-y += ../amdht/ht_wrapper.c +romstage-y += ../amdht/comlib.c +romstage-y += ../amdht/AsPsNb.c +romstage-y += ../amdht/h3ncmn.c + +IS_DDR3=$(shell test "x$(( $(CONFIG_DIMM_SUPPORT) & 15 ))" = "x5"; echo "$?") + +ifeq ($(IS_DDR3), 0) +# DDR3 +romstage-$(CONFIG_HAVE_ACPI_RESUME) += ../amdmct/mct_ddr3/s3utils.c +romstage-y += ../amdmct/wrappers/mcti_d.c +romstage-y += ../amdmct/mct_ddr3/mct_d.c +romstage-y += ../amdmct/mct_ddr3/mctmtr_d.c +romstage-y += ../amdmct/mct_ddr3/mctcsi_d.c +romstage-y += ../amdmct/mct_ddr3/mctecc_d.c +romstage-y += ../amdmct/mct_ddr3/mctdqs_d.c +romstage-y += ../amdmct/mct_ddr3/mctsrc.c +romstage-y += ../amdmct/mct_ddr3/mctsdi.c +romstage-y += ../amdmct/mct_ddr3/mctprod.c +romstage-y += ../amdmct/mct_ddr3/mctproc.c +romstage-y += ../amdmct/mct_ddr3/mctprob.c +romstage-y += ../amdmct/mct_ddr3/mcthwl.c +romstage-y += ../amdmct/mct_ddr3/mctwl.c +romstage-y += ../amdmct/mct_ddr3/mport_d.c +romstage-y += ../amdmct/mct_ddr3/mutilc_d.c +romstage-y += ../amdmct/mct_ddr3/modtrdim.c +romstage-y += ../amdmct/mct_ddr3/mhwlc_d.c +romstage-y += ../amdmct/mct_ddr3/mctrci.c +romstage-y += ../amdmct/mct_ddr3/mctsrc1p.c +romstage-y += ../amdmct/mct_ddr3/mcttmrl.c +romstage-y += ../amdmct/mct_ddr3/mcthdi.c +romstage-y += ../amdmct/mct_ddr3/mctndi_d.c +romstage-y += ../amdmct/mct_ddr3/mctchi_d.c +romstage-y += ../amdmct/mct_ddr3/modtrd.c + +ifeq ($(CONFIG_CPU_SOCKET_TYPE), 0x11) +romstage-y += ../amdmct/mct_ddr3/mctardk5.c +endif +ifeq ($(CONFIG_CPU_SOCKET_TYPE), 0x13) +romstage-y += ../amdmct/mct_ddr3/mctardk5.c +endif +ifeq ($(CONFIG_CPU_SOCKET_TYPE), 0x14) +romstage-y += ../amdmct/mct_ddr3/mctardk5.c +endif +ifeq ($(CONFIG_CPU_SOCKET_TYPE), 0x15) +romstage-y += ../amdmct/mct_ddr3/mctardk5.c +endif +ifeq ($(CONFIG_CPU_SOCKET_TYPE), 0x16) +romstage-y += ../amdmct/mct_ddr3/mctardk5.c +endif +ifeq ($(CONFIG_CPU_SOCKET_TYPE), 0x12) +romstage-y += ../amdmct/mct_ddr3/mctardk6.c +endif + +else +# DDR2 +romstage-y += ../amdmct/wrappers/mcti_d.c +romstage-y += ../amdmct/mct/mct_d.c +romstage-y += ../amdmct/mct/mct_d_gcc.c +romstage-y += ../amdmct/mct/mctcsi_d.c +romstage-y += ../amdmct/mct/mctmtr_d.c +romstage-y += ../amdmct/mct/mctecc_d.c +romstage-y += ../amdmct/mct/mctpro_d.c +romstage-y += ../amdmct/mct/mctdqs_d.c +romstage-y += ../amdmct/mct/mctsrc.c +romstage-y += ../amdmct/mct/mctsrc1p.c +romstage-y += ../amdmct/mct/mcttmrl.c +romstage-y += ../amdmct/mct/mcthdi.c +romstage-y += ../amdmct/mct/mctndi_d.c +romstage-y += ../amdmct/mct/mctchi_d.c + +ifeq ($(CONFIG_CPU_SOCKET_TYPE), 0x10) +romstage-y += ../amdmct/mct/mctardk3.c +endif + +ifeq ($(CONFIG_CPU_SOCKET_TYPE), 0x11) +romstage-y += ../amdmct/mct/mctardk4.c +endif + +# Generic ROMSTAGE stuff +romstage-y += reset_test.c +romstage-y += debug.c +romstage-y += setup_resource_map.c +romstage-y += raminit_sysinfo_in_ram.c +romstage-y += raminit_amdmct.c +romstage-y += pci.c +romstage-y += early_ht.c + +endif + +# RAMSTAGE ramstage-y += northbridge.c ramstage-y += misc_control.c ramstage-y += link_control.c diff --git a/src/northbridge/amd/amdfam10/amdfam10.h b/src/northbridge/amd/amdfam10/amdfam10.h index 7ba91d7..611291a 100644 --- a/src/northbridge/amd/amdfam10/amdfam10.h +++ b/src/northbridge/amd/amdfam10/amdfam10.h @@ -15,8 +15,28 @@ */
#ifndef AMDFAM10_H - #define AMDFAM10_H + +#include <inttypes.h> +#include <arch/io.h> +#include <device/device.h> +#include "early_ht.h" + +#include "inline_helper.c" +struct DCTStatStruc; +struct MCTStatStruc; + +#define RES_PCI_IO 0x10 +#define RES_PORT_IO_8 0x22 +#define RES_PORT_IO_32 0x20 +#define RES_MEM_IO 0x40 + +#define NODE_ID 0x60 +#define HT_INIT_CONTROL 0x6c +#define HTIC_ColdR_Detect (1<<4) +#define HTIC_BIOSR_Detect (1<<5) +#define HTIC_INIT_Detect (1<<6) + /* Definitions of various FAM10 registers */ /* Function 0 */ #define HT_TRANSACTION_CONTROL 0x68 @@ -900,14 +920,8 @@ that are corresponding to 0x01, 0x02, 0x03, 0x05, 0x06, 0x07 #endif #endif
-#include "raminit.h" - -#include "../amdmct/wrappers/mcti.h" -#if (CONFIG_DIMM_SUPPORT & 0x000F) == 0x0005 /* AMD_FAM10_DDR3 */ - #include "../amdmct/mct_ddr3/mct_d.h" -#else - #include "../amdmct/mct/mct_d.h" -#endif +/* Include wrapper for MCT (works for DDR2 or DDR3) */ +#include <northbridge/amd/amdmct/wrappers/mcti.h>
struct link_pair_t { pci_devfn_t udev; @@ -965,10 +979,12 @@ struct sys_info { struct DCTStatStruc DCTstatA[NODE_NUMS]; } __attribute__((packed));
+ +/* #ifdef __PRE_RAM__ extern struct sys_info sysinfo_car; #endif - +*/ #ifndef __PRE_RAM__ device_t get_node_pci(u32 nodeid, u32 fn); #endif @@ -983,14 +999,19 @@ void setup_resource_map_x_offset(const u32 *register_values, u32 max, u32 offset_pci_dev, u32 offset_io_base);
void setup_resource_map_x(const u32 *register_values, u32 max); +void setup_resource_map(const u32 *register_values, u32 max);
/* reset_test.c */ u32 cpu_init_detected(u8 nodeid); u32 bios_reset_detected(void); u32 cold_reset_detected(void); u32 other_reset_detected(void); +u32 warm_reset_detect(u8 nodeid); +void distinguish_cpu_resets(u8 nodeid); u32 get_sblk(void); u8 get_sbbusn(u8 sblk); +void set_bios_reset(void); + #endif
#include "northbridge/amd/amdht/porting.h" @@ -1005,4 +1026,6 @@ unsigned long northbridge_write_acpi_tables(device_t device, void northbridge_acpi_write_vars(device_t device); #endif
+void set_sysinfo_in_ram(u32 val); + #endif /* AMDFAM10_H */ diff --git a/src/northbridge/amd/amdfam10/amdfam10_util.c b/src/northbridge/amd/amdfam10/amdfam10_util.c index c9b30f8..e0195c6 100644 --- a/src/northbridge/amd/amdfam10/amdfam10_util.c +++ b/src/northbridge/amd/amdfam10/amdfam10_util.c @@ -17,8 +17,8 @@ #include <console/console.h>
#include <arch/cpu.h> -#include <northbridge/amd/amdmct/wrappers/mcti.h> -#include <northbridge/amd/amdmct/mct/mct_d.h> +#include <arch/io.h> +#include "raminit.h" #include <northbridge/amd/amdmct/amddefs.h>
#ifndef __PRE_RAM__ diff --git a/src/northbridge/amd/amdfam10/debug.c b/src/northbridge/amd/amdfam10/debug.c index f9c7266..e9a433d 100644 --- a/src/northbridge/amd/amdfam10/debug.c +++ b/src/northbridge/amd/amdfam10/debug.c @@ -13,26 +13,21 @@ * GNU General Public License for more details. */
-/* - * Generic FAM10 debug code, used by mainboard specific romstage.c - */ - -#include "pci.c" -#include <delay.h> +#include "debug.h"
-static inline void print_debug_addr(const char *str, void *val) +inline void print_debug_addr(const char *str, void *val) { #if CONFIG_DEBUG_CAR printk(BIOS_DEBUG, "------Address debug: %s%p------\n", str, val); #endif }
-static void print_debug_pci_dev(u32 dev) +void print_debug_pci_dev(u32 dev) { printk(BIOS_DEBUG, "PCI: %02x:%02x.%02x", (dev>>20) & 0xff, (dev>>15) & 0x1f, (dev>>12) & 0x7); }
-static inline void print_pci_devices(void) +inline void print_pci_devices(void) { pci_devfn_t dev; for (dev = PCI_DEV(0, 0, 0); @@ -57,7 +52,7 @@ static inline void print_pci_devices(void) } }
-static inline void print_pci_devices_on_bus(u32 busn) +inline void print_pci_devices_on_bus(u32 busn) { pci_devfn_t dev; for (dev = PCI_DEV(busn, 0, 0); @@ -82,7 +77,7 @@ static inline void print_pci_devices_on_bus(u32 busn) } }
-static void dump_pci_device_range(u32 dev, u32 start_reg, u32 size) +void dump_pci_device_range(u32 dev, u32 start_reg, u32 size) { int i; print_debug_pci_dev(dev); @@ -103,12 +98,12 @@ static void dump_pci_device_range(u32 dev, u32 start_reg, u32 size) printk(BIOS_DEBUG, "\n"); }
-static void dump_pci_device(u32 dev) +void dump_pci_device(u32 dev) { dump_pci_device_range(dev, 0, 4096); }
-static void dump_pci_device_index_wait_range(u32 dev, u32 index_reg, u32 start, +void dump_pci_device_index_wait_range(u32 dev, u32 index_reg, u32 start, u32 size) { int i; @@ -130,13 +125,13 @@ static void dump_pci_device_index_wait_range(u32 dev, u32 index_reg, u32 start, printk(BIOS_DEBUG, "\n"); }
-static inline void dump_pci_device_index_wait(u32 dev, u32 index_reg) +inline void dump_pci_device_index_wait(u32 dev, u32 index_reg) { dump_pci_device_index_wait_range(dev, index_reg, 0, 0x54); dump_pci_device_index_wait_range(dev, index_reg, 0x100, 0x08); //DIMM1 when memclk > 400Hz }
-static inline void dump_pci_device_index(u32 dev, u32 index_reg, u32 type, u32 length) +inline void dump_pci_device_index(u32 dev, u32 index_reg, u32 type, u32 length) { int i; print_debug_pci_dev(dev); @@ -156,7 +151,7 @@ static inline void dump_pci_device_index(u32 dev, u32 index_reg, u32 type, u32 l printk(BIOS_DEBUG, "\n"); }
-static inline void dump_pci_devices(void) +inline void dump_pci_devices(void) { pci_devfn_t dev; for (dev = PCI_DEV(0, 0, 0); @@ -181,7 +176,7 @@ static inline void dump_pci_devices(void) } }
-static inline void dump_pci_devices_on_bus(u32 busn) +inline void dump_pci_devices_on_bus(u32 busn) { pci_devfn_t dev; for (dev = PCI_DEV(busn, 0, 0); @@ -207,8 +202,7 @@ static inline void dump_pci_devices_on_bus(u32 busn) }
#if CONFIG_DEBUG_SMBUS - -static void dump_spd_registers(const struct mem_controller *ctrl) +void dump_spd_registers(const struct mem_controller *ctrl) { int i; printk(BIOS_DEBUG, "\n"); @@ -254,7 +248,8 @@ static void dump_spd_registers(const struct mem_controller *ctrl) } } } -static void dump_smbus_registers(void) + +void dump_smbus_registers(void) { u32 device; printk(BIOS_DEBUG, "\n"); @@ -279,7 +274,8 @@ static void dump_smbus_registers(void) } } #endif -static inline void dump_io_resources(u32 port) + +inline void dump_io_resources(u32 port) {
int i; @@ -299,7 +295,7 @@ static inline void dump_io_resources(u32 port) } }
-static inline void dump_mem(u32 start, u32 end) +inline void dump_mem(u32 start, u32 end) { u32 i; printk(BIOS_DEBUG, "dump_mem:"); @@ -311,3 +307,26 @@ static inline void dump_mem(u32 start, u32 end) } printk(BIOS_DEBUG, "\n"); } + +#if (CONFIG_DIMM_SUPPORT & 0x000F)!=0x0005 /* not needed for AMD_FAM10_DDR3 */ +void print_tx(const char *strval, u32 val) +{ +#if CONFIG_DEBUG_RAM_SETUP + printk(BIOS_DEBUG, "%s%08x\n", strval, val); +#endif +} + +void print_t(const char *strval) +{ +#if CONFIG_DEBUG_RAM_SETUP + printk(BIOS_DEBUG, "%s", strval); +#endif +} +#endif + +void print_tf(const char *func, const char *strval) +{ +#if CONFIG_DEBUG_RAM_SETUP + printk(BIOS_DEBUG, "%s: %s", func, strval); +#endif +} diff --git a/src/northbridge/amd/amdfam10/debug.h b/src/northbridge/amd/amdfam10/debug.h new file mode 100644 index 0000000..1e0c941 --- /dev/null +++ b/src/northbridge/amd/amdfam10/debug.h @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Damien Zammit damien@zamaudio.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef AMDFAM10_DEBUG_H +#define AMDFAM10_DEBUG_H + +#include <inttypes.h> +#include <console/console.h> +#include <arch/io.h> +#include <device/pci_def.h> +#include <delay.h> +#include "pci.h" + +inline void print_debug_addr(const char *str, void *val); +void print_debug_pci_dev(u32 dev); +inline void print_pci_devices(void); +inline void print_pci_devices_on_bus(u32 busn); +void dump_pci_device_range(u32 dev, u32 start_reg, u32 size); +void dump_pci_device(u32 dev); +void dump_pci_device_index_wait_range(u32 dev, u32 index_reg, u32 start, + u32 size); +inline void dump_pci_device_index_wait(u32 dev, u32 index_reg); +inline void dump_pci_device_index(u32 dev, u32 index_reg, u32 type, u32 length); +inline void dump_pci_devices(void); +inline void dump_pci_devices_on_bus(u32 busn); + +#if CONFIG_DEBUG_SMBUS +void dump_spd_registers(const struct mem_controller *ctrl); +void dump_smbus_registers(void); +#endif + +inline void dump_io_resources(u32 port); +inline void dump_mem(u32 start, u32 end); + +void print_tx(const char *strval, u32 val); +void print_t(const char *strval); +void print_tf(const char *func, const char *strval); +#endif diff --git a/src/northbridge/amd/amdfam10/early_ht.c b/src/northbridge/amd/amdfam10/early_ht.c index 3681463..1dbe732 100644 --- a/src/northbridge/amd/amdfam10/early_ht.c +++ b/src/northbridge/amd/amdfam10/early_ht.c @@ -13,9 +13,11 @@ * GNU General Public License for more details. */
+#include "early_ht.h" + // For SB HT chain only // mmconf is not ready yet -static void set_bsp_node_CHtExtNodeCfgEn(void) +void set_bsp_node_CHtExtNodeCfgEn(void) { #if CONFIG_EXT_RT_TBL_SUPPORT u32 dword; @@ -34,7 +36,7 @@ static void set_bsp_node_CHtExtNodeCfgEn(void) #endif }
-static void enumerate_ht_chain(void) +void enumerate_ht_chain(void) { #if CONFIG_HT_CHAIN_UNITID_BASE != 0 /* CONFIG_HT_CHAIN_UNITID_BASE could be 0 (only one ht device in the ht chain), diff --git a/src/northbridge/amd/amdfam10/early_ht.h b/src/northbridge/amd/amdfam10/early_ht.h new file mode 100644 index 0000000..0fe5990 --- /dev/null +++ b/src/northbridge/amd/amdfam10/early_ht.h @@ -0,0 +1,17 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Damien Zammit damien@zamaudio.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +void set_bsp_node_CHtExtNodeCfgEn(void); +void enumerate_ht_chain(void); diff --git a/src/northbridge/amd/amdfam10/inline_helper.c b/src/northbridge/amd/amdfam10/inline_helper.c new file mode 100644 index 0000000..116b2a4 --- /dev/null +++ b/src/northbridge/amd/amdfam10/inline_helper.c @@ -0,0 +1,16 @@ +#include <arch/cpu.h> + +static inline uint8_t is_fam15h(void) +{ + uint8_t fam15h = 0; + uint32_t family; + + family = cpuid_eax(0x80000001); + family = ((family & 0xf00000) >> 16) | ((family & 0xf00) >> 8); + + if (family >= 0x6f) + /* Family 15h or later */ + fam15h = 1; + + return fam15h; +} diff --git a/src/northbridge/amd/amdfam10/link_control.c b/src/northbridge/amd/amdfam10/link_control.c index 468f184..a7fbe4c 100644 --- a/src/northbridge/amd/amdfam10/link_control.c +++ b/src/northbridge/amd/amdfam10/link_control.c @@ -29,21 +29,6 @@
#include "amdfam10.h"
-static inline uint8_t is_fam15h(void) -{ - uint8_t fam15h = 0; - uint32_t family; - - family = cpuid_eax(0x80000001); - family = ((family & 0xf00000) >> 16) | ((family & 0xf00) >> 8); - - if (family >= 0x6f) - /* Family 15h or later */ - fam15h = 1; - - return fam15h; -} - static void nb_control_init(struct device *dev) { uint8_t enable_c_states; diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 5634441..24e85c8 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -81,21 +81,6 @@ device_t get_node_pci(u32 nodeid, u32 fn) #endif }
-static inline uint8_t is_fam15h(void) -{ - uint8_t fam15h = 0; - uint32_t family; - - family = cpuid_eax(0x80000001); - family = ((family & 0xf00000) >> 16) | ((family & 0xf00) >> 8); - - if (family >= 0x6f) - /* Family 15h or later */ - fam15h = 1; - - return fam15h; -} - static void get_fx_devs(void) { int i; diff --git a/src/northbridge/amd/amdfam10/pci.c b/src/northbridge/amd/amdfam10/pci.c index 03b63b5..6c6d717 100644 --- a/src/northbridge/amd/amdfam10/pci.c +++ b/src/northbridge/amd/amdfam10/pci.c @@ -13,13 +13,11 @@ * GNU General Public License for more details. */
+#include "pci.h"
-#ifndef AMDFAM10_PCI_C -#define AMDFAM10_PCI_C /* bit [10,8] are dev func, bit[1,0] are dev index */
- -static u32 pci_read_config32_index(pci_devfn_t dev, u32 index_reg, u32 index) +u32 pci_read_config32_index(pci_devfn_t dev, u32 index_reg, u32 index) { u32 dword;
@@ -29,7 +27,7 @@ static u32 pci_read_config32_index(pci_devfn_t dev, u32 index_reg, u32 index) }
#ifdef UNUSED_CODE -static void pci_write_config32_index(pci_devfn_t dev, u32 index_reg, u32 index, +void pci_write_config32_index(pci_devfn_t dev, u32 index_reg, u32 index, u32 data) {
@@ -40,7 +38,7 @@ static void pci_write_config32_index(pci_devfn_t dev, u32 index_reg, u32 index, } #endif
-static u32 pci_read_config32_index_wait(pci_devfn_t dev, u32 index_reg, +u32 pci_read_config32_index_wait(pci_devfn_t dev, u32 index_reg, u32 index) {
@@ -56,7 +54,7 @@ static u32 pci_read_config32_index_wait(pci_devfn_t dev, u32 index_reg, }
#ifdef UNUSED_CODE -static void pci_write_config32_index_wait(pci_devfn_t dev, u32 index_reg, +void pci_write_config32_index_wait(pci_devfn_t dev, u32 index_reg, u32 index, u32 data) {
@@ -71,4 +69,3 @@ static void pci_write_config32_index_wait(pci_devfn_t dev, u32 index_reg,
} #endif -#endif diff --git a/src/northbridge/amd/amdfam10/pci.h b/src/northbridge/amd/amdfam10/pci.h new file mode 100644 index 0000000..8fcdbd8 --- /dev/null +++ b/src/northbridge/amd/amdfam10/pci.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Damien Zammit damien@zamaudio.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef AMDFAM10_PCI_H +#define AMDFAM10_PCI_H + +#include <inttypes.h> +#include <arch/io.h> +#include <device/pci_def.h> + +u32 pci_read_config32_index(pci_devfn_t dev, u32 index_reg, u32 index); +u32 pci_read_config32_index_wait(pci_devfn_t dev, u32 index_reg, u32 index); + +#endif diff --git a/src/northbridge/amd/amdfam10/raminit.h b/src/northbridge/amd/amdfam10/raminit.h index c1ef29e..7a06a88 100644 --- a/src/northbridge/amd/amdfam10/raminit.h +++ b/src/northbridge/amd/amdfam10/raminit.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007 Advanced Micro Devices, Inc. + * Copyright (C) 2016 Damien Zammit damien@zamaudio.com * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -13,8 +13,10 @@ * GNU General Public License for more details. */
-#ifndef RAMINIT_H -#define RAMINIT_H +#ifndef AMDFAM10_RAMINIT_H +#define AMDFAM10_RAMINIT_H + +#include "../amdmct/amddefs.h"
//DDR2 REG and unbuffered : Socket F 1027 and AM3 /* every channel have 4 DDR2 DIMM for socket F @@ -40,4 +42,25 @@ struct mem_controller { u8 spd_addr[DIMM_SOCKETS*2]; };
+#if (CONFIG_DIMM_SUPPORT & 0x000F) == 0x0005 +# include "../amdmct/mct_ddr3/mwlc_d.h" +# include "../amdmct/mct_ddr3/mct_d.h" +# include "../amdmct/mct_ddr3/mct_d_gcc.h" +#else +# include "../amdmct/mct/mct_d.h" +# include "../amdmct/mct/mct_d_gcc.h" +#endif + +struct sys_info; +struct DCTStatStruc; +struct MCTStatStruc; + +int mctRead_SPD(u32 smaddr, u32 reg); +void mctSMBhub_Init(u32 node); +void mctGet_DIMMAddr(struct DCTStatStruc *pDCTstat, u32 node); +void raminit_amdmct(struct sys_info *sysinfo); +void amdmct_cbmem_store_info(struct sys_info *sysinfo); +void fill_mem_ctrl(u32 controllers, struct mem_controller *ctrl_a, const u8 *spd_addr); +uint16_t mct_MaxLoadFreq(uint8_t count, uint8_t highest_rank_count, uint8_t registered, uint8_t voltage, uint16_t freq); +u8 mctGetProcessorPackageType(void); #endif diff --git a/src/northbridge/amd/amdfam10/raminit_amdmct.c b/src/northbridge/amd/amdfam10/raminit_amdmct.c index 86f0788..70a7903 100644 --- a/src/northbridge/amd/amdfam10/raminit_amdmct.c +++ b/src/northbridge/amd/amdfam10/raminit_amdmct.c @@ -1,6 +1,7 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2016 Damien Zammit damien@zamaudio.com * Copyright (C) 2015 Timothy Pearson tpearson@raptorengineeringinc.com, Raptor Engineering * Copyright (C) 2007 Advanced Micro Devices, Inc. * @@ -14,29 +15,20 @@ * GNU General Public License for more details. */
+#include <inttypes.h> +#include <arch/io.h> +#include <arch/acpi.h> +#include <device/pci.h> +#include <string.h> +#include <cbmem.h> +#include "amdfam10.h" +#include "raminit.h" +#include "debug.h"
-#if (CONFIG_DIMM_SUPPORT & 0x000F)!=0x0005 /* not needed for AMD_FAM10_DDR3 */ -static void print_tx(const char *strval, u32 val) -{ -#if CONFIG_DEBUG_RAM_SETUP - printk(BIOS_DEBUG, "%s%08x\n", strval, val); -#endif -} - -static void print_t(const char *strval) -{ -#if CONFIG_DEBUG_RAM_SETUP - printk(BIOS_DEBUG, "%s", strval); -#endif -} -#endif - -static void print_tf(const char *func, const char *strval) -{ -#if CONFIG_DEBUG_RAM_SETUP - printk(BIOS_DEBUG, "%s: %s", func, strval); -#endif -} +/* Define in board romstage.c */ +extern int spd_read_byte(unsigned int device, unsigned int address); +extern void activate_spd_rom(const struct mem_controller *ctrl); +extern struct sys_info sysinfo_car;
static inline void fam15h_switch_dct(uint32_t dev, uint8_t dct) { @@ -144,7 +136,7 @@ static uint16_t voltage_index_to_mv(uint8_t index) return 1500; }
-static uint16_t mct_MaxLoadFreq(uint8_t count, uint8_t highest_rank_count, uint8_t registered, uint8_t voltage, uint16_t freq) +uint16_t mct_MaxLoadFreq(uint8_t count, uint8_t highest_rank_count, uint8_t registered, uint8_t voltage, uint16_t freq) { /* FIXME * Mainboards need to be able to specify the maximum number of DIMMs installable per channel @@ -524,106 +516,6 @@ static uint16_t mct_MaxLoadFreq(uint8_t count, uint8_t highest_rank_count, uint8 return freq; }
-#if (CONFIG_DIMM_SUPPORT & 0x000F) == 0x0005 /* AMD_FAM10_DDR3 */ -#include "amdfam10.h" -#include "../amdmct/wrappers/mcti.h" -#include "../amdmct/amddefs.h" -#include "../amdmct/mct_ddr3/mwlc_d.h" -#include "../amdmct/mct_ddr3/mct_d.h" -#include "../amdmct/mct_ddr3/mct_d_gcc.h" - -#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) -#include "../amdmct/mct_ddr3/s3utils.c" -#endif - -#include "../amdmct/wrappers/mcti_d.c" -#include "../amdmct/mct_ddr3/mct_d.c" - -#include "../amdmct/mct_ddr3/mctmtr_d.c" -#include "../amdmct/mct_ddr3/mctcsi_d.c" -#include "../amdmct/mct_ddr3/mctecc_d.c" -#include "../amdmct/mct_ddr3/mctdqs_d.c" -#include "../amdmct/mct_ddr3/mctsrc.c" -#include "../amdmct/mct_ddr3/mctsdi.c" -#include "../amdmct/mct_ddr3/mctprod.c" -#include "../amdmct/mct_ddr3/mctproc.c" -#include "../amdmct/mct_ddr3/mctprob.c" -#include "../amdmct/mct_ddr3/mcthwl.c" -#include "../amdmct/mct_ddr3/mctwl.c" -#include "../amdmct/mct_ddr3/mport_d.c" -#include "../amdmct/mct_ddr3/mutilc_d.c" -#include "../amdmct/mct_ddr3/modtrdim.c" -#include "../amdmct/mct_ddr3/mhwlc_d.c" -#include "../amdmct/mct_ddr3/mctrci.c" -#include "../amdmct/mct_ddr3/mctsrc1p.c" -#include "../amdmct/mct_ddr3/mcttmrl.c" -#include "../amdmct/mct_ddr3/mcthdi.c" -#include "../amdmct/mct_ddr3/mctndi_d.c" -#include "../amdmct/mct_ddr3/mctchi_d.c" -#include "../amdmct/mct_ddr3/modtrd.c" - -#if CONFIG_CPU_SOCKET_TYPE == 0x10 -//TODO: S1G1? -#elif CONFIG_CPU_SOCKET_TYPE == 0x11 -//AM3 -#include "../amdmct/mct_ddr3/mctardk5.c" -#elif CONFIG_CPU_SOCKET_TYPE == 0x12 -//F (1207), Fr2, G (1207) -#include "../amdmct/mct_ddr3/mctardk6.c" -#elif CONFIG_CPU_SOCKET_TYPE == 0x13 -//ASB2 -#include "../amdmct/mct_ddr3/mctardk5.c" -//C32 -#elif CONFIG_CPU_SOCKET_TYPE == 0x14 -#include "../amdmct/mct_ddr3/mctardk5.c" -//G34 -#elif CONFIG_CPU_SOCKET_TYPE == 0x15 -#include "../amdmct/mct_ddr3/mctardk5.c" -//FM2 -#elif CONFIG_CPU_SOCKET_TYPE == 0x16 -#include "../amdmct/mct_ddr3/mctardk5.c" -#endif - -#else /* DDR2 */ - -#include "amdfam10.h" -#include "../amdmct/wrappers/mcti.h" -#include "../amdmct/amddefs.h" -#include "../amdmct/mct/mct_d.h" -#include "../amdmct/mct/mct_d_gcc.h" - -#include "../amdmct/wrappers/mcti_d.c" -#include "../amdmct/mct/mct_d.c" - - -#include "../amdmct/mct/mctmtr_d.c" -#include "../amdmct/mct/mctcsi_d.c" -#include "../amdmct/mct/mctecc_d.c" -#include "../amdmct/mct/mctpro_d.c" -#include "../amdmct/mct/mctdqs_d.c" -#include "../amdmct/mct/mctsrc.c" -#include "../amdmct/mct/mctsrc1p.c" -#include "../amdmct/mct/mcttmrl.c" -#include "../amdmct/mct/mcthdi.c" -#include "../amdmct/mct/mctndi_d.c" -#include "../amdmct/mct/mctchi_d.c" - -#if CONFIG_CPU_SOCKET_TYPE == 0x10 -//L1 -#include "../amdmct/mct/mctardk3.c" -#elif CONFIG_CPU_SOCKET_TYPE == 0x11 -//AM2 -#include "../amdmct/mct/mctardk4.c" -//#elif SYSTEM_TYPE == MOBILE -//s1g1 -//#include "../amdmct/mct/mctardk5.c" -#endif - -#endif /* DDR2 */ - -#include <arch/early_variables.h> -struct sys_info sysinfo_car CAR_GLOBAL; - int mctRead_SPD(u32 smaddr, u32 reg) { return spd_read_byte(smaddr, reg); @@ -652,14 +544,14 @@ void mctGet_DIMMAddr(struct DCTStatStruc *pDCTstat, u32 node) }
#if IS_ENABLED(CONFIG_SET_FIDVID) -static u8 mctGetProcessorPackageType(void) { +u8 mctGetProcessorPackageType(void) { /* FIXME: I guess this belongs wherever mctGetLogicalCPUID ends up ? */ u32 BrandId = cpuid_ebx(0x80000001); return (u8)((BrandId >> 28) & 0x0F); } #endif
-static void raminit_amdmct(struct sys_info *sysinfo) +void raminit_amdmct(struct sys_info *sysinfo) { struct MCTStatStruc *pMCTstat = &(sysinfo->MCTstat); struct DCTStatStruc *pDCTstatA = sysinfo->DCTstatA; @@ -671,7 +563,7 @@ static void raminit_amdmct(struct sys_info *sysinfo) printk(BIOS_DEBUG, "raminit_amdmct end:\n"); }
-static void amdmct_cbmem_store_info(struct sys_info *sysinfo) +void amdmct_cbmem_store_info(struct sys_info *sysinfo) { if (!sysinfo) return; diff --git a/src/northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c b/src/northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c index 0461323..bc2c29d 100644 --- a/src/northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c +++ b/src/northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */
+#include "amdfam10.h" #include <delay.h>
static void set_htic_bit(u8 i, u32 val, u8 bit) @@ -45,12 +46,7 @@ static void wait_till_sysinfo_in_ram(void) } #endif
-static void set_sysinfo_in_ram(u32 val) -{ - set_htic_bit(0, val, 9); -} - -static void fill_mem_ctrl(u32 controllers, struct mem_controller *ctrl_a, const u8 *spd_addr) +void fill_mem_ctrl(u32 controllers, struct mem_controller *ctrl_a, const u8 *spd_addr) { int i; int j; @@ -76,3 +72,8 @@ static void fill_mem_ctrl(u32 controllers, struct mem_controller *ctrl_a, const } } } + +void set_sysinfo_in_ram(u32 val) +{ + set_htic_bit(0, val, 9); +} diff --git a/src/northbridge/amd/amdfam10/reset_test.c b/src/northbridge/amd/amdfam10/reset_test.c index 0e64397..4fa3385 100644 --- a/src/northbridge/amd/amdfam10/reset_test.c +++ b/src/northbridge/amd/amdfam10/reset_test.c @@ -17,12 +17,6 @@ #include <cpu/x86/lapic.h> #include "amdfam10.h"
-#define NODE_ID 0x60 -#define HT_INIT_CONTROL 0x6c -#define HTIC_ColdR_Detect (1<<4) -#define HTIC_BIOSR_Detect (1<<5) -#define HTIC_INIT_Detect (1<<6) - /* mmconf is not ready */ /* io_ext is not ready */ u32 cpu_init_detected(u8 nodeid) @@ -60,7 +54,7 @@ u32 other_reset_detected(void) // other warm reset not started by BIOS return (htic & HTIC_ColdR_Detect) && (htic & HTIC_BIOSR_Detect); }
-static void distinguish_cpu_resets(u8 nodeid) +void distinguish_cpu_resets(u8 nodeid) { u32 htic; pci_devfn_t device; @@ -70,7 +64,7 @@ static void distinguish_cpu_resets(u8 nodeid) pci_io_write_config32(device, HT_INIT_CONTROL, htic); }
-static u32 warm_reset_detect(u8 nodeid) +u32 warm_reset_detect(u8 nodeid) { u32 htic; pci_devfn_t device; @@ -79,7 +73,6 @@ static u32 warm_reset_detect(u8 nodeid) return (htic & HTIC_ColdR_Detect) && !(htic & HTIC_BIOSR_Detect); }
-void set_bios_reset(void); void set_bios_reset(void) {
diff --git a/src/northbridge/amd/amdfam10/setup_resource_map.c b/src/northbridge/amd/amdfam10/setup_resource_map.c index 3d67bdd..cd9b376 100644 --- a/src/northbridge/amd/amdfam10/setup_resource_map.c +++ b/src/northbridge/amd/amdfam10/setup_resource_map.c @@ -14,10 +14,13 @@ * GNU General Public License for more details. */
+#include <inttypes.h> +#include "amdfam10.h" +#include <console/console.h>
#define RES_DEBUG 0
-static void setup_resource_map(const u32 *register_values, u32 max) +void setup_resource_map(const u32 *register_values, u32 max) { u32 i;
@@ -53,11 +56,6 @@ void setup_resource_map_offset(const u32 *register_values, u32 max, u32 offset_p } }
-#define RES_PCI_IO 0x10 -#define RES_PORT_IO_8 0x22 -#define RES_PORT_IO_32 0x20 -#define RES_MEM_IO 0x40 - void setup_resource_map_x_offset(const u32 *register_values, u32 max, u32 offset_pci_dev, u32 offset_io_base) { u32 i; diff --git a/src/northbridge/amd/amdht/comlib.h b/src/northbridge/amd/amdht/comlib.h index b696b69..0253fed 100644 --- a/src/northbridge/amd/amdht/comlib.h +++ b/src/northbridge/amd/amdht/comlib.h @@ -16,9 +16,15 @@ #ifndef COMLIB_H #define COMLIB_H
-#ifndef FILECODE -#error "FILECODE was not defined, should be #define'd to 0xFxxx" -#endif +#undef FILECODE +#define FILECODE 0xF001 + +#include <inttypes.h> +#include <stdlib.h> +#include <device/pci.h> +#include <console/console.h> +#include <cpu/amd/msr.h> +#include <northbridge/amd/amdfam10/amdfam10.h>
#include "porting.h"
diff --git a/src/northbridge/amd/amdht/h3ffeat.h b/src/northbridge/amd/amdht/h3ffeat.h index bcd4c10..59e8feb 100644 --- a/src/northbridge/amd/amdht/h3ffeat.h +++ b/src/northbridge/amd/amdht/h3ffeat.h @@ -18,6 +18,8 @@ #ifndef H3FFEAT_H #define H3FFEAT_H
+#include "h3finit.h" + /*---------------------------------------------------------------------------- * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) * diff --git a/src/northbridge/amd/amdht/h3finit.c b/src/northbridge/amd/amdht/h3finit.c index 2baf886..3023c20 100644 --- a/src/northbridge/amd/amdht/h3finit.c +++ b/src/northbridge/amd/amdht/h3finit.c @@ -21,19 +21,11 @@ *---------------------------------------------------------------------------- */
-#undef FILECODE -#define FILECODE 0xF001 - -#include "comlib.h" #include "h3finit.h" #include "h3ffeat.h" #include "h3ncmn.h" #include "h3gtopo.h" #include "AsPsNb.h" -/* this is pre-ram so include the required C files here */ -#include "comlib.c" -#include "AsPsNb.c" -#include "h3ncmn.c"
/*---------------------------------------------------------------------------- * DEFINITIONS AND MACROS @@ -41,9 +33,6 @@ *---------------------------------------------------------------------------- */
-#undef FILECODE -#define FILECODE 0xF001 - /* APIC defines from amdgesa.inc, which can't be included in to c code. */ #define APIC_Base_BSP 8 #define APIC_Base 0x1b diff --git a/src/northbridge/amd/amdht/h3finit.h b/src/northbridge/amd/amdht/h3finit.h index c973792..45ed3c1 100644 --- a/src/northbridge/amd/amdht/h3finit.h +++ b/src/northbridge/amd/amdht/h3finit.h @@ -17,6 +17,8 @@ #ifndef H3FINIT_H #define H3FINIT_H
+#include "comlib.h" + /*---------------------------------------------------------------------------- * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) * diff --git a/src/northbridge/amd/amdht/h3ncmn.c b/src/northbridge/amd/amdht/h3ncmn.c index 0d0055b..bf6bc39 100644 --- a/src/northbridge/amd/amdht/h3ncmn.c +++ b/src/northbridge/amd/amdht/h3ncmn.c @@ -23,9 +23,9 @@
#undef FILECODE #define FILECODE 0xF002 +#include "h3ncmn.h" #include "h3finit.h" #include "h3ffeat.h" -#include "h3ncmn.h" #include "AsPsNb.h"
@@ -89,22 +89,7 @@ *** FAMILY/NORTHBRIDGE SPECIFIC FUNCTIONS *** ***************************************************************************/
-static inline uint8_t is_fam15h(void) -{ - uint8_t fam15h = 0; - uint32_t family; - - family = cpuid_eax(0x80000001); - family = ((family & 0xf00000) >> 16) | ((family & 0xf00) >> 8); - - if (family >= 0x6f) - /* Family 15h or later */ - fam15h = 1; - - return fam15h; -} - -static inline uint8_t is_gt_rev_d(void) +inline uint8_t is_gt_rev_d(void) { uint8_t fam15h = 0; uint8_t rev_gte_d = 0; diff --git a/src/northbridge/amd/amdht/h3ncmn.h b/src/northbridge/amd/amdht/h3ncmn.h index 3c8a346..f37d7bc 100644 --- a/src/northbridge/amd/amdht/h3ncmn.h +++ b/src/northbridge/amd/amdht/h3ncmn.h @@ -17,17 +17,13 @@ #ifndef H3NCMN_H #define H3NCMN_H
-/*---------------------------------------------------------------------------- - * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) - * - *---------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *----------------------------------------------------------------------------- - */ +#include <inttypes.h> +#include <device/pci.h> +#include <console/console.h> +#include <cpu/amd/msr.h> +#include "comlib.h" +#include "h3finit.h" +#include "h3ffeat.h"
/* Use a macro to convert a node number to a PCI device. If some future port of * this code needs to, this can easily be replaced by a function call: @@ -65,12 +61,6 @@ ((u16)fc & HT_FREQUENCY_LIMIT_HT1_ONLY) #endif
-/*---------------------------------------------------------------------------- - * TYPEDEFS, STRUCTURES, ENUMS - * - *---------------------------------------------------------------------------- - */ - struct cNorthBridge { /* Public data, clients of northbridge can access */ @@ -119,11 +109,7 @@ struct cNorthBridge u32 compatibleKey; } ;
-/*---------------------------------------------------------------------------- - * FUNCTIONS PROTOTYPE - * - *---------------------------------------------------------------------------- - */ void newNorthBridge(u8 node, cNorthBridge *nb); +inline uint8_t is_gt_rev_d(void);
#endif /* H3NCMN_H */ diff --git a/src/northbridge/amd/amdht/ht_wrapper.c b/src/northbridge/amd/amdht/ht_wrapper.c index 4c68f41..8a25993 100644 --- a/src/northbridge/amd/amdht/ht_wrapper.c +++ b/src/northbridge/amd/amdht/ht_wrapper.c @@ -16,8 +16,6 @@
#include <cpu/x86/msr.h> #include <console/console.h> -#include <northbridge/amd/amdfam10/amdfam10.h> - #include "ht_wrapper.h"
/*---------------------------------------------------------------------------- @@ -51,37 +49,12 @@ #include "h3gtopo.h" #include "h3finit.h"
-/* include the main HT source file */ -#include "h3finit.c" - - /*---------------------------------------------------------------------------- * LOCAL FUNCTIONS * *---------------------------------------------------------------------------- */
-/* FIXME: Find a better place for these pre-ram functions. */ -#define NODE_HT(x) NODE_PCI(x,0) -#define NODE_MP(x) NODE_PCI(x,1) -#define NODE_MC(x) NODE_PCI(x,3) -#define NODE_LC(x) NODE_PCI(x,4) - -static u32 get_nodes(void) -{ - pci_devfn_t dev; - u32 nodes; - - dev = PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0); - nodes = ((pci_read_config32(dev, 0x60)>>4) & 7); -#if CONFIG_MAX_PHYSICAL_CPUS > 8 - nodes += (((pci_read_config32(dev, 0x160)>>4) & 7)<<3); -#endif - nodes++; - - return nodes; -} - static const char * event_class_string_decodes[] = { [HT_EVENT_CLASS_CRITICAL] = "CRITICAL", [HT_EVENT_CLASS_ERROR] = "ERROR", @@ -255,7 +228,7 @@ static BOOL AMD_CB_IgnoreLink (u8 node, u8 link) * AMD HT init coreboot wrapper * */ -static void amd_ht_init(struct sys_info *sysinfo) +void amd_ht_init(struct sys_info *sysinfo) {
if (!sysinfo) { @@ -390,3 +363,18 @@ void amd_ht_fixup(struct sys_info *sysinfo) { } } } + +u32 get_nodes(void) +{ + pci_devfn_t dev; + u32 nodes; + + dev = PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0); + nodes = ((pci_read_config32(dev, 0x60)>>4) & 7); +#if CONFIG_MAX_PHYSICAL_CPUS > 8 + nodes += (((pci_read_config32(dev, 0x160)>>4) & 7)<<3); +#endif + nodes++; + + return nodes; +} diff --git a/src/northbridge/amd/amdht/ht_wrapper.h b/src/northbridge/amd/amdht/ht_wrapper.h index 5c3c2d9..b39c810 100644 --- a/src/northbridge/amd/amdht/ht_wrapper.h +++ b/src/northbridge/amd/amdht/ht_wrapper.h @@ -16,6 +16,12 @@ #ifndef AMD_HT_WRAPPER_H #define AMD_HT_WRAPPER_H
+#include <northbridge/amd/amdfam10/amdfam10.h> +#include <inttypes.h> +#include "h3finit.h" + void amd_ht_fixup(struct sys_info *sysinfo); +u32 get_nodes(void); +void amd_ht_init(struct sys_info *sysinfo);
#endif diff --git a/src/northbridge/amd/amdmct/mct/mct_d.c b/src/northbridge/amd/amdmct/mct/mct_d.c index 62fc626..f70c09f 100644 --- a/src/northbridge/amd/amdmct/mct/mct_d.c +++ b/src/northbridge/amd/amdmct/mct/mct_d.c @@ -33,6 +33,8 @@ * supported. */
+#include "mct_d.h" + static u8 ReconfigureDIMMspare_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); static void DQSTiming_D(struct MCTStatStruc *pMCTstat, @@ -41,15 +43,8 @@ static void LoadDQSSigTmgRegs_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); static void HTMemMapInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); -static void MCTMemClr_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstatA); -static void DCTMemClr_Init_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat); static void DCTMemClr_Sync_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat); -static void MCTMemClrSync_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstatA); -static u8 NodePresent_D(u8 Node); static void SyncDCTsReady_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); static void StartupDCT_D(struct MCTStatStruc *pMCTstat, @@ -175,7 +170,7 @@ static const u8 Table_Comp_Rise_Slew_15x[] = {7, 7, 3, 2, 0xFF}; static const u8 Table_Comp_Fall_Slew_20x[] = {7, 5, 3, 2, 0xFF}; static const u8 Table_Comp_Fall_Slew_15x[] = {7, 7, 5, 3, 0xFF};
-static void mctAutoInitMCT_D(struct MCTStatStruc *pMCTstat, +void mctAutoInitMCT_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) { /* @@ -661,7 +656,7 @@ static void HTMemMapInit_D(struct MCTStatStruc *pMCTstat, }
-static void MCTMemClr_D(struct MCTStatStruc *pMCTstat, +void MCTMemClr_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) {
@@ -693,7 +688,7 @@ static void MCTMemClr_D(struct MCTStatStruc *pMCTstat, }
-static void DCTMemClr_Init_D(struct MCTStatStruc *pMCTstat, +void DCTMemClr_Init_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat) { u32 val; @@ -716,7 +711,7 @@ static void DCTMemClr_Init_D(struct MCTStatStruc *pMCTstat, }
-static void MCTMemClrSync_D(struct MCTStatStruc *pMCTstat, +void MCTMemClrSync_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) { /* Ensures that memory clear has completed on all node.*/ @@ -768,7 +763,7 @@ static void DCTMemClr_Sync_D(struct MCTStatStruc *pMCTstat, }
-static u8 NodePresent_D(u8 Node) +u8 NodePresent_D(u8 Node) { /* * Determine if a single Hammer Node exists within the network. @@ -3655,7 +3650,7 @@ static void mct_BeforeDramInit_Prod_D(struct MCTStatStruc *pMCTstat, }
-static void mct_AdjustDelayRange_D(struct MCTStatStruc *pMCTstat, +void mct_AdjustDelayRange_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 *dqs_pos) { // FIXME: Skip for Ax @@ -3907,7 +3902,7 @@ static void mct_ResetDLL_D(struct MCTStatStruc *pMCTstat, }
-static void mct_EnableDatIntlv_D(struct MCTStatStruc *pMCTstat, +void mct_EnableDatIntlv_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat) { u32 dev = pDCTstat->dev_dct; diff --git a/src/northbridge/amd/amdmct/mct/mct_d.h b/src/northbridge/amd/amdmct/mct/mct_d.h index 4e1a909..3170749 100644 --- a/src/northbridge/amd/amdmct/mct/mct_d.h +++ b/src/northbridge/amd/amdmct/mct/mct_d.h @@ -20,7 +20,18 @@ #ifndef MCT_D_H #define MCT_D_H
+#define DQS_TRAIN_DEBUG 0
+#include <inttypes.h> +#include "mct_d_gcc.h" +#include <northbridge/amd/amdfam10/debug.h> +#include <northbridge/amd/amdfam10/raminit.h> +#include <northbridge/amd/amdmct/wrappers/mcti.h> + +extern const u8 Table_DQSRcvEn_Offset[]; +extern const u32 TestPattern0_D[]; +extern const u32 TestPattern1_D[]; +extern const u32 TestPattern2_D[];
/*=========================================================================== CPU - K8/FAM10 @@ -689,6 +700,8 @@ struct DCTStatStruc { /* A per Node structure*/
#define NV_MAX_DIMMS_PER_CH 64 /* Maximum number of DIMMs per channel */
+#include <northbridge/amd/amdfam10/amdfam10.h> + /*=============================================================================== CBMEM storage ===============================================================================*/ @@ -735,9 +748,6 @@ void mct_TrainRcvrEn_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTs void mct_EnableDimmEccEn_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 _DisableDramECC); u32 procOdtWorkaround(struct DCTStatStruc *pDCTstat, u32 dct, u32 val); void mct_BeforeDramInit_D(struct DCTStatStruc *pDCTstat, u32 dct); -void mctGet_DIMMAddr(struct DCTStatStruc *pDCTstat, u32 node); -void mctSMBhub_Init(u32 node); -int mctRead_SPD(u32 smaddr, u32 reg); void InterleaveNodes_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); void InterleaveChannels_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); void mct_BeforeDQSTrain_Samp_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat); @@ -753,4 +763,35 @@ u8 mct_RcvrRankEnabled_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDC u32 mct_GetRcvrSysAddr_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 channel, u8 receiver, u8 *valid); void mct_Read1LTestPattern_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u32 addr); void EarlySampleSupport_D(void); + +void mctAutoInitMCT_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); +void mct_AdjustDelayRange_D(struct MCTStatStruc *pMCTstat, + struct DCTStatStruc *pDCTstat, u8 *dqs_pos); +void mct_EnableDatIntlv_D(struct MCTStatStruc *pMCTstat, + struct DCTStatStruc *pDCTstat); +void MCTMemClrSync_D(struct MCTStatStruc *pMCTstat, + struct DCTStatStruc *pDCTstatA); +void beforeInterleaveChannels_D(struct DCTStatStruc *pDCTstatA, u8 *enabled); +u8 mct_checkFenceHoleAdjust_D(struct MCTStatStruc *pMCTstat, + struct DCTStatStruc *pDCTstat, u8 DQSDelay, + u8 ChipSel, u8 *result); +void proc_IOCLFLUSH_D(u32 addr_hi); +void mct_Write1LTestPattern_D(struct MCTStatStruc *pMCTstat, + struct DCTStatStruc *pDCTstat, + u32 TestAddr, u8 pattern); +u8 NodePresent_D(u8 Node); +void DCTMemClr_Init_D(struct MCTStatStruc *pMCTstat, + struct DCTStatStruc *pDCTstat); +void MCTMemClr_D(struct MCTStatStruc *pMCTstat, + struct DCTStatStruc *pDCTstatA); +void print_debug_dqs(const char *str, u32 val, u8 level); +void print_debug_dqs_pair(const char *str, u32 val, const char *str2, u32 val2, u8 level); +u8 mct_DisableDimmEccEn_D(struct MCTStatStruc *pMCTstat, + struct DCTStatStruc *pDCTstat); +void ResetDCTWrPtr_D(u32 dev, u32 index_reg, u32 index); +void SetTargetWTIO_D(u32 TestAddr); +void ResetTargetWTIO_D(void); +u32 mct_GetMCTSysAddr_D(struct MCTStatStruc *pMCTstat, + struct DCTStatStruc *pDCTstat, u8 Channel, + u8 receiver, u8 *valid); #endif diff --git a/src/northbridge/amd/amdmct/mct/mct_d_gcc.c b/src/northbridge/amd/amdmct/mct/mct_d_gcc.c new file mode 100644 index 0000000..59618f6 --- /dev/null +++ b/src/northbridge/amd/amdmct/mct/mct_d_gcc.c @@ -0,0 +1,351 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "mct_d_gcc.h" + +inline void _WRMSR(u32 addr, u32 lo, u32 hi) +{ + __asm__ volatile ( + "wrmsr" + : + :"c"(addr),"a"(lo), "d" (hi) + ); +} + + +inline void _RDMSR(u32 addr, u32 *lo, u32 *hi) +{ + __asm__ volatile ( + "rdmsr" + :"=a"(*lo), "=d" (*hi) + :"c"(addr) + ); +} + + +inline void _RDTSC(u32 *lo, u32 *hi) +{ + __asm__ volatile ( + "rdtsc" + : "=a" (*lo), "=d"(*hi) + ); +} + + +inline void _cpu_id(u32 addr, u32 *val) +{ + __asm__ volatile( + "cpuid" + : "=a" (val[0]), + "=b" (val[1]), + "=c" (val[2]), + "=d" (val[3]) + : "0" (addr)); + +} + + +u32 bsr(u32 x) +{ + u8 i; + u32 ret = 0; + + for (i = 31; i > 0; i--) { + if (x & (1<<i)) { + ret = i; + break; + } + } + + return ret; + +} + + +u32 bsf(u32 x) +{ + u8 i; + u32 ret = 32; + + for (i = 0; i < 32; i++) { + if (x & (1<<i)) { + ret = i; + break; + } + } + + return ret; +} + +#define _MFENCE asm volatile ("mfence") + +#define _SFENCE asm volatile ("sfence") + +/* prevent speculative execution of following instructions */ +#define _EXECFENCE asm volatile ("outb %al, $0xed") + +#include <cpu/x86/cr.h> + +void proc_CLFLUSH(u32 addr_hi) +{ + SetUpperFSbase(addr_hi); + + __asm__ volatile ( + /* clflush fs:[eax] */ + "outb %%al, $0xed\n\t" /* _EXECFENCE */ + "clflush %%fs:(%0)\n\t" + "mfence\n\t" + ::"a" (addr_hi<<8) + ); +} + + +void WriteLNTestPattern(u32 addr_lo, u8 *buf_a, u32 line_num) +{ + __asm__ volatile ( + /*prevent speculative execution of following instructions*/ + /* FIXME: needed ? */ + "outb %%al, $0xed\n\t" /* _EXECFENCE */ + "1:\n\t" + "movdqa (%3), %%xmm0\n\t" + "movntdq %%xmm0, %%fs:(%0)\n\t" /* xmm0 is 128 bit */ + "addl %1, %0\n\t" + "addl %1, %3\n\t" + "loop 1b\n\t" + "mfence\n\t" + + :: "a" (addr_lo), "d" (16), "c" (line_num * 4), "b"(buf_a) + ); + +} + + +u32 read32_fs(u32 addr_lo) +{ + u32 value; + __asm__ volatile ( + "outb %%al, $0xed\n\t" /* _EXECFENCE */ + "movl %%fs:(%1), %0\n\t" + :"=b"(value): "a" (addr_lo) + ); + return value; +} + +#ifdef UNUSED_CODE +static u8 read8_fs(u32 addr_lo) +{ + u8 byte; + __asm__ volatile ( + "outb %%al, $0xed\n\t" /* _EXECFENCE */ + "movb %%fs:(%1), %b0\n\t" + "mfence\n\t" + :"=b"(byte): "a" (addr_lo) + ); + return byte; +} +#endif + +void FlushDQSTestPattern_L9(u32 addr_lo) +{ + __asm__ volatile ( + "outb %%al, $0xed\n\t" /* _EXECFENCE */ + "clflush %%fs:-128(%%ecx)\n\t" + "clflush %%fs:-64(%%ecx)\n\t" + "clflush %%fs:(%%ecx)\n\t" + "clflush %%fs:64(%%ecx)\n\t" + + "clflush %%fs:-128(%%eax)\n\t" + "clflush %%fs:-64(%%eax)\n\t" + "clflush %%fs:(%%eax)\n\t" + "clflush %%fs:64(%%eax)\n\t" + + "clflush %%fs:-128(%%ebx)\n\t" + + :: "b" (addr_lo+128+8*64), "c"(addr_lo+128), + "a"(addr_lo+128+4*64) + ); + +} + + +__attribute__((noinline)) void FlushDQSTestPattern_L18(u32 addr_lo) +{ + __asm__ volatile ( + "outb %%al, $0xed\n\t" /* _EXECFENCE */ + "clflush %%fs:-128(%%eax)\n\t" + "clflush %%fs:-64(%%eax)\n\t" + "clflush %%fs:(%%eax)\n\t" + "clflush %%fs:64(%%eax)\n\t" + + "clflush %%fs:-128(%%edi)\n\t" + "clflush %%fs:-64(%%edi)\n\t" + "clflush %%fs:(%%edi)\n\t" + "clflush %%fs:64(%%edi)\n\t" + + "clflush %%fs:-128(%%ebx)\n\t" + "clflush %%fs:-64(%%ebx)\n\t" + "clflush %%fs:(%%ebx)\n\t" + "clflush %%fs:64(%%ebx)\n\t" + + "clflush %%fs:-128(%%ecx)\n\t" + "clflush %%fs:-64(%%ecx)\n\t" + "clflush %%fs:(%%ecx)\n\t" + "clflush %%fs:64(%%ecx)\n\t" + + "clflush %%fs:-128(%%edx)\n\t" + "clflush %%fs:-64(%%edx)\n\t" + + :: "b" (addr_lo+128+8*64), "c" (addr_lo+128+12*64), + "d" (addr_lo +128+16*64), "a"(addr_lo+128), + "D"(addr_lo+128+4*64) + ); +} + +void ReadL18TestPattern(u32 addr_lo) +{ + // set fs and use fs prefix to access the mem + __asm__ volatile ( + "outb %%al, $0xed\n\t" /* _EXECFENCE */ + "movl %%fs:-128(%%esi), %%eax\n\t" //TestAddr cache line + "movl %%fs:-64(%%esi), %%eax\n\t" //+1 + "movl %%fs:(%%esi), %%eax\n\t" //+2 + "movl %%fs:64(%%esi), %%eax\n\t" //+3 + + "movl %%fs:-128(%%edi), %%eax\n\t" //+4 + "movl %%fs:-64(%%edi), %%eax\n\t" //+5 + "movl %%fs:(%%edi), %%eax\n\t" //+6 + "movl %%fs:64(%%edi), %%eax\n\t" //+7 + + "movl %%fs:-128(%%ebx), %%eax\n\t" //+8 + "movl %%fs:-64(%%ebx), %%eax\n\t" //+9 + "movl %%fs:(%%ebx), %%eax\n\t" //+10 + "movl %%fs:64(%%ebx), %%eax\n\t" //+11 + + "movl %%fs:-128(%%ecx), %%eax\n\t" //+12 + "movl %%fs:-64(%%ecx), %%eax\n\t" //+13 + "movl %%fs:(%%ecx), %%eax\n\t" //+14 + "movl %%fs:64(%%ecx), %%eax\n\t" //+15 + + "movl %%fs:-128(%%edx), %%eax\n\t" //+16 + "movl %%fs:-64(%%edx), %%eax\n\t" //+17 + "mfence\n\t" + + :: "a"(0), "b" (addr_lo+128+8*64), "c" (addr_lo+128+12*64), + "d" (addr_lo +128+16*64), "S"(addr_lo+128), + "D"(addr_lo+128+4*64) + ); + +} + +void ReadL9TestPattern(u32 addr_lo) +{ + + // set fs and use fs prefix to access the mem + __asm__ volatile ( + "outb %%al, $0xed\n\t" /* _EXECFENCE */ + + "movl %%fs:-128(%%ecx), %%eax\n\t" //TestAddr cache line + "movl %%fs:-64(%%ecx), %%eax\n\t" //+1 + "movl %%fs:(%%ecx), %%eax\n\t" //+2 + "movl %%fs:64(%%ecx), %%eax\n\t" //+3 + + "movl %%fs:-128(%%edx), %%eax\n\t" //+4 + "movl %%fs:-64(%%edx), %%eax\n\t" //+5 + "movl %%fs:(%%edx), %%eax\n\t" //+6 + "movl %%fs:64(%%edx), %%eax\n\t" //+7 + + "movl %%fs:-128(%%ebx), %%eax\n\t" //+8 + "mfence\n\t" + + :: "a"(0), "b" (addr_lo+128+8*64), "c"(addr_lo+128), + "d"(addr_lo+128+4*64) + ); + +} + +void ReadMaxRdLat1CLTestPattern_D(u32 addr) +{ + SetUpperFSbase(addr); + + __asm__ volatile ( + "outb %%al, $0xed\n\t" /* _EXECFENCE */ + "movl %%fs:-128(%%esi), %%eax\n\t" //TestAddr cache line + "movl %%fs:-64(%%esi), %%eax\n\t" //+1 + "movl %%fs:(%%esi), %%eax\n\t" //+2 + "mfence\n\t" + :: "a"(0), "S"((addr<<8)+128) + ); + +} + +void WriteMaxRdLat1CLTestPattern_D(u32 buf, u32 addr) +{ + SetUpperFSbase(addr); + + __asm__ volatile ( + "outb %%al, $0xed\n\t" /* _EXECFENCE */ + "1:\n\t" + "movdqa (%3), %%xmm0\n\t" + "movntdq %%xmm0, %%fs:(%0)\n\t" /* xmm0 is 128 bit */ + "addl %1, %0\n\t" + "addl %1, %3\n\t" + "loop 1b\n\t" + "mfence\n\t" + + :: "a" (addr<<8), "d" (16), "c" (3 * 4), "b"(buf) + ); +} + +void FlushMaxRdLatTestPattern_D(u32 addr) +{ + /* Flush a pattern of 72 bit times (per DQ) from cache. + * This procedure is used to ensure cache miss on the next read training. + */ + + SetUpperFSbase(addr); + + __asm__ volatile ( + "outb %%al, $0xed\n\t" /* _EXECFENCE */ + "clflush %%fs:-128(%%esi)\n\t" //TestAddr cache line + "clflush %%fs:-64(%%esi)\n\t" //+1 + "clflush %%fs:(%%esi)\n\t" //+2 + "mfence\n\t" + + :: "S"((addr<<8)+128) + ); +} + +u32 stream_to_int(u8 const *p) +{ + int i; + u32 val; + u32 valx; + + val = 0; + + for (i = 3; i >= 0; i--) { + val <<= 8; + valx = *(p+i); + val |= valx; + } + + return val; +} + +u8 oemNodePresent_D(u8 Node, u8 *ret) +{ + *ret = 0; + return 0; +} diff --git a/src/northbridge/amd/amdmct/mct/mct_d_gcc.h b/src/northbridge/amd/amdmct/mct/mct_d_gcc.h index fbfe988..d2d351f 100644 --- a/src/northbridge/amd/amdmct/mct/mct_d_gcc.h +++ b/src/northbridge/amd/amdmct/mct/mct_d_gcc.h @@ -13,83 +13,19 @@ * GNU General Public License for more details. */
+#ifndef MCT_D_GCC_H +#define MCT_D_GCC_H
-static inline void _WRMSR(u32 addr, u32 lo, u32 hi) -{ - __asm__ volatile ( - "wrmsr" - : - :"c"(addr),"a"(lo), "d" (hi) - ); -} +#include <inttypes.h>
- -static inline void _RDMSR(u32 addr, u32 *lo, u32 *hi) -{ - __asm__ volatile ( - "rdmsr" - :"=a"(*lo), "=d" (*hi) - :"c"(addr) - ); -} - - -static inline void _RDTSC(u32 *lo, u32 *hi) -{ - __asm__ volatile ( - "rdtsc" - : "=a" (*lo), "=d"(*hi) - ); -} - - -static inline void _cpu_id(u32 addr, u32 *val) -{ - __asm__ volatile( - "cpuid" - : "=a" (val[0]), - "=b" (val[1]), - "=c" (val[2]), - "=d" (val[3]) - : "0" (addr)); - -} - - -static u32 bsr(u32 x) -{ - u8 i; - u32 ret = 0; - - for (i = 31; i > 0; i--) { - if (x & (1<<i)) { - ret = i; - break; - } - } - - return ret; - -} - - -static u32 bsf(u32 x) -{ - u8 i; - u32 ret = 32; - - for (i = 0; i < 32; i++) { - if (x & (1<<i)) { - ret = i; - break; - } - } - - return ret; -} +inline void _WRMSR(u32 addr, u32 lo, u32 hi); +inline void _RDMSR(u32 addr, u32 *lo, u32 *hi); +inline void _RDTSC(u32 *lo, u32 *hi); +inline void _cpu_id(u32 addr, u32 *val); +u32 bsr(u32 x); +u32 bsf(u32 x);
#define _MFENCE asm volatile ("mfence") - #define _SFENCE asm volatile ("sfence")
/* prevent speculative execution of following instructions */ @@ -98,277 +34,17 @@ static u32 bsf(u32 x) #include <cpu/x86/cr.h>
u32 SetUpperFSbase(u32 addr_hi); +void proc_CLFLUSH(u32 addr_hi); +void WriteLNTestPattern(u32 addr_lo, u8 *buf_a, u32 line_num); +u32 read32_fs(u32 addr_lo); +void FlushDQSTestPattern_L9(u32 addr_lo); +__attribute__((noinline)) void FlushDQSTestPattern_L18(u32 addr_lo); +void ReadL18TestPattern(u32 addr_lo); +void ReadL9TestPattern(u32 addr_lo); +void ReadMaxRdLat1CLTestPattern_D(u32 addr); +void WriteMaxRdLat1CLTestPattern_D(u32 buf, u32 addr); +void FlushMaxRdLatTestPattern_D(u32 addr); +u32 stream_to_int(u8 const *p); +u8 oemNodePresent_D(u8 Node, u8 *ret);
- -static void proc_CLFLUSH(u32 addr_hi) -{ - SetUpperFSbase(addr_hi); - - __asm__ volatile ( - /* clflush fs:[eax] */ - "outb %%al, $0xed\n\t" /* _EXECFENCE */ - "clflush %%fs:(%0)\n\t" - "mfence\n\t" - ::"a" (addr_hi<<8) - ); -} - - -static void WriteLNTestPattern(u32 addr_lo, u8 *buf_a, u32 line_num) -{ - __asm__ volatile ( - /*prevent speculative execution of following instructions*/ - /* FIXME: needed ? */ - "outb %%al, $0xed\n\t" /* _EXECFENCE */ - "1:\n\t" - "movdqa (%3), %%xmm0\n\t" - "movntdq %%xmm0, %%fs:(%0)\n\t" /* xmm0 is 128 bit */ - "addl %1, %0\n\t" - "addl %1, %3\n\t" - "loop 1b\n\t" - "mfence\n\t" - - :: "a" (addr_lo), "d" (16), "c" (line_num * 4), "b"(buf_a) - ); - -} - - -static u32 read32_fs(u32 addr_lo) -{ - u32 value; - __asm__ volatile ( - "outb %%al, $0xed\n\t" /* _EXECFENCE */ - "movl %%fs:(%1), %0\n\t" - :"=b"(value): "a" (addr_lo) - ); - return value; -} - -#ifdef UNUSED_CODE -static u8 read8_fs(u32 addr_lo) -{ - u8 byte; - __asm__ volatile ( - "outb %%al, $0xed\n\t" /* _EXECFENCE */ - "movb %%fs:(%1), %b0\n\t" - "mfence\n\t" - :"=b"(byte): "a" (addr_lo) - ); - return byte; -} -#endif - -static void FlushDQSTestPattern_L9(u32 addr_lo) -{ - __asm__ volatile ( - "outb %%al, $0xed\n\t" /* _EXECFENCE */ - "clflush %%fs:-128(%%ecx)\n\t" - "clflush %%fs:-64(%%ecx)\n\t" - "clflush %%fs:(%%ecx)\n\t" - "clflush %%fs:64(%%ecx)\n\t" - - "clflush %%fs:-128(%%eax)\n\t" - "clflush %%fs:-64(%%eax)\n\t" - "clflush %%fs:(%%eax)\n\t" - "clflush %%fs:64(%%eax)\n\t" - - "clflush %%fs:-128(%%ebx)\n\t" - - :: "b" (addr_lo+128+8*64), "c"(addr_lo+128), - "a"(addr_lo+128+4*64) - ); - -} - - -static __attribute__((noinline)) void FlushDQSTestPattern_L18(u32 addr_lo) -{ - __asm__ volatile ( - "outb %%al, $0xed\n\t" /* _EXECFENCE */ - "clflush %%fs:-128(%%eax)\n\t" - "clflush %%fs:-64(%%eax)\n\t" - "clflush %%fs:(%%eax)\n\t" - "clflush %%fs:64(%%eax)\n\t" - - "clflush %%fs:-128(%%edi)\n\t" - "clflush %%fs:-64(%%edi)\n\t" - "clflush %%fs:(%%edi)\n\t" - "clflush %%fs:64(%%edi)\n\t" - - "clflush %%fs:-128(%%ebx)\n\t" - "clflush %%fs:-64(%%ebx)\n\t" - "clflush %%fs:(%%ebx)\n\t" - "clflush %%fs:64(%%ebx)\n\t" - - "clflush %%fs:-128(%%ecx)\n\t" - "clflush %%fs:-64(%%ecx)\n\t" - "clflush %%fs:(%%ecx)\n\t" - "clflush %%fs:64(%%ecx)\n\t" - - "clflush %%fs:-128(%%edx)\n\t" - "clflush %%fs:-64(%%edx)\n\t" - - :: "b" (addr_lo+128+8*64), "c" (addr_lo+128+12*64), - "d" (addr_lo +128+16*64), "a"(addr_lo+128), - "D"(addr_lo+128+4*64) - ); -} - - -static void ReadL18TestPattern(u32 addr_lo) -{ - // set fs and use fs prefix to access the mem - __asm__ volatile ( - "outb %%al, $0xed\n\t" /* _EXECFENCE */ - "movl %%fs:-128(%%esi), %%eax\n\t" //TestAddr cache line - "movl %%fs:-64(%%esi), %%eax\n\t" //+1 - "movl %%fs:(%%esi), %%eax\n\t" //+2 - "movl %%fs:64(%%esi), %%eax\n\t" //+3 - - "movl %%fs:-128(%%edi), %%eax\n\t" //+4 - "movl %%fs:-64(%%edi), %%eax\n\t" //+5 - "movl %%fs:(%%edi), %%eax\n\t" //+6 - "movl %%fs:64(%%edi), %%eax\n\t" //+7 - - "movl %%fs:-128(%%ebx), %%eax\n\t" //+8 - "movl %%fs:-64(%%ebx), %%eax\n\t" //+9 - "movl %%fs:(%%ebx), %%eax\n\t" //+10 - "movl %%fs:64(%%ebx), %%eax\n\t" //+11 - - "movl %%fs:-128(%%ecx), %%eax\n\t" //+12 - "movl %%fs:-64(%%ecx), %%eax\n\t" //+13 - "movl %%fs:(%%ecx), %%eax\n\t" //+14 - "movl %%fs:64(%%ecx), %%eax\n\t" //+15 - - "movl %%fs:-128(%%edx), %%eax\n\t" //+16 - "movl %%fs:-64(%%edx), %%eax\n\t" //+17 - "mfence\n\t" - - :: "a"(0), "b" (addr_lo+128+8*64), "c" (addr_lo+128+12*64), - "d" (addr_lo +128+16*64), "S"(addr_lo+128), - "D"(addr_lo+128+4*64) - ); - -} - - -static void ReadL9TestPattern(u32 addr_lo) -{ - - // set fs and use fs prefix to access the mem - __asm__ volatile ( - "outb %%al, $0xed\n\t" /* _EXECFENCE */ - - "movl %%fs:-128(%%ecx), %%eax\n\t" //TestAddr cache line - "movl %%fs:-64(%%ecx), %%eax\n\t" //+1 - "movl %%fs:(%%ecx), %%eax\n\t" //+2 - "movl %%fs:64(%%ecx), %%eax\n\t" //+3 - - "movl %%fs:-128(%%edx), %%eax\n\t" //+4 - "movl %%fs:-64(%%edx), %%eax\n\t" //+5 - "movl %%fs:(%%edx), %%eax\n\t" //+6 - "movl %%fs:64(%%edx), %%eax\n\t" //+7 - - "movl %%fs:-128(%%ebx), %%eax\n\t" //+8 - "mfence\n\t" - - :: "a"(0), "b" (addr_lo+128+8*64), "c"(addr_lo+128), - "d"(addr_lo+128+4*64) - ); - -} - - -static void ReadMaxRdLat1CLTestPattern_D(u32 addr) -{ - SetUpperFSbase(addr); - - __asm__ volatile ( - "outb %%al, $0xed\n\t" /* _EXECFENCE */ - "movl %%fs:-128(%%esi), %%eax\n\t" //TestAddr cache line - "movl %%fs:-64(%%esi), %%eax\n\t" //+1 - "movl %%fs:(%%esi), %%eax\n\t" //+2 - "mfence\n\t" - :: "a"(0), "S"((addr<<8)+128) - ); - -} - - -static void WriteMaxRdLat1CLTestPattern_D(u32 buf, u32 addr) -{ - SetUpperFSbase(addr); - - __asm__ volatile ( - "outb %%al, $0xed\n\t" /* _EXECFENCE */ - "1:\n\t" - "movdqa (%3), %%xmm0\n\t" - "movntdq %%xmm0, %%fs:(%0)\n\t" /* xmm0 is 128 bit */ - "addl %1, %0\n\t" - "addl %1, %3\n\t" - "loop 1b\n\t" - "mfence\n\t" - - :: "a" (addr<<8), "d" (16), "c" (3 * 4), "b"(buf) - ); -} - - -static void FlushMaxRdLatTestPattern_D(u32 addr) -{ - /* Flush a pattern of 72 bit times (per DQ) from cache. - * This procedure is used to ensure cache miss on the next read training. - */ - - SetUpperFSbase(addr); - - __asm__ volatile ( - "outb %%al, $0xed\n\t" /* _EXECFENCE */ - "clflush %%fs:-128(%%esi)\n\t" //TestAddr cache line - "clflush %%fs:-64(%%esi)\n\t" //+1 - "clflush %%fs:(%%esi)\n\t" //+2 - "mfence\n\t" - - :: "S"((addr<<8)+128) - ); -} - - -static u32 stream_to_int(u8 const *p) -{ - int i; - u32 val; - u32 valx; - - val = 0; - - for (i = 3; i >= 0; i--) { - val <<= 8; - valx = *(p+i); - val |= valx; - } - - return val; -} - - -#ifdef UNUSED_CODE -static void oemSet_NB32(u32 addr, u32 val, u8 *valid) -{ -} - - -static u32 oemGet_NB32(u32 addr, u8 *valid) -{ - *valid = 0; - return 0xffffffff; -} #endif - - -static u8 oemNodePresent_D(u8 Node, u8 *ret) -{ - *ret = 0; - return 0; -} diff --git a/src/northbridge/amd/amdmct/mct/mctardk3.c b/src/northbridge/amd/amdmct/mct/mctardk3.c index e290333..fe57d31 100644 --- a/src/northbridge/amd/amdmct/mct/mctardk3.c +++ b/src/northbridge/amd/amdmct/mct/mctardk3.c @@ -13,6 +13,8 @@ * GNU General Public License for more details. */
+#include <inttypes.h> +#include "mct_d.h"
static void Get_ChannelPS_Cfg0_D(u8 MAAdimms, u8 Speed, u8 MAAload, u8 DATAAload, u32 *AddrTmgCTL, u32 *ODC_CTL); diff --git a/src/northbridge/amd/amdmct/mct/mctchi_d.c b/src/northbridge/amd/amdmct/mct/mctchi_d.c index 705bd91..d2acc15 100644 --- a/src/northbridge/amd/amdmct/mct/mctchi_d.c +++ b/src/northbridge/amd/amdmct/mct/mctchi_d.c @@ -13,7 +13,7 @@ * GNU General Public License for more details. */
- +#include "mct_d.h"
void InterleaveChannels_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) diff --git a/src/northbridge/amd/amdmct/mct/mctcsi_d.c b/src/northbridge/amd/amdmct/mct/mctcsi_d.c index 1c86239..6a19788 100644 --- a/src/northbridge/amd/amdmct/mct/mctcsi_d.c +++ b/src/northbridge/amd/amdmct/mct/mctcsi_d.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */
+#include "mct_d.h"
/* Low swap bit vs bank size encoding (physical, not logical address bit) * ;To calculate the number by hand, add the number of Bank address bits diff --git a/src/northbridge/amd/amdmct/mct/mctdqs_d.c b/src/northbridge/amd/amdmct/mct/mctdqs_d.c index 6363162..b92f33a 100644 --- a/src/northbridge/amd/amdmct/mct/mctdqs_d.c +++ b/src/northbridge/amd/amdmct/mct/mctdqs_d.c @@ -13,6 +13,8 @@ * GNU General Public License for more details. */
+#include "mct_d.h" +#include <cpu/amd/mtrr.h>
static void CalcEccDQSPos_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u16 like, @@ -38,30 +40,20 @@ static u8 CompareDQSTestPattern_D(struct MCTStatStruc *pMCTstat, u32 addr_lo); static void FlushDQSTestPattern_D(struct DCTStatStruc *pDCTstat, u32 addr_lo); -static void SetTargetWTIO_D(u32 TestAddr); -static void ResetTargetWTIO_D(void); static void ReadDQSTestPattern_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u32 TestAddr_lo); -void ResetDCTWrPtr_D(u32 dev, u32 index_reg, u32 index); -u8 mct_DisableDimmEccEn_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat); static void mct_SetDQSDelayCSR_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 ChipSel); static void mct_SetDQSDelayAllCSR_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 cs_start); -u32 mct_GetMCTSysAddr_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 Channel, - u8 receiver, u8 *valid); static void SetupDqsPattern_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u32 *buffer);
-#define DQS_TRAIN_DEBUG 0 - -static void print_debug_dqs(const char *str, u32 val, u8 level) +void print_debug_dqs(const char *str, u32 val, u8 level) { #if DQS_TRAIN_DEBUG > 0 if (DQS_TRAIN_DEBUG >= level) { @@ -70,7 +62,7 @@ static void print_debug_dqs(const char *str, u32 val, u8 level) #endif }
-static void print_debug_dqs_pair(const char *str, u32 val, const char *str2, u32 val2, u8 level) +void print_debug_dqs_pair(const char *str, u32 val, const char *str2, u32 val2, u8 level) { #if DQS_TRAIN_DEBUG > 0 if (DQS_TRAIN_DEBUG >= level) { @@ -653,7 +645,7 @@ static void TrainWriteDQS_D(struct MCTStatStruc *pMCTstat, }
-static void proc_IOCLFLUSH_D(u32 addr_hi) +void proc_IOCLFLUSH_D(u32 addr_hi) { SetTargetWTIO_D(addr_hi); proc_CLFLUSH(addr_hi); @@ -820,7 +812,7 @@ static void FlushDQSTestPattern_D(struct DCTStatStruc *pDCTstat, } }
-static void SetTargetWTIO_D(u32 TestAddr) +void SetTargetWTIO_D(u32 TestAddr) { u32 lo, hi; hi = TestAddr >> 24; @@ -832,7 +824,7 @@ static void SetTargetWTIO_D(u32 TestAddr) }
-static void ResetTargetWTIO_D(void) +void ResetTargetWTIO_D(void) { u32 lo, hi;
@@ -1173,7 +1165,7 @@ exitGetAddr: }
-static void mct_Write1LTestPattern_D(struct MCTStatStruc *pMCTstat, +void mct_Write1LTestPattern_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u32 TestAddr, u8 pattern) { diff --git a/src/northbridge/amd/amdmct/mct/mcthdi.c b/src/northbridge/amd/amdmct/mct/mcthdi.c index d9d87af..b67282e 100644 --- a/src/northbridge/amd/amdmct/mct/mcthdi.c +++ b/src/northbridge/amd/amdmct/mct/mcthdi.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */
+#include "mct_d.h"
void mct_DramInit_Hw_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 dct) diff --git a/src/northbridge/amd/amdmct/mct/mctndi_d.c b/src/northbridge/amd/amdmct/mct/mctndi_d.c index 389d56b..3f09f4a 100644 --- a/src/northbridge/amd/amdmct/mct/mctndi_d.c +++ b/src/northbridge/amd/amdmct/mct/mctndi_d.c @@ -14,7 +14,7 @@ * GNU General Public License for more details. */
- +#include "mct_d.h"
void InterleaveNodes_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) diff --git a/src/northbridge/amd/amdmct/mct/mctpro_d.c b/src/northbridge/amd/amdmct/mct/mctpro_d.c index 6802a76..0acb6f4 100644 --- a/src/northbridge/amd/amdmct/mct/mctpro_d.c +++ b/src/northbridge/amd/amdmct/mct/mctpro_d.c @@ -14,6 +14,8 @@ * GNU General Public License for more details. */
+#include "mct_d.h" + void EarlySampleSupport_D(void) { } @@ -321,7 +323,7 @@ static u8 mct_AdjustDelay_D(struct DCTStatStruc *pDCTstat, u8 dly) } #endif
-static u8 mct_checkFenceHoleAdjust_D(struct MCTStatStruc *pMCTstat, +u8 mct_checkFenceHoleAdjust_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 DQSDelay, u8 ChipSel, u8 *result) { @@ -365,12 +367,6 @@ u8 mct_AdjustDQSPosDelay_D(struct DCTStatStruc *pDCTstat, u8 dly)
}
-static void beforeInterleaveChannels_D(struct DCTStatStruc *pDCTstatA, u8 *enabled) { - - if (pDCTstatA->LogicalCPUID & (AMD_DR_Ax)) - *enabled = 0; -} - #ifdef UNUSED_CODE static u8 mctDoAxRdPtrInit_D(struct DCTStatStruc *pDCTstat, u8 *Rdtr) { @@ -394,3 +390,8 @@ void mct_AdjustScrub_D(struct DCTStatStruc *pDCTstat, u16 *scrub_request) { pDCTstat->ErrStatus |= 1 << SB_DCBKScrubDis; } } + +void beforeInterleaveChannels_D(struct DCTStatStruc *pDCTstatA, u8 *enabled) { + if (pDCTstatA->LogicalCPUID & (AMD_DR_Ax)) + *enabled = 0; +} diff --git a/src/northbridge/amd/amdmct/mct/mctsrc.c b/src/northbridge/amd/amdmct/mct/mctsrc.c index a87cea8..58a6d9f 100644 --- a/src/northbridge/amd/amdmct/mct/mctsrc.c +++ b/src/northbridge/amd/amdmct/mct/mctsrc.c @@ -14,6 +14,8 @@ * GNU General Public License for more details. */
+#include "mct_d.h" + /****************************************************************************** Description: Receiver En and DQS Timing Training feature for DDR 2 MCT ******************************************************************************/ @@ -46,19 +48,19 @@ static void mct_DisableDQSRcvEn_D(struct DCTStatStruc *pDCTstat);
/* Warning: These must be located so they do not cross a logical 16-bit segment boundary! */ -static const u32 TestPattern0_D[] = { +const u32 TestPattern0_D[] = { 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, }; -static const u32 TestPattern1_D[] = { +const u32 TestPattern1_D[] = { 0x55555555, 0x55555555, 0x55555555, 0x55555555, 0x55555555, 0x55555555, 0x55555555, 0x55555555, 0x55555555, 0x55555555, 0x55555555, 0x55555555, 0x55555555, 0x55555555, 0x55555555, 0x55555555, }; -static const u32 TestPattern2_D[] = { +const u32 TestPattern2_D[] = { 0x12345678, 0x87654321, 0x23456789, 0x98765432, 0x59385824, 0x30496724, 0x24490795, 0x99938733, 0x40385642, 0x38465245, 0x29432163, 0x05067894, diff --git a/src/northbridge/amd/amdmct/mct/mctsrc1p.c b/src/northbridge/amd/amdmct/mct/mctsrc1p.c index bfd103b..31a3a5d 100644 --- a/src/northbridge/amd/amdmct/mct/mctsrc1p.c +++ b/src/northbridge/amd/amdmct/mct/mctsrc1p.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */
+#include "mct_d.h"
u8 mct_checkNumberOfDqsRcvEn_1Pass(u8 pass) { diff --git a/src/northbridge/amd/amdmct/mct/mcttmrl.c b/src/northbridge/amd/amdmct/mct/mcttmrl.c index 1095259..d38ae93 100644 --- a/src/northbridge/amd/amdmct/mct/mcttmrl.c +++ b/src/northbridge/amd/amdmct/mct/mcttmrl.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */
+#include "mct_d.h"
/* * Description: Max Read Latency Training feature for DDR 2 MCT diff --git a/src/northbridge/amd/amdmct/wrappers/mcti.h b/src/northbridge/amd/amdmct/wrappers/mcti.h index 5eaff2c..4f607a0 100644 --- a/src/northbridge/amd/amdmct/wrappers/mcti.h +++ b/src/northbridge/amd/amdmct/wrappers/mcti.h @@ -3,6 +3,7 @@ * * Copyright (C) 2007 Advanced Micro Devices, Inc. * Copyright (C) 2015 Timothy Pearson tpearson@raptorengineeringinc.com, Raptor Engineering + * Copyright (C) 2016 Damien Zammit damien@zamaudio.com * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -14,6 +15,15 @@ * GNU General Public License for more details. */
+#ifndef MCTI_H +#define MCTI_H + +#include <inttypes.h> +#include <stdlib.h> +#include <pc80/mc146818rtc.h> + +struct DCTStatStruc; +struct MCTStatStruc;
#define SERVER 0 #define DESKTOP 1 @@ -22,7 +32,6 @@ #define REV_DR 1 #define REV_FDR 2
- /*---------------------------------------------------------------------------- COMMENT OUT ALL BUT 1 ----------------------------------------------------------------------------*/ @@ -77,3 +86,68 @@ UPDATE AS NEEDED
#define MCT_TRNG_KEEPOUT_START 0x00000C00 #define MCT_TRNG_KEEPOUT_END 0x00000CFF + +#define NVRAM_DDR2_800 0 +#define NVRAM_DDR2_667 1 +#define NVRAM_DDR2_533 2 +#define NVRAM_DDR2_400 3 + +#define NVRAM_DDR3_1600 0 +#define NVRAM_DDR3_1333 1 +#define NVRAM_DDR3_1066 2 +#define NVRAM_DDR3_800 3 + +/* The recommended maximum GFX Upper Memory Area + * size is 256M, however, to be on the safe side + * move TOM down by 512M. + */ +#define MAXIMUM_GFXUMA_SIZE 0x20000000 + +/* Do not allow less than 16M of DRAM in 32-bit space. + * This number is not hardware constrained and can be + * changed as needed. + */ +#define MINIMUM_DRAM_BELOW_4G 0x1000000 + +static const uint16_t ddr2_limits[4] = {400, 333, 266, 200}; +static const uint16_t ddr3_limits[16] = {933, 800, 666, 533, 400, 333, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; + +#if (CONFIG_DIMM_SUPPORT & 0x000F) == 0x0005 // AMD_FAM10_DDR3 + #include <northbridge/amd/amdmct/mct_ddr3/mct_d.h> +#else + #include <northbridge/amd/amdmct/mct/mct_d.h> +#endif + +#if IS_ENABLED(CONFIG_DIMM_DDR2) +void mctSaveDQSSigTmg_D(void); +void mctGetDQSSigTmg_D(void); +u8 mctSetNodeBoundary_D(void); +#endif +u16 mctGet_NVbits(u8 index); +void mctHookAfterDIMMpre(void); +void mctGet_MaxLoadFreq(struct DCTStatStruc *pDCTstat); +void mctAdjustAutoCycTmg_D(void); +void mctHookAfterAutoCycTmg(void); +void mctGetCS_ExcludeMap(void); +void mctHookBeforeECC(void); +void mctHookAfterECC(void); +void mctHookAfterAutoCfg(void); +void mctHookAfterPSCfg(void); +void mctHookAfterHTMap(void); +void mctHookAfterCPU(void); +void mctInitMemGPIOs_A_D(void); +void mctNodeIDDebugPort_D(void); +void mctWarmReset_D(void); +void mctHookBeforeDramInit(void); +void mctHookAfterDramInit(void); +void mctHookBeforeAnyTraining(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); +void mctHookAfterAnyTraining(void); +uint64_t mctGetLogicalCPUID_D(u8 node); + +#if (CONFIG_DIMM_SUPPORT & 0x000F) == 0x0005 /* AMD_FAM10_DDR3 */ +void vErratum372(struct DCTStatStruc *pDCTstat); +void vErratum414(struct DCTStatStruc *pDCTstat); +u32 mct_AdjustSPDTimings(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA, u32 val); +#endif + +#endif diff --git a/src/northbridge/amd/amdmct/wrappers/mcti_d.c b/src/northbridge/amd/amdmct/wrappers/mcti_d.c index 9cb981a..1cf115f 100644 --- a/src/northbridge/amd/amdmct/wrappers/mcti_d.c +++ b/src/northbridge/amd/amdmct/wrappers/mcti_d.c @@ -16,6 +16,7 @@
/* Call-backs */ #include <delay.h> +#include "mcti.h"
#define NVRAM_DDR2_800 0 #define NVRAM_DDR2_667 1 @@ -39,10 +40,7 @@ */ #define MINIMUM_DRAM_BELOW_4G 0x1000000
-static const uint16_t ddr2_limits[4] = {400, 333, 266, 200}; -static const uint16_t ddr3_limits[16] = {933, 800, 666, 533, 400, 333, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; - -static u16 mctGet_NVbits(u8 index) +u16 mctGet_NVbits(u8 index) { u16 val = 0; int nvram; @@ -312,12 +310,12 @@ static u16 mctGet_NVbits(u8 index) }
-static void mctHookAfterDIMMpre(void) +void mctHookAfterDIMMpre(void) { }
-static void mctGet_MaxLoadFreq(struct DCTStatStruc *pDCTstat) +void mctGet_MaxLoadFreq(struct DCTStatStruc *pDCTstat) { pDCTstat->PresetmaxFreq = mctGet_NVbits(NV_MAX_MEMCLK);
@@ -370,111 +368,92 @@ static void mctGet_MaxLoadFreq(struct DCTStatStruc *pDCTstat) pDCTstat->PresetmaxFreq = mct_MaxLoadFreq(max(ch1_count, ch2_count), max(highest_rank_count[0], highest_rank_count[1]), (ch1_registered || ch2_registered), (ch1_voltage | ch2_voltage), pDCTstat->PresetmaxFreq); }
-#ifdef UNUSED_CODE -static void mctAdjustAutoCycTmg(void) +void mctAdjustAutoCycTmg_D(void) { } -#endif
-static void mctAdjustAutoCycTmg_D(void) +void mctHookAfterAutoCycTmg(void) { }
-static void mctHookAfterAutoCycTmg(void) +void mctGetCS_ExcludeMap(void) { }
-static void mctGetCS_ExcludeMap(void) +void mctHookAfterAutoCfg(void) { }
-static void mctHookAfterAutoCfg(void) +void mctHookAfterPSCfg(void) { }
-static void mctHookAfterPSCfg(void) +void mctHookAfterHTMap(void) { }
-static void mctHookAfterHTMap(void) -{ -} - - -static void mctHookAfterCPU(void) +void mctHookAfterCPU(void) { }
#if IS_ENABLED(CONFIG_DIMM_DDR2) -static void mctSaveDQSSigTmg_D(void) +void mctSaveDQSSigTmg_D(void) { } -#endif -
-#if IS_ENABLED(CONFIG_DIMM_DDR2) -static void mctGetDQSSigTmg_D(void) +void mctGetDQSSigTmg_D(void) { } #endif
- -static void mctHookBeforeECC(void) +void mctHookBeforeECC(void) { }
- -static void mctHookAfterECC(void) +void mctHookAfterECC(void) { }
#ifdef UNUSED_CODE -static void mctInitMemGPIOs_A(void) +void mctInitMemGPIOs_A(void) { } #endif
-static void mctInitMemGPIOs_A_D(void) +void mctInitMemGPIOs_A_D(void) { }
-static void mctNodeIDDebugPort_D(void) +void mctNodeIDDebugPort_D(void) { }
-#ifdef UNUSED_CODE -static void mctWarmReset(void) -{ -} -#endif - - -static void mctWarmReset_D(void) +void mctWarmReset_D(void) { }
-static void mctHookBeforeDramInit(void) +void mctHookBeforeDramInit(void) { }
-static void mctHookAfterDramInit(void) +void mctHookAfterDramInit(void) { }
#if (CONFIG_DIMM_SUPPORT & 0x000F) == 0x0005 /* AMD_FAM10_DDR3 */ -static void vErratum372(struct DCTStatStruc *pDCTstat) +void vErratum372(struct DCTStatStruc *pDCTstat) { msr_t msr = rdmsr(NB_CFG_MSR);
@@ -489,7 +468,7 @@ static void vErratum372(struct DCTStatStruc *pDCTstat) } }
-static void vErratum414(struct DCTStatStruc *pDCTstat) +void vErratum414(struct DCTStatStruc *pDCTstat) { int dct = 0; for (; dct < 2 ; dct++) { @@ -505,7 +484,7 @@ static void vErratum414(struct DCTStatStruc *pDCTstat) #endif
-static void mctHookBeforeAnyTraining(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) +void mctHookBeforeAnyTraining(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) { #if (CONFIG_DIMM_SUPPORT & 0x000F) == 0x0005 /* AMD_FAM10_DDR3 */ /* FIXME : as of 25.6.2010 errata 350 and 372 should apply to ((RB|BL|DA)-C[23])|(HY-D[01])|(PH-E0) but I don't find constants for all of them */ @@ -517,7 +496,7 @@ static void mctHookBeforeAnyTraining(struct MCTStatStruc *pMCTstat, struct DCTSt }
#if (CONFIG_DIMM_SUPPORT & 0x000F) == 0x0005 /* AMD_FAM10_DDR3 */ -static u32 mct_AdjustSPDTimings(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA, u32 val) +u32 mct_AdjustSPDTimings(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA, u32 val) { if (pDCTstatA->LogicalCPUID & AMD_DR_Bx) { if (pDCTstatA->Status & (1 << SB_Registered)) { @@ -528,17 +507,17 @@ static u32 mct_AdjustSPDTimings(struct MCTStatStruc *pMCTstat, struct DCTStatStr } #endif
-static void mctHookAfterAnyTraining(void) +void mctHookAfterAnyTraining(void) { }
-static uint64_t mctGetLogicalCPUID_D(u8 node) +uint64_t mctGetLogicalCPUID_D(u8 node) { return mctGetLogicalCPUID(node); }
#if (CONFIG_DIMM_SUPPORT & 0x000F)!=0x0005 /* not needed for AMD_FAM10_DDR3 */ -static u8 mctSetNodeBoundary_D(void) +u8 mctSetNodeBoundary_D(void) { return 0; }
-
Damien Zammit