Change in coreboot[master]: mb/google/dedede: Add weak pull-up for EC_AP_PWR_BTN_ODL gpio
Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39852 )
Change subject: mb/google/dedede: Add weak pull-up for EC_AP_PWR_BTN_ODL gpio ......................................................................
mb/google/dedede: Add weak pull-up for EC_AP_PWR_BTN_ODL gpio
According to the EDS, EC_AP_PWR_BTN_ODL has a default internal pull-up of 20K. Retain it during the GPIO pad configuration.
BUG=b:150985246 TEST=Boot the mainboard.
Change-Id: I042ba70f78fca1a5b9eda30029df97b3f8e65656 Signed-off-by: Karthikeyan Ramasubramanian kramasub@google.com --- M src/mainboard/google/dedede/variants/baseboard/gpio.c 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/39852/1
diff --git a/src/mainboard/google/dedede/variants/baseboard/gpio.c b/src/mainboard/google/dedede/variants/baseboard/gpio.c index a012737..89683bd 100644 --- a/src/mainboard/google/dedede/variants/baseboard/gpio.c +++ b/src/mainboard/google/dedede/variants/baseboard/gpio.c @@ -372,7 +372,7 @@ /* GPD2 : EC_AP_WAKE_ODL */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* GPD3 : EC_AP_PWR_BTN_ODL */ - PAD_CFG_NF(GPD3, NONE, DEEP, NF1), + PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), /* GPD4 : AP_SLP_S3_L */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* GPD5 : AP_SLP_S4_L */
Justin TerAvest has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39852 )
Change subject: mb/google/dedede: Add weak pull-up for EC_AP_PWR_BTN_ODL gpio ......................................................................
Patch Set 1: Code-Review+2
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39852 )
Change subject: mb/google/dedede: Add weak pull-up for EC_AP_PWR_BTN_ODL gpio ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39852/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39852/1//COMMIT_MSG@13 PS1, Line 13: Boot the mainboard. Did this solve the issue that you were running into?
Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39852 )
Change subject: mb/google/dedede: Add weak pull-up for EC_AP_PWR_BTN_ODL gpio ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39852/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39852/1//COMMIT_MSG@13 PS1, Line 13: Boot the mainboard.
Did this solve the issue that you were running into?
Not yet. The SoC went from G3 to S0 with the change. But stayed there for a very short duration before going all the way back to G3. So still triaging the original issue.
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39852 )
Change subject: mb/google/dedede: Add weak pull-up for EC_AP_PWR_BTN_ODL gpio ......................................................................
Patch Set 1: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/39852/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39852/1//COMMIT_MSG@13 PS1, Line 13: Boot the mainboard.
Not yet. The SoC went from G3 to S0 with the change. […]
Okay. I think this change is still needed independent of that issue.
Furquan Shaikh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39852 )
Change subject: mb/google/dedede: Add weak pull-up for EC_AP_PWR_BTN_ODL gpio ......................................................................
mb/google/dedede: Add weak pull-up for EC_AP_PWR_BTN_ODL gpio
According to the EDS, EC_AP_PWR_BTN_ODL has a default internal pull-up of 20K. Retain it during the GPIO pad configuration.
BUG=b:150985246 TEST=Boot the mainboard.
Change-Id: I042ba70f78fca1a5b9eda30029df97b3f8e65656 Signed-off-by: Karthikeyan Ramasubramanian kramasub@google.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/39852 Reviewed-by: Justin TerAvest teravest@chromium.org Reviewed-by: Furquan Shaikh furquan@google.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/google/dedede/variants/baseboard/gpio.c 1 file changed, 1 insertion(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Justin TerAvest: Looks good to me, approved
diff --git a/src/mainboard/google/dedede/variants/baseboard/gpio.c b/src/mainboard/google/dedede/variants/baseboard/gpio.c index a012737..89683bd 100644 --- a/src/mainboard/google/dedede/variants/baseboard/gpio.c +++ b/src/mainboard/google/dedede/variants/baseboard/gpio.c @@ -372,7 +372,7 @@ /* GPD2 : EC_AP_WAKE_ODL */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* GPD3 : EC_AP_PWR_BTN_ODL */ - PAD_CFG_NF(GPD3, NONE, DEEP, NF1), + PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), /* GPD4 : AP_SLP_S3_L */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* GPD5 : AP_SLP_S4_L */
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Furquan Shaikh (Code Review) -
Justin TerAvest (Code Review)
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Karthik Ramasubramanian (Code Review)