Change in coreboot[master]: nb/intel/sandybridge: Remove wrong and nonsense condition

[Angel Pons (Code Review)]

Attention is currently required from: Nico Huber.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49318 )

Change subject: nb/intel/sandybridge: Remove wrong and nonsense condition
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Patch Set 1: -Code-Review

(1 comment)

Commit Message:

https://review.coreboot.org/c/coreboot/+/49318/comment/76e618e7_df51206f 
PS1, Line 10: comment that says the opposite
> Argh, let me revise it again...

# Programming Command, Control, Clock

CMD is a single setting, shared across all ranks.
CTL is per DIMM, and we use the average for dual-rank DIMMs.
CLK is per rank, and needs the extra `pi_code_offset`. CB:49319

If some ranks have a negative `pi_coding` value, determine the most negative `pi_coding` value among all populated ranks, save it as `min_pi_code`, then program:

* CMD = -min_pi_code;
 * CTL = -min_pi_code + pi_coding;
 * CLK = -min_pi_code + pi_coding + pi_code_offset;

If all `pi_coding` values are positive, `min_pi_code` is zero:

* CMD = 0;
 * CTL = pi_coding;
 * CLK = pi_coding + pi_code_offset;

# Data training fix (what CB:49067 does)

After adjusting CCC (CMD, CTL, CLK), the data training result needs to be corrected, per rank. This correction involves incrementing the TxDQ, TxDQS, RcvEn timings by `-min_pi_code + pi_coding` (the theoretical value for CTL).

Note that the rank's I/O and roundtrip latencies need to be adjusted accordingly when changing the RcvEn timings. This involves five steps:

1. Compute the difference between the smallest and largest RcvEn logic delays of the current rank. Let's call it `delta_prev`.

2. For all lanes of the current rank, adjust the RcvEn timings as required.

3. Find the smallest RcvEn logic delay (whole number of QCLKs) among all lanes (of the current rank). Then, decrement the I/O latency and RcvEn of all lanes of the current rank by this amount of QCLKs.

4. Compute the difference between the smallest and largest RcvEn logic delays of the current rank, again. Let's call it `delta_post`.

5. If `delta_post < delta_prev`, decrease the current rank's I/O and roundtrip latencies by one. Else if `delta_post > delta_prev`, increase the current rank's I/O and roundtrip latencies by one.