Change in coreboot[master]: soc/intel/alderlake: Add option to make MRC log silent

[Subrata Banik (Code Review)]

Attention is currently required from:  Felix Singer, Nico Huber, Paul Menzel, Tim Wawrzynczak, Arthur Heymans, Nick Vaccaro, Andrey Petrov, Patrick Rudolph.
Hello  Felix Singer, build bot (Jenkins), Nico Huber, Tim Wawrzynczak, Angel Pons, Arthur Heymans, Nick Vaccaro, Tim Wawrzynczak, Andrey Petrov, Patrick Rudolph, EricR Lai,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/60441

to look at the new patch set (#6).

Change subject: soc/intel/alderlake: Add option to make MRC log silent
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soc/intel/alderlake: Add option to make MRC log silent

Typically, FSP-M aka MRC debug log level defaults to `3`
meaning prints all `Load, Error, Warnings & Info` messages.

Sometimes it's too much information to parse even when users
aren't required to have such detailed information hence,
implement `fsp_map_console_log_level()` that maps coreboot console
log level to FSP-M debug log level and suppress verbose MRC debug
messages unless caller selects `HAVE_DEBUG_RAM_SETUP` config and
then the user can enable `DEBUG_RAM_SETUP`.

TEST=FSP-M debug log suggested default `SerialDebugMrcLevel`
UPD value is `2`. While this patch selects `HAVE_DEBUG_RAM_SETUP`
and user to select `DEBUG_RAM_SETUP` config to override
`SerialDebugMrcLevel` UPD value to '5' aka verbose.

Signed-off-by: Subrata Banik 
Change-Id: Iea3b32feca0893a83fdf700798b0883d26ccc718
---
M src/soc/intel/alderlake/Kconfig
M src/soc/intel/alderlake/romstage/fsp_params.c
2 files changed, 4 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/60441/6