Change in coreboot[master]: mb/siemens/{mc_apl1,...,mc_apl6}: Configure FSP-S UPDs

[Mario Scheithauer (Code Review)]

Attention is currently required from: Paul Menzel, Mario Scheithauer.
Hello build bot (Jenkins), Paul Menzel, Uwe Poeche, siemens-bot, Werner Zeh,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/49462

to look at the new patch set (#3).

Change subject: mb/siemens/{mc_apl1,...,mc_apl6}: Configure FSP-S UPDs
......................................................................

mb/siemens/{mc_apl1,...,mc_apl6}: Configure FSP-S UPDs

Until now some FSP-S parameters were configured for Siemens APL
mainboards via the Binary Configuration Tool (BCT). For simplification,
the original APL FSP binary should now be used. For this purpose, the
corresponding FSP-S parameters are set via devicetree, respectively via
mainboard_silicon_init_params accordingly.

The following parameters are affected:
- Disable CPU power states (C-states)
- Set lowest Max Pkg Cstate - PkgC0C1
- Disable PCIe Hot Plug for all enabled RPs
- Disable PCIe Transmitter Half Swing for all RPs
- Disable PCIe Active State Power Management (ASPM) for all RPs
- Disable PCIe L1 Substates for all RPs

TEST:
- Compare old with new coreboot log on mc_apl5, found no differences
- Boot Linux v4.4 and check output of 'lspci'

Change-Id: I5af627defd6426140cc9a74bb18db400a8971d72
Signed-off-by: Mario Scheithauer 
---
M src/mainboard/siemens/mc_apl1/mainboard.c
M src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb
M src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb
M src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb
M src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb
M src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb
M src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb
7 files changed, 164 insertions(+), 86 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/49462/3