[S] Change in coreboot[master]: soc/mediatek/mt8188: Enable mfgpll properly and fix SPMI muxes

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/67355 )

Change subject: soc/mediatek/mt8188: Enable mfgpll properly and fix SPMI muxes
......................................................................

soc/mediatek/mt8188: Enable mfgpll properly and fix SPMI muxes

Some of the pll settings are incorrect, which cause problems in GPU
after booting into kernel.

- MFGPLL opp_ck_en bit isn't located at MFGPLL_CON1, so we need to fix
  it to enable MFGPLL properly.
- Switch SPMI clock muxes to 260M to avoid kernel hang while probing
  SPMI kernel driver.

TEST=GPU bringup correctly.
BUG=b:233720142

Signed-off-by: Johnson Wang 
Change-Id: I971109a5f72e3307899daaf5a5f26022124b559b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67355
Reviewed-by: Yu-Ping Wu 
Tested-by: build bot (Jenkins) 
Reviewed-by: Yidi Lin 
---
M src/soc/mediatek/mt8188/pll.c
1 file changed, 28 insertions(+), 4 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Yu-Ping Wu: Looks good to me, approved
  Yidi Lin: Looks good to me, but someone else must approve

diff --git a/src/soc/mediatek/mt8188/pll.c b/src/soc/mediatek/mt8188/pll.c
index 22f8a04..f7ce86b 100644
--- a/src/soc/mediatek/mt8188/pll.c
+++ b/src/soc/mediatek/mt8188/pll.c
@@ -319,9 +319,9 @@
    { .id = TOP_VDEC_SEL, .sel = 1 },			/* 1: mainpll_d5_d2 */
    { .id = TOP_PWM_SEL, .sel = 3 },			/* 3: univpll_d6_d4 */
    { .id = TOP_MCUPM_SEL, .sel = 1 },			/* 1: mainpll_d6_d2 */
-	{ .id = TOP_SPMI_P_MST_SEL, .sel = 7 },			/* 7: mainpll_d7_d8 */
+	{ .id = TOP_SPMI_P_MST_SEL, .sel = 3 },			/* 7: mainpll_d7_d8 */
    /* CLK_CFG_14 */
-	{ .id = TOP_SPMI_M_MST_SEL, .sel = 7 },			/* 7: mainpll_d7_d8 */
+	{ .id = TOP_SPMI_M_MST_SEL, .sel = 3 },			/* 7: mainpll_d7_d8 */
    { .id = TOP_DVFSRC_SEL, .sel = 0 },			/* 0: clk26m */
    { .id = TOP_TL_SEL, .sel = 2 },				/* 2: mainpll_d4_d4 */
    { .id = TOP_AES_MSDCFDE_SEL, .sel = 5 },		/* 5: univpll_d6 */
@@ -522,8 +522,7 @@
    }

/* disable mfg_ck_en[20], enable mfg_opp_ck_en[2]  */
-	clrbits32(&mtk_apmixed->mfgpll_con0, 0x1 << 20);
-	setbits32(&mtk_apmixed->mfgpll_con1, 0x1 << 2);
+	clrsetbits32(&mtk_apmixed->mfgpll_con0, BIT(20), BIT(2));

/* xPLL Frequency Set */
    for (i = 0; i < ARRAY_SIZE(rates); i++)