Change in ...coreboot[master]: soc/intel/baytrail: Place the raminit in a common location

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32968

Change subject: soc/intel/baytrail: Place the raminit in a common location
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soc/intel/baytrail: Place the raminit in a common location

Change-Id: I784382d5c5251fac7039f991f8a6ad123a0b4f83
Signed-off-by: Arthur Heymans 
---
M src/mainboard/google/rambi/romstage.c
M src/soc/intel/baytrail/include/soc/romstage.h
M src/soc/intel/baytrail/romstage/romstage.c
3 files changed, 43 insertions(+), 52 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/32968/1

diff --git a/src/mainboard/google/rambi/romstage.c b/src/mainboard/google/rambi/romstage.c
index c244c83..93b6ba4 100644
--- a/src/mainboard/google/rambi/romstage.c
+++ b/src/mainboard/google/rambi/romstage.c
@@ -58,7 +58,7 @@
    return spd_ptr;
 }

-void mainboard_romstage_entry(struct mrc_params *mrc_params)
+void mainboard_pre_raminit(struct mrc_params *mrc_params)
 {
    void *spd_content;
    int dual_channel = 0;
@@ -80,6 +80,4 @@
    mrc_params->mainboard.dram_data[0] = spd_content;
    if (dual_channel)
    	mrc_params->mainboard.dram_data[1] = spd_content;
-
-	romstage_common(mrc_params);
 }
diff --git a/src/soc/intel/baytrail/include/soc/romstage.h b/src/soc/intel/baytrail/include/soc/romstage.h
index ea6298b..7730893 100644
--- a/src/soc/intel/baytrail/include/soc/romstage.h
+++ b/src/soc/intel/baytrail/include/soc/romstage.h
@@ -24,8 +24,7 @@
 #include <arch/cpu.h>
 #include <soc/mrc_wrapper.h>

-void mainboard_romstage_entry(struct mrc_params *mrc_params);
-void romstage_common(struct mrc_params *mrc_params);
+void mainboard_pre_raminit(struct mrc_params *mrc_params);
 void raminit(struct mrc_params *mp, int prev_sleep_state);
 void gfx_init(void);
 void tco_disable(void);
diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c
index 73991df..cc3bcd9 100644
--- a/src/soc/intel/baytrail/romstage/romstage.c
+++ b/src/soc/intel/baytrail/romstage/romstage.c
@@ -96,49 +96,6 @@
    write32(bcr, reg);
 }

-/* Entry from cache-as-ram.inc. */
-static void romstage_main(uint64_t tsc, uint32_t bist)
-{
-	struct mrc_params mrc_params;
-
-	/* Save initial timestamp from bootblock. */
-	timestamp_init(tsc);
-
-	/* Save romstage begin */
-	timestamp_add_now(TS_START_ROMSTAGE);
-
-	program_base_addresses();
-
-	tco_disable();
-
-	byt_config_com1_and_enable();
-
-	console_init();
-
-	spi_init();
-
-	set_max_freq();
-
-	punit_init();
-
-	gfx_init();
-
-	/* Call into mainboard. */
-	mainboard_romstage_entry(&mrc_params);
-
-	platform_enter_postcar();
-
-	/* We don't return here */
-}
-
-/* This wrapper enables easy transition towards C_ENVIRONMENT_BOOTBLOCK,
- * keeping changes in cache_as_ram.S easy to manage.
- */
-asmlinkage void bootblock_c_entry_bist(uint64_t base_timestamp, uint32_t bist)
-{
-	romstage_main(base_timestamp, bist);
-}
-
 static struct chipset_power_state power_state;

static void migrate_power_state(int is_recovery)
@@ -208,12 +165,38 @@
    return prev_sleep_state;
 }

-/* Entry from the mainboard. */
-void romstage_common(struct mrc_params *mrc_params)
+/* Entry from cache-as-ram.inc. */
+static void romstage_main(uint64_t tsc, uint32_t bist)
 {
+	struct mrc_params mrc_params;
    struct chipset_power_state *ps;
    int prev_sleep_state;

+	/* Save initial timestamp from bootblock. */
+	timestamp_init(tsc);
+
+	/* Save romstage begin */
+	timestamp_add_now(TS_START_ROMSTAGE);
+
+	program_base_addresses();
+
+	tco_disable();
+
+	byt_config_com1_and_enable();
+
+	console_init();
+
+	spi_init();
+
+	set_max_freq();
+
+	punit_init();
+
+	gfx_init();
+
+	/* Call into mainboard. */
+	mainboard_pre_raminit(&mrc_params);
+
    timestamp_add_now(TS_BEFORE_INITRAM);

ps = fill_power_state();
@@ -226,13 +209,24 @@
    	boot_count_increment();
 #endif

-
    /* Initialize RAM */
-	raminit(mrc_params, prev_sleep_state);
+	raminit(&mrc_params, prev_sleep_state);

timestamp_add_now(TS_AFTER_INITRAM);

romstage_handoff_init(prev_sleep_state == ACPI_S3);
+
+	platform_enter_postcar();
+
+	/* We don't return here */
+}
+
+/* This wrapper enables easy transition towards C_ENVIRONMENT_BOOTBLOCK,
+ * keeping changes in cache_as_ram.S easy to manage.
+ */
+asmlinkage void bootblock_c_entry_bist(uint64_t base_timestamp, uint32_t bist)
+{
+	romstage_main(base_timestamp, bist);
 }

#define ROMSTAGE_RAM_STACK_SIZE 0x5000

Change in coreboot[master]: soc/intel/baytrail: Place the raminit in a common location

[Arthur Heymans (Code Review)]

Arthur Heymans has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/32968 )

Change subject: soc/intel/baytrail: Place the raminit in a common location
......................................................................

Abandoned