Attention is currently required from: Cliff Huang, Intel coreboot Reviewers, Jayvik Desai, Kapil Porwal, Pranava Y N.
Hello Bora Guvendik, Intel coreboot Reviewers, Jayvik Desai, Kapil Porwal, Pranava Y N, Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/86290?usp=email
to look at the new patch set (#9).
Change subject: soc/intel/pantherlake: Enable multiple ACPI devices for GPIO ......................................................................
soc/intel/pantherlake: Enable multiple ACPI devices for GPIO
In the Panther Lake architecture, each GPIO community functions as a separate pin control entity. Therefore, when specifying a GPIO identifier, one should use the community-specific offset, not the number from the first pad within the GPIO series. This is achieved by selecting the Kconfig option SOC_INTEL_COMMON_BLOCK_GPIO_MULTI_ACPI_DEVICES within the Panther Lake SOC Kconfig file.
The numbers within the _CRS GpioInt and GpIo objects in the SSDT should be offsets within the community. The GPIO identifier employed should correspond to the offset from the respective community.
Let's take an example. In the fatcat board overridetree.cb, ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E19) points to GPIO Group E. The pad starts at 74. It is inside community 1, which starts at 48. The correct GPIO reference is (19 + 74) - 48 = 45, or 0x002D in hexadecimal.
Here are two notable changes in the fatcat board SSDT introduced by this commit.
- ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E19)
"\_SB.PCI0.GPI1", 0x00, ResourceConsumer, , ) { // Pin list - 0x0033 + 0x002D } }) Name (_DSD, Package (0x02) // _DSD: Device-Specific Data
- ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A16)
"\_SB.PCI0.GPI3", 0x00, ResourceConsumer, , ) { // Pin list - 0x0050 + 0x003B } }) Name (_DSD, Package (0x02) // _DSD: Device-Specific Data
This change is verified via S0ix in Google Fatcat board with touchscreen/touchpad attached as the wake source.
BUG=none TEST=Check the number from CRS GpinInt and GpIo objects in the SSDT, and ensure that the GPIO number used matches the community offset.
Signed-off-by: Cliff Huang cliff.huang@intel.com Change-Id: Ic2ba67518fa173e13975478ccae5f8a1772ebf08 --- M src/soc/intel/pantherlake/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/86290/9